Method and apparatus for reinforcing a prefetch chain

[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 09/999,518, entitled Method and Apparatus for Content-Aware Prefetching, and Ser. No. 10/000,549, entitled Method and Apparatus for Identifying Candidate Virtual Addresses in a Content-Aware Prefetcher, both of which were filed on Nov. 30, 2001.

[0002] Embodiments of the invention relate generally to prefetching within the memory hierarchy of a processor and, more particularly, to a method and apparatus for reinforcing a prefetch chain.

[0003] A conventional processor typically operates at a much faster speed than the main memory to which the processor is coupled. To overcome the inherent latency of main memory, which usually comprises dynamic random access memory (DRAM), a memory hierarchy is employed. The memory hierarchy includes one or more levels of cache, each cache comprising a relatively fast memory device or circuitry configured to hold data recently accessedor expected to be accessedby the processor. The purpose of the cache is to insure most data needed by a processor is readily available to the processor without accessing the main memory, as the process of accessing main memory is very slow in comparison to the speed of the processor or the speed at which the processor can access a cache.

[0004] Typically, a memory hierarchy comprises multiple levels of cache, wherein each level is faster than next lower level and the level closest to the processor exhibits the highest speed and performance. A cache may be located on the processor itselfi.e., an on-chip cacheor a cache may comprise an external memory devicei.e., an offchip cache. For example, a processor may include a high level on-chip cacheoften times referred to as an L1 cachewherein the processor is coupled with a lower level off-chip cachewhich is often referred to as an L2 cache. Alternatively, a processor may include an on-chip L1 cache, as well as an on-chip L2 cache. Of course, a memory hierarchy may include any suitable number of caches, each of the caches located on-chip or off-chip.

[0005] As noted above, each level of cache may hold data recently accessed by the processor, such recently accessed data being highly likelydue to the principles of temporal and spatial localityto be needed by the processor again in the near future. However, system performance may be further enhancedand memory latency reduced by anticipating the needs of a processor. If data needed by a processor in the near future can be predicted with some degree of accuracy, this data can be fetched in advanceor prefetchedsuch that the data is cached and readily available to the processor. Generally, some type of algorithm is utilized to anticipate the needs of a processor, and the value of any prefetching scheme is dependent upon the degree to which these needs can be accurately predicted.

[0006] One conventional type of prefetcher is commonly known as a stride prefetcher. A stride prefetcher anticipates the needs of a processor by examining the addresses of data requested by the processori.e., a demand loadto determine if the requested addresses exhibit a regular pattern. If the processor (or an application executing thereon) is stepping through memory using a constant offset from address to addressi.e., a constant stridethe stride prefetcher attempts to recognize this constant stride and prefetch data according to this recognizable pattern. Stride prefetchers do, however, exhibit a significant drawback. A stride prefetcher does not function well when the address pattern of a series of demand loads is irregulari.e., there is not a constant stridesuch as may occur during dynamic memory allocation.

[0007] Another method of data prefetching utilizes a translation look-aside buffer (TLB), which is a cache for virtual-to-physical address translations. According to this method, the fill contentsi.e., the requested dataassociated with a demand load are examined and, if an address-sized data value matches an address contained in the TLB, the data value likely corresponds to a pointer loadi.e., a demand load in which the requested data is an address pointing to a memory locationand is, therefore, deemed to be a candidate address. A prefetch request may then be issued for the candidate address. Because the contents of the requested dataas opposed to addresses thereofare being examined, this method may be referred to as content-based, or content-aware, prefetching. Such a content-aware prefetching scheme that references the TLB (or, more generally, that references any external source or index of addresses) has a significant limitation: likely addresses are limited to those cached in the TLB, and this constraint significantly reduces the number of prefetch opportunities. Also, this content-aware prefetching scheme requires a large number of accesses to the TLB; thus, additional ports must be added to the TLB to handle the content prefetcher overhead.

[0008] FIG. 1 is a schematic diagram of an exemplary embodiment of a system including a processor having a content prefetcher.

[0009] FIG. 2 is a schematic diagram of an exemplary embodiment of a processor including an embodiment of a content prefetcher having a virtual address predictor.

[0010] FIG. 3 is a flow chart illustrating an embodiment of a method of content-aware prefetching.

[0011] FIG. 4 is a flow chart illustrating another embodiment of the method of content-aware prefetching.

[0012] FIG. 5 is a flow chart illustrating a further embodiment of the method of content-aware prefetching.

[0013] FIG. 6 is a flow chart illustrating an embodiment of a method of identifying candidate virtual addresses.

[0014] FIGS. 7 through 9 are schematic diagrams, each further illustrating the method shown in FIG. 6.

[0015] FIG. 10 is a schematic diagram illustrating an embodiment of a process for comparing an address-sized word in a cache line with the cache line's effective address.

[0016] FIG. 11 is a flow chart illustrating another embodiment of the method of identifying candidate virtual addresses.

[0017] FIG. 12 is a schematic diagram illustrating another embodiment of the process for comparing an address-sized word in a cache line an effective address thereof.

[0018] FIG. 13 is a flow chart illustrating a further embodiment of the method of identifying candidate virtual addresses.

[0019] FIG. 14 shows a schematic diagram illustrating a linked data structure with no reinforcement of prefetch chains.

[0020] FIG. 15 is a flow chart illustrating an embodiment of a method of reinforcing a prefetch chain.

[0021] FIGS. 16A-16C show schematic diagrams illustrating the embodiment of the method of reinforcing a prefetch chain shown in FIG. 15.

[0022] FIG. 17 is a flow chart illustrating another embodiment of the method of reinforcing a prefetch chain.

[0023] FIG. 18 is a flow chart illustrating a further embodiment of the method of reinforcing a prefetch chain.

[0024] FIGS. 19A-19B show schematic diagrams illustrating the embodiment of the method of reinforcing a prefetch chain shown in FIG. 18.

[0025] Referring to FIG. 1, a system 100 includes a bus 110 having a processor 200 coupled therewith. The processor 200 may comprise any suitable processing device or circuitry. In one embodiment, as will be discussed below, the processor 200 includes only on-chip cache. However, in an alternative embodiment, the processor 200 may include off-chip cache 170which may be provided alone or in combination with on-chip cachecoupled with the processor 200.

[0026] A main memory 120 is coupled with the bus 110, the main memory 120 comprising, for example, dynamic random access memory (DRAM). The main memory 120 may contain data and/or instructions to be used by the processor 200 while executing an application. A read only memory (ROM) 130 may also be coupled with the bus 110. The ROM 130 may store instructions for execution on processor 200. Further, a data storage device 140, such as a hard disk drive or other suitable non-volatile memory, may be coupled with the bus 110.

[0027] The system 100 may also include one or more output devices 150 coupled with the bus 110. Common output devices 150 include video monitors, printers, and audio output devices (e.g., a sound card and/or speakers). The system 100 may further include one or more input devices 160 coupled with the bus 110. Typical input devices include keyboards, pointing devices such as a mouse, as well as scanners and other data entry devices. It should be understood that the system 100 may include other components in addition to those illustrated in FIG. 1, which have been omitted for clarity, including a removable storage media (e.g., floppy disk drive, CD-ROM drive), a network interface, a chip set coupled with the processor, as well as additional signal lines and busses.

[0028] Referring now to FIG. 2, the processor 200 includes a CPU (central processing unit) core 210. Coupled with the CPU core 210 is a first level on-chip cache, or L1 cache, 220. A second level on-chip cache, or L2 cache, 230 is also disposed in the processor 200. An arbiter, which will be referred to herein as the L2 arbiter 240, is coupled with each of the L1 and L2 caches 220, 230. Another arbiter, which will be referred to herein as the bus arbiter 250, is coupled with the L2 cache. The bus arbiter 250 is also coupled with a bus interface unit 260. The bus interface unit 260 couples the processor 200 with bus 110, thereby enabling communication between processor 200 and main memory 120. The L1 and L2 caches 220, 230 may each comprise any suitable type of memory or circuitry.

[0029] The L1 cache 220 and L2 cache 230, in conjunction with main memory 120, provide a memory hierarchy for CPU core 210. Generally, the L1 cache 220 exhibits the highest speed relative to the CPU core 210, whereas the main memory 120 exhibits the lowest relative speed. The L2 cache 230 operates much faster than the main memory 120, but may be slower than L1 cache 220. The data storage device 140 (see FIG. 1) may also be considered a part of the memory hierarchy, the data storage device 140 being the slowest element in the hierarchy. Each of the L1 and L2 caches 220, 230 store data and/or instructions recently accessed, or expected to be accessed, by CPU core 210.

[0030] During operation, if the CPU core 210 request datai.e., a demand load or a demand requestthe L1 cache 220 is accessed to determine whether it contains the requested data and, if so, the data is provided to the CPU core 210. If the L1 cache 220 does not contain the requested datai.e., a cache missthe demand request is passed to the L2 arbiter 240. The L2 arbiter 240 then provides the demand request to the L2 cache 230, and the L2 cache 230 is accessed to determine whether it contains the requested data. If the L2 cache 230 contains the requested data, the requested datai.e., the fill contentis forwarded to the L1 cache 220 and on to the CPU core 210. If the demand load is not met by the L2 cache 230, the load is passed to the bus arbiter 250. The bus arbiter 250 will transmit the demand request off-chip to main memory 120. If the main memory 120 holds the requested data, the fill content is passed up the memory hierarchy to the CPU core 210. If the main memory 120 can not satisfy the demand request, data storage device 140 may be accessed. Each of the L2 and bus arbiters 240, 250 includes a buffer memory, and the L2 and bus arbiters 240, 250 may buffer a demand request if multiple loads are in progress. During memory request arbitration, the L2 and bus arbiters 240, 250 may also buffer prefetch requests, as will be explained below.

[0031] A process executing in CPU core 210 may access a virtual address space. Typically, such a virtual address space is maintained by a memory management unit, or MMU (not shown in figures). To access virtually addressed data, the virtual address (or addresses) must be mapped to a physical addressi.e., an actual location in main memory 120. Thus, it should be understood that, as data traverses the memory hierarchy, the data may undergo a virtual-to-physical address translation. For example, the L1 cache 220 may be virtually indexed and the L2 cache 230 physically indexed; therefore, if there is a cache miss at L1 cache 220, a virtual-to-physical address translation is required before accessing the L2 cache 230.

[0032] As suggested above, system performance can be enhanced by anticipating the needs of CPU core 210 and prefetching any data that is likely to be imminently requested by the CPU core 210. The processor 200 may include a stride prefetcher 270 coupled with the L2 arbiter 240 and L2 cache 230. The stride prefetcher 270 monitors the L1 miss traffici.e., demand loads that have missed at L1 cache 220as well as the L2 miss traffici.e., demand loads that have missed at L2 cache 230and attempts to detect a constant stride in the requested addresses. If a constant stride is detected, prefetch (PF) requests are provided to the L2 arbiter 240 based upon the detected stride. However, as suggested above, the stride prefetcher 270 does not function adequately when the address pattern of successive demand requests is irregular and there is not a constant stride (e.g., which may occur during dynamic memory allocation).

[0033] The processor 200 also includes a novel content prefetcher 290. The content prefetcher 290 is coupled with the L2 cache 230 and receives a copy of all fill content directed to L2 cache 230, the fill content including one or more cache lines. More generally, however, the content prefetcher 290 may be coupled with any level in the memory hierarchy of a processor and receives a copy of all fill content directed thereto. Further, although the content prefetcher 290 of processor 200 is coupled with an on-chip L2 cache 230, it should be understood that the content prefetcher 290 may also be coupled with an off-chip cache, such as the off-chip cache 170 illustrated in FIG. 1. The content prefetcher 290 is also coupled with the L2 arbiter 240.

[0034] The content prefetcher 290 includes a virtual address predictor 295. As previously described, the content prefetcher 290 receives a copy of each cache line received at L2 cache 230. The virtual address predictor 295 examines a cache line and differentiates candidate virtual addresses from other data values and random bit patterns contained in the cache line without reference to any external address sourcei.e., a TLBwhich may unnecessarily constrain the range of potential addresses and, hence, the potential prefetch opportunities. The virtual address predictor 295 comprises any suitable circuitry and/or instructions capable of identifying candidate virtual addresses in a cache line based upon the data contained in the cache line itself, without accessing an external address reference.

[0035] Operation of the content prefetcher 290 and virtual address predictor 295 may be better understood with reference to a method 300 of content-aware prefetching shown in FIG. 3. Referring to reference numeral 310 in FIG. 3, fill content is received at L2 cache 230. A copy of the fill content is provided to the content prefetcher 290, as denoted at 320. The fill content includes a cache line (or, alternatively, the fill content includes two or more cache lines). As shown at reference numeral 330, the cache line is scanned for candidate virtual addresses. If a candidate virtual address is identified by virtual address predictor 295see reference numeral 340the content prefetcher 290 generates a prefetch request corresponding to the identified candidate virtual address, as illustrated by reference numeral 350. The content prefetcher 290 then provides a the prefetch request to the L2 arbiter 240see reference numeral 360which may buffer and/or issue to main memory 120 a prefetch request based upon memory request arbitration, as will be described below.

[0036] The above-described process is continued until the entire cache line has been scanned. When the entire cache line has been scannedsee reference numeral 370and all candidate virtual addresses contained in the cache line identified, the scan of the cache line is complete, as shown at 380. As will be described in greater detail below, the entire cache lineor a portion thereofmay be scanned in parallel.

[0037] As described above, a copy of all fill content directed to the L2 cache 230 is provided to the content prefetcher 290. Thus, for each demand request issued by the CPU core 210 resulting in a cache miss at L2 cache 230or, more generally, resulting in a cache miss at the level of cache with which the content prefetcher 290 is coupledthe content prefetcher 290 will receive a copy of the requested data. The fill contents associated with demand requests that have missed at some level of cache in the memory hierarchy may be referred to as the demand reference stream. However, other fill content will be directed to the L2 cache 230 as a result of prefetch requests issued by the L2 arbiter 240 (or bus arbiter 250)i.e., the prefetch reference streamand a copy of fill content associated with the prefetch reference stream is also provided to the content prefetcher 290. Thus, by examining fill content associated with the demand reference stream as well as that fill content associated with the prefetch reference stream, the content prefetcher 290 includes a recurrence component and may provide prefetch requests based upon prior prefetch requests. Such a recurrence component allows the content prefetcher 290 to follow a recursive path within a data structure, such as a linked data structure (i.e., a data structure in which each element contains a pointer to the next element of the structure). A prefetch request provided by the content prefetcher 290 based upon a prior prefetch request may be referred to as a chained prefetch request.

[0038] When the L2 arbiter 240 receives a prefetch request from the content prefetcher 290the prefetch request corresponding to a candidate virtual address identified by the virtual address predictor 295the L2 arbiter 240 may buffer the prefetch request and delay it issuance. Buffering of prefetch requests (as well as, in some instances, demand requests) in the L2 arbiter may be (and, in most instances, is) necessary due to the low bandwidth of bus 110 and the slow access speed of main memory 120. Accordingly, the L2 arbiter 240, as well as the bus arbiter 250, may implement a prioritizing scheme to determine which among multiple prefetch requests, as well as multiple demand requests, contained in its buffer should be issued first. This process of prioritizing memory requests and issuing demand or prefetch requests according to each request's priority may be referred to as memory request arbitration.

[0039] Demand requests generally should be accorded the highest priority, as a demand request corresponds to data currently needed by the CPU core 210. Prefetch requests are generally accorded a priority lower than that of demand requests; however, not all prefetch requests in a recursive chain of prefetch requests are as likely to represent data imminently needed by the CPU core 210i.e., they are more speculativeand, therefore, should be assigned differing priorities. That the content prefetcher 290 provides a recursive component providing a chain of prefetchesthe first in the chain based upon the fill content associated with a demand request and each successive prefetch request in the chain based upon the fill content resulting from a previous prefetchleads to the notion of a request depth. If a demand request is, for example, assigned a request depth of zero (0), a prefetch request resulting from the fill content associated with a demand request is assigned a request depth of one (1), and each successive chained prefetch is assigned a request depth equal to one (1) more than the prefetch request upon which the chained prefetch request is based.

[0040] The above-described request depth provides a measure of confidence in a prefetch request and may be used by the L2 arbiter 240, as well as by the bus arbiter 250, during memory request arbitration to determine the priority of a prefetch request. Memory requests with the lowest request depth may be assigned the highest priority and issued first by the L2 arbiter 240 (or bus arbiter 250). Demand requests have a request depth of, for example, zero and are assigned the highest priority. Prefetch requests resulting from fill content associated with a demand load are assigned the next highest priority. A chained prefetch requests is assigned a priority commensurate with its request depth, the assigned priority inversely proportional to the request depth. Accordingly, chained prefetch requests exhibiting a higher request depth are assigned a lower priority, as they are likely to be more speculative. A chained prefetch request having a request depth greater than a predefined thresholda threshold at which confidence in the prefetch request is loware squashed and a prefetch request is not issued by an arbiter. Prefetch requests of the same priority (i.e., the same request depth) are scheduled for issuance by the L2 arbiter 240 (or bus arbiter 250) in a first-come-first-served manner.

[0041] A method 400 of content-aware prefetching and determining a priority of each prefetch request is illustrated in FIG. 4. It should be noted that the method 400 shown in FIG. 4 includes many elements identical to the method 300 of FIG. 3, and like elements retain the same reference numeral in FIG. 4.

[0042] Referring to reference numeral 310 in FIG. 4, fill content is received at L2 cache 230, and a copy of the fill content is provided to the content prefetcher 290 (see reference numeral 320). The fill content includes a cache line (or, alternatively, the fill content includes two or more cache lines). The cache line is then scanned for candidate virtual addresses, as denoted at 330. If a candidate virtual address is identified by virtual address predictor 295see reference numeral 340the content prefetcher 290 generates a prefetch request for that address, as shown at 350.

[0043] Referring now to reference numeral 410 in FIG. 4, the content prefetcher 290 determines a request depth of the prefetch request, as described above. If the request depth is greater than the predefined thresholdsee reference numeral 420the prefetch request is squashed, as denoted at 440. If the request depth does not exceed the predefined threshold, a priority is assigned to the prefetchsee reference numeral 430 wherein the priority is based upon the request depth, as previously described.

[0044] Once a priority is assigned to the prefetch request, the content prefetcher 290 provides the prefetch request to the L2 arbiter 240, as shown at 360. The L2 arbiter 240 enqueues the prefetch request in buffer memory pending memory request arbitration based upon the priority of each prefetch request held in its buffer. Again, demand requests have the highest priority and are issued first by the L2 arbiter 240 (and bus arbiter 250). Prefetch requests, which have a priority lower than demand requests, are issued by the L2 arbiter 240 (or bus arbiter 250) in accordance with their respective priority. Again, the priority of a prefetch request is based upon that prefetch request's request depth. The process is continued until the entire cache line has been scanned and, when the entire cache line has been scanned (see reference numeral 370) and all candidate virtual addresses contained in the cache line identified, the scan of the cache line is complete, as shown at 380.

[0045] A further embodiment of a method 500 of content-aware prefetching is illustrated in FIG. 5. It should be noted that the method 500 shown in FIG. 5 includes many elements identical to the method 300 of FIG. 3, and like elements retain the same reference numeral in FIG. 5. Also, the method 500 of content-aware prefetching is similar to the method 300 illustrated in FIG. 3, and a detailed description of those elements previously described is not repeated.

[0046] Referring to reference numeral 510, if a candidate virtual address has been identified (see reference numeral 340), both of the L2 and bus arbiters 240, 250 are polled to see if a matching memory request is currently in-flighti.e., a memory request corresponding to the candidate virtual address has already been issued. If a matching memory request is in-flight, the prefetch request is squashed, as shown at reference numeral 530. In the event a prefetch request is squashed due to an in-flight memory request, scan of the cache line continues (see reference numerals 330, 370).

[0047] Prefetch requests are enqueued in a memory buffer of the L2 arbiter 240 (or bus arbiter 250) pending memory request arbitration, as previously described. In some instances, the L2 arbiter's buffer may become full. If no buffer space is available in the L2 arbiter 240see reference numeral 520the prefetch request is squashed, as illustrated at reference numeral 530. In the event a prefetch request is squashed due to a lack of available buffer space, the scan of the cache line may continuesee reference numerals 330, 370as memory space may again become available in the L2 arbiter's buffer.

[0048] As set forth above, the virtual address predictor 295 of content prefetcher 290 differentiateswithout reference to an external address source, such as a TLB, which may limit the range of prefetch opportunitiescandidate virtual addresses from data values and random bit patterns contained within a cache line. A method of identifying candidate virtual addresses, as may be implemented by virtual address predictor 295, is now disclosed. It should be noted that the method of identifying candidate virtual addresses looks for virtual addressesas opposed to physical addressesbecause likely addresses contained in fill content directed to the CPU core 210 are in the virtual address space, even though a virtual-to-physical address translation may have taken place within the memory hierarchy.

[0049] The method of identifying candidate virtual addresses is based on the premise that if a pointer loadi.e., a demand load in which the requested data is an address pointing to a memory locationis loaded from memory, there is a strong likelihood that the address of the pointer load will be the effective address of a future demand request. Central to this premise is the idea that the base address of a data structure is provided via a pointer load, and any data value within that structure that shares this base address can be interpreted as a pointer to another member of the same data structure. Assuming that all demand requests potentially include pointer loads, any address-sized word contained within a cache line returned in response to a demand request that shares this base address is deemed a candidate virtual address. If a number of upper bits of the address-sized word match the same number of upper bits in the effective address of the cache line, these matching upper bits suggests that the address-sized word and the effective address of the cache line were computed from the same base address and, therefore, the address-sized word likely corresponds to the effective address of a future demand load.

[0050] An exemplary embodiment of a method 600 of identifying candidate virtual addresses is illustrated in FIG. 6. Referring to reference numeral 610, the virtual address predictor 295 receives a cache line. The cache line is included in fill content received at the content prefetcher 290see FIG. 3, items 310, 320the fill content received at content prefetcher 290 comprising a copy of fill content directed to L2 cache 230, as noted above. The effective address of the cache line is then retrieved, as denoted by reference numeral 620. The cache line is scannedsee FIG. 3, reference numeral 330and an address-sized word is read (or otherwise accessed) from the cache line, as illustrated by reference numeral 630. An address-sized word corresponds to thirty-two (32) bits, or four (4) bytes, for a typical processor; however, an address-sized word may be of any suitable length.

[0051] The process of reading an address-sized word (or words) from a cache line is further illustrated in FIGS. 7 through 9. Referring to FIG. 7, an exemplary cache line 700 comprises sixty-four (64) bytes 705. It should be understood, however, that a cache line may be of any suitable length (e.g., 128 bytes). A first address-sized word 710 (i.e., the first four bytes) may be read from the cache line. A second address-sized word 720 may be read from the cache line, wherein the start of the second address-sized word 720 is separated from the start of the first address sized word 710 by an offset 708 of one (1) byte. Similarly, a third address-sized word 730 may be read from the cache line, the third address-sized word 730 and second address-sized word 720 separated by an offset of one (1) byte. Other address-sized words may be read from the cache line in a similar fashion until the final address-sized word 790 is read from the cache line.

[0052] The process of scanning a cache line illustrated in FIG. 8 is similar to that illustrated in FIG. 7; however, the offset has been increased and the number of address-sized words read from the cache line decreased. A cache line 800 includes, for example, sixty-four (64) bytes 805. Address-sized words 810, 820, 830, . . . 890 are read from the cache line 800, the start of each address-sized word separated from the preceding address-sized word by an offset 808 of two (2) bytes. Thus, the granularity of the cache line scan can be varied by changing the offset 808, 708, thereby altering the number of address-sized words that will be examined. Also, as suggested above, the cache line 800 (or 700) may be scanned in parallel, wherein the entire cache line is scanned at once. It should be understood, however, that when the amount of data that can be read from the cache line is limited by, for example, bus width, the cache line may be scanned in portions, each portion being scanned in parallel.

[0053] Referring to FIG. 9, a cache line 900 comprises sixty-four (64) bytes 905. A first address-sized word 910 is read from the cache line 900, the first address-sized word including the first four bytes of the cache line 900. A second address-sized word 920 is read from the cache line, wherein the start of the second address-sized word 920 corresponds to the end of the first address-sized word 910. Stated another way, the first and second address-sized words 910, 920 are separated by an offset of four (4) bytes, which is also the length of each address-sized word to be read from the cache line 900. A third address-sized word 930 read from the cache line 900 is similarly offset by four bytes from the preceding address-sized word.

[0054] A data structure stored in memory wherein each element of the data structure is read starting at a word boundary is said to be memory aligned or J-byte aligned. For example, the cache line 900 illustrated in FIG. 9 is 4-byte aligned, whereas the cache line 800 of FIG. 8 is 2-byte aligned. As will be explained below, such memory aligned data exhibits certain characteristics which the virtual address predictor 795 may advantageously utilize during operation.

[0055] Referring again to FIG. 6, once an address-sized word has been read from the cache line, a certain number of the upper bits of the address-sized word are compared against the same number of upper bits in the effective address of the cache line, as denoted at 640. Specifically, an N number of the upper bits of the address-sized word are compared with the upper N bits of the effective address of the cache line. This process is better illustrated with reference to FIG. 10. The upper N bits of the effective address 1010 of a cache line are compared against the upper N bits of an address-sized word 1020 contained in the cache line. The upper N bits of each of the effective address 1010 and the address-sized word 1020, respectively, may be referred to as the compare bits 1030. The upper N bits, or compare bits 1030, may comprise any suitable number of bits. By way of example, for a 32 bit address-sized word, the N compare bits may comprise between 8 and 12 bits.

[0056] A bit pattern can be interpreted as a pointer load, a data value, or simply random bits. An address-sized word is deemed to be a pointer to a member of a data structure if the upper N bits thereof match the upper N bits of the effective address of the cache line, which suggests that the address-sized word and the effective address of the cache line were computed from the same base address. If the upper N bits of the address-sized word match the upper N bits of the effective address of the cache linesee reference numeral 650the address-sized word is identified as a candidate virtual address, as shown at 660, and the content prefetcher 290 may provide a prefetch request for the identified candidate address (see FIGS. 3 through 5). If the upper N bits do not match, the address-sized word is discarded, as illustrated by reference numeral 670. The above-described processsee reference numerals 630, 640, 650, 660, 670is applied to each address-sized word read from the cache line during the cache line scan.

[0057] A further embodiment of the method of identifying candidate virtual addresses is illustrated in FIG. 11. As previously described, a cache line may be memory aligned. For example, a data structure may be 2-byte aligned, 4-byte aligned, 8-byte aligned, 16 byte aligned, or, more generally, J-byte aligned. If the data in a cache line is J-byte aligned, a certain number of the least significant bits (see FIG. 10, reference numeral 1090) of any candidate virtual address will be zero (0). By way of example, for 2-byte aligned data the least significant bit will be zero, for 4-byte aligned data the two least significant bits will be zero, for 8-byte aligned data the three least significant bits will be zero, and for 16-byte aligned data the four least significant bits will be zero. More generally, for J-byte aligned data, the K least significant bits will be zero. The virtual address predictor 295 can use the assumption of memory aligned data to disqualify candidate virtual address. Assuming memory alignment, if any of the K least significant bits of an address-sized word are non-zero, the address-sized word can be disqualified as a candidate virtual address. Referring to FIG. 11, which illustrates a method 1100 substantially similar to the method 600 shown in FIG. 6 (all like elements retaining the same reference numeral), if any of the K least significant bits of the address-sized word read from the cache line are non-zerosee reference numeral 1110the address-sized word is discarded, as shown at 670.

[0058] The method 600 (as well as the method 1100) of identifying candidate virtual addresses described above generally functions for any bit pattern contained in the upper bits of the effective address of the cache line, with two exceptions: where the upper N bits are all 0's and where the upper N bits are all 1's (in which case a negative number can potentially be misidentified as a candidate virtual address). However, rather than not predicting when the compare bits of an effective address are all 0's or all 1's, additional filter bits can be used in the comparison to distinguish candidate virtual addresses from data values or random bit patterns. Referring to FIG. 12, the compare bits 1230 of an effective address 1210 of a cache line are either all 1's or all 0's. If the upper N bits of an address-sized word 1220 of the cache line match the upper N bits of the effective address (which are either all 1's or all 0's), additional filter bits 1240 of the address-sized word are examined. The filter bits 1240 comprise the next M bits after the upper N bits or compare bits 1230. If the compare bits 1230 are all 0's and a non-zero bit is found in the filter bit range of an address-sized word, or if the compare bits 1230 are all 1's and a non-one bit is found in the filter bit range of the address-sized word, the address-sized word is deemed a candidate virtual address.

[0059] A method 1300 of identifying candidate virtual addresses utilizing filter bits is illustrated in FIG. 13. The method 1300 is similar to the method 600 of identifying candidate virtual addresses shown and described with respect to FIG. 6, and like elements retain the same reference numeral. As shown at reference numeral 610, the virtual address predictor 295 receives a cache line. Again, the cache line is included in a copy of fill content received at the content prefetcher 290. The effective address of the cache line is then retrieved, as shown at reference numeral 620. The cache line is scanned and an address-sized word is read (or otherwise accessed) from the cache line, as denoted by reference numeral 630. Referring to reference numeral 640, the upper N bits of the address-sized word are then compared with the upper N bits of the effective address.

[0060] If the compare bits of the address-sized word and effective address of the cache line matchsee reference numeral 650and the upper N bits of the effective address are all 0'ssee reference numeral 1310the next M filter bits of the address-size word are examined. Referring to reference numeral 1320, if any one of the next M filter bits of the address-sized word is a non-zero bit, the address-sized word is a candidate virtual address (see reference numeral 660). If a non-zero bit is not found in the filter bit range, the address-sized word is discarded, as shown at 670. Similarly, if the compare bits of the address-sized word and effective address matchsee reference numeral 650and the upper N bits of the effective address are all 1'ssee reference numeral 1330the next M filter bits of the address-sized word are examined. As illustrated at reference numeral 1340, if any one of the next M filter bits of the address-sized word is a non-one bit, the address-sized word is a candidate virtual address (see reference numeral 660). If a non-one bit is not found in the filter bit range, the address-sized word is discarded, as denoted at 670.

[0061] The filter bit range may comprise any suitable number of bits. By way of example, for a 32-bit address-sized word, a filter bit range of between 1 and 4 bits is believed suitable. Employing no filter bits would result in no virtual address prediction when the compare bits of the effective address of a cache line are all 0's or all 1's, whereas increasing the number of filter bits relaxes the requirements for potential candidate virtual addresses.

[0062] As described above, if a prefetch request has a request depth that exceeds a predefined threshold request depth, the prefetch request is squashed. Stated another way, if a prefetch request has a request depth that equals the threshold request depth, the fill content associated with that prefetch request is not scanned and, accordingly, any candidate virtual addresses in that fill content would not be identified. Thus, no subsequent prefetch requests (having a request depth greater than the threshold) will be generated from fill content associated with a prefetch request having a threshold request depth. This is shown schematically in FIG. 14, which depicts an instance 1400 of the memory hierarchy.

[0063] Referring to FIG. 14, a first cache line 10a has been retrieved from main memory 120or other element of the memory hierarchyin response to a demand request for data not in cache (i.e., a cache miss). A demand request accompanied by a subsequent cache miss will be referred to herein as a demand miss. Because the cache line 10a is associated with a demand miss (i.e., a failed demand for data specifically requested by CPU core 210), the cache line 10a has a request depth of zero (0). This request depth is stored with the cache line 10a, the request depth typically being stored in a number of status bits associated with the cache line. The cache line 10a includes a number of bytes of data. For example, the cache line 10a may comprise Q bytes of data, including bytes 15a, 15b, . . . , 15q. A typical length for a cache line is 64 bytes; however, the cache line 10a (as well as cache lines 10b through 10j) may be of any suitable length.

[0064] In the example of FIG. 14, the threshold request depth is three (3). The cache line 10a does not exceed this threshold request depth and, accordingly, the content prefetcher 290 scans the cache line 10a for candidate virtual addresses (see FIGS. 3 through 5). A candidate virtual address 90a is identified by content prefetcher 290. The candidate virtual address 90a identifies another cache line 10b, and a prefetch request is issued for this cache line. For ease of understanding, only a single candidate virtual address is shown in cache line 10a (as well as cache lines 10b through 10j); however, it should be understood that a cache line may have multiple candidate virtual address.

[0065] Cache line 10b was prefetched based upon a scan of fill content associated with the demand reference stream; therefore, the cache line 10b has a request depth of one (1). As the request depth of cache line 10b is less than the threshold request depth (i.e., three), a scan of cache line 10b is performed by content prefetcher 290 and a candidate virtual address 90b identified. The candidate virtual address 90b points to a cache line 10c, which is then prefetched. The cache line 10c has a request depth of two (2), since cache line 10c was prefetched based upon a scan of a prior prefetched cache line having a request depth of one (1). Because the request depth of cache line 10c is less than the threshold request depth, the cache line 10c is scanned for candidate virtual addresses.

[0066] Based upon the virtual address scan, cache line 10c is shown to include a candidate virtual address 90c, which address points to a cache line 10d that is then prefetched. The cache line 10d, as well as cache lines 10b and 10c, each include Q-bytes of data (i.e., bytes 15a, 15b, . . . , 15q). Cache line 10d, which was prefetched based upon the scan of a cache line having a request depth of two (2), has a request depth of three (3). Thus, the cache line 10d has a request depth equal to the threshold request depth, and cache line 10d is not scanned for candidate virtual addresses. The chain of prefetches, or prefetch chain, that includes caches lines 10a-d is, therefore, terminated.

[0067] The cache lines 10a through 10d may form part of a linked data structure 5. As illustrated by the instance 1400 of the memory hierarchy shown in FIG. 14, the linked data structure 5 may have other members, including, for example, members 10e, Of, 10g, 10h, 10i, and 10j, as well as other members, each of these members also having Q-bytes of data. The members 10e through 10j of data structure 5 may also include data needed by the CPU core 210; however, because the prefetch chain of the data structure 5 was terminated, the data contained in cache lines 10e-j will not be fetched, absent a demand miss (or misses). Note that cache line 10d includes a candidate virtual address 90d that points to the next member of the data structure 5 (i.e., cache line 10e), but cache line 10d was not scanned for virtual address because the threshold request depth was reached. Thus, the prefetch chain on linked data structure 5 could be said to have prematurely terminated, and the premature termination of a prefetch chain can result in missed prefetch opportunities.

[0068] As previously suggested, an additional demand miss or misses will need to occur in order to prefetch all members (10a-j) of the data structure 5. For example, as illustrated by the instance 1400 of the memory hierarchy shown in FIG. 14, a demand miss may occur for cache line 10e, causing cache line 10e (request depth equal to zero) to be loaded from memory and scanned for candidate virtual addresses. Cache line 10e contains a candidate virtual address 90e. The candidate virtual address 90e points to cache line 10fanother member of data structure 5and cache line 10f is prefetched and subsequently scanned for candidate virtual addresses. Cache line 10f (request depth equal to one) also includes a candidate virtual address 90f that identifies a cache line 10g, which is another member of the linked data structure 5. Cache line 10g (request depth equal to two) is prefetched and scanned for candidate virtual addresses, and a candidate virtual address 90g is found. Virtual address 90g points to a cache line 10h (request depth equal to three), but cache line 10h has a request depth that equals the threshold request depth. Thus, the cache line 10h is not scanned for candidate virtual addresses and the prefetch chain on linked data structure 5 is again terminated.

[0069] The cache line 10h includes a candidate virtual address 90h that identifies another member of the data structure 5i.e., cache line 10ibut cache line 10h has a request depth (i.e., three) equal to the threshold request depth and, therefore, was not scanned. To continue traversing the linked data structure 5i.e., to prefetch other members of the data structure 5 that may be needed by CPU core 210another demand miss (or misses) would have to occur. For example, a demand miss at cache line 10i would cause cache line 10i (having a request depth of zero) to be loaded from main memory 120 (or other element of the memory hierarchy) and scanned for candidate virtual addresses. Cache line 10i includes a candidate virtual address 90i, which address identifies a cache line 90j. A prefetch request may be issued for cache line 90j, which is then loaded from memory and scanned for candidate virtual addresses. Cache line 90j (request depth equal to one) contains a candidate virtual address 90j, which will lead to a subsequent prefetch request, thereby continuing the prefetch chain of data structure 5.

[0070] Although, for the instance 1400 of the memory hierarchy shown in FIG. 14, all members of the linked data structure 5 were prefetched or otherwise retrieved from main memory 120 (or other element of the memory hierarchy), the prefetch chain was twice terminated and two demand misses were incurred to retrieve members 10a-j of the data structure 5. When a demand miss occurs, processor latency is incurred as the CPU core 210 is waiting for any data that is the subject of a demand request. Thus, repetitively terminating the prefetch chain for a linked data structure leads to missed prefetch opportunities and, accordingly, to a higher rate of demand misses and a corresponding decrease in processor efficiency.

[0071] Rather than incur demand misses and, hence, processing latency in order to retrieve all members of a linked data structure that may include data needed, or likely to be needed, by the CPU core 210, it would be desirable to perpetuate, or reinforce, a prefetch chain without incurring a demand miss. Reinforcing a prefetch chain would enable continued traversal of a prefetch chaina prefetch chain that may have been prematurely terminatedif the chain represents data needed by the CPU core 210. Conversely, if a prefetch chain is unlikely to lead to additional data needed by CPU core 210i.e., the data is speculativethe greatest efficiency would be achieved by allowing the prefetch chain to terminate without reinforcement. Stated another way, it is desirable to perpetuate good prefetch chainsi.e., those having data likely to be needed by CPU core 210while allowing bad prefetch chainsi.e., those having highly speculative datato terminate (at the threshold request depth) with no reinforcement.

[0072] Reinforcement is based on the premise that, while no explicit storing is provided for a prefetch chain, the prefetch chain itself is implicitly stored in cache memory (e.g., L1 cache 220 and/or L2 cache 230). Thus, any demand request that hits on a prefetched cache linei.e., a prefetch hitwill provide the content prefetcher 290 with the necessary feedback to perpetuate a prefetch chain. The request depth value assigned to a prefetched cache line is not fixed for the life of the prefetched cache line in memory. If a prefetched cache line is the object of a prefetch hit, that cache line's request depth may be updated to reflect this demand reference to the cache line. Such a reinforcement mechanismwherein a cache line's request depth may be continually updated or promoted in response to a demand reference to that cache lineprovides for the perpetuation of a prefetch chain. For example, applying this reinforcement mechanism, a terminated prefetched chain can be re-established.

[0073] Referring to FIG. 15, an embodiment 1500 of a method of reinforcing a prefetch chain is illustrated. Referring to block 1505, a prefetch (PF) chain is stored in cache (e.g., L2 cache 230 and/or L1 cache 220). The prefetch chain may be terminated i.e., the threshold request depth reachedor the prefetch chain may be openi.e., members are still being added to the prefetch chain. Referring to reference numeral 1510, if a prefetch hit occurs within the prefetch chain, the prefetch chain is reinforced, as shown at block 1515. Referring again to reference numeral 1510, if a prefetch hit has not occurred within the prefetch chain, no new members (e.g., prefetched cache lines) are added to the prefetch chain.

[0074] The method 1500 of reinforcing a prefetch chain may be better understood with reference to the example of FIGS. 16A through 16C. These figures depict the linked data structure 5 (see FIG. 14) at various states in the memory hierarchy. A first instance 1600a of the memory hierarchy is illustrated in FIG. 16A, a second instance 1600b of the memory hierarchy is illustrated in FIG. 16B, and a third instance 1600c of the memory hierarchy is shown in FIG. 16C. For all cache lines 10a-j of data structure 5, only a single candidate virtual addresses is shown. Again, however, it should be understood that any of the cache lines 10a-j may include multiple candidate virtual addresses. Also, for the example of FIGS. 16A-C, the threshold request depth is again set to three (3).

[0075] Referring to FIG. 16A, a demand miss has occurred, causing cache line 10a to be retrieved from main memory 120 (or other element of the memory hierarchy) and stored in cache. The issuance of subsequent prefetch requests has resulted in cache lines 10b, 10c, and 10d being loaded from memory and cached. The cache line 10d has a request depth of three (3), which is equal to the threshold request, thereby terminating the prefetch chain (i.e., cache lines 10a-d). Note that cache line 10e would have a request depth greater than the threshold and, because cache line 10d was not scanned, a prefetch request for cache line 10e has essentially been squashed. Other members 10e-j of the linked data structure 5 have not been prefetched, and one could view those cache lines that have been loaded from memory and cached (i.e., cache lines 10a-d) as having fallen within a prefetch window 1650a.

[0076] Referring to FIG. 16B, a prefetch hit has occurred at cache line 10b (i.e., a demand request has been issued for data contained in cache line 10b). As illustrated in FIG. 15see reference numerals 1510, 1515the prefetch chain will be reinforced to reflect the demand reference to cache line 10b. To reinforce the prefetch chain, the request depth of the hit cache line 10b is promoted to the request depth associated with a demand miss (note that cache line 10b now contains data specifically requested by CPU core 210). Thus, the request depth of cache line 10b is promoted to zero (0). The cache line 10b is then scanned for candidate virtual addresses. It should be understood that cache line 10b is actually being re-scanned, as the result of the initial scani.e., identification of candidate virtual address 90bis not stored in the memory hierarchy (although the cache line 10c corresponding to address 90b is stored in memory).

[0077] Upon scanning cache line 10b, candidate virtual address 90b will be identified, resulting in a prefetch request for cache line 10c. This prefetch request will not propagate past L2 cache 230or, more generally, past the level of cache with which the content prefetcher 290 is coupledbecause the cache line 10c was previously loaded from memory and cached. Cache line 10c was previously cached with a request depth of two (2), and the request depth of cache line 10c is also promoted. Cache line 10c will be promoted to a request depth of one (1), which is one more than the request depth of cache line 10b (promoted to zero). Cache line 10c is then re-scanned for candidate virtual addresses, and candidate virtual address 90c is found. Virtual address 90c points to cache line 90d, which was also previously cached with a request depth of three (3). The request depth of cache line 90d is similarly promoted, such that cache line 90d has a request depth of two (2) (or one greater than the promoted request depth of cache line 10c).

[0078] Referring back to FIG. 16A, the cache line 10d was not scanned during the instance 1600a the memory hierarchy, as this cache line's prior request depth (i.e., three) was equal to the threshold request depth. Thus, the prefetch chain was terminated at cache line 10d, although cache line 10d contains a candidate virtual address pointing to another member (i.e., cache line 10e) of the data structure 5. Returning to FIG. 16B, the cache line 10d is now scanned for the first timeagain, the request depth of cache line 10d is now only two (2), which is less than the threshold request depthand the candidate virtual address 90d identified. In response to identifying the candidate virtual address 90d, a prefetch request is issued for the cache line 10e. Cache line 10e is loaded from memory and stored in cache, thereby reinforcing the prefetch chain for data structure 5. Cache line 10e is assigned a request depth of three (3), which is one greater than the request depth of line 10d, and the prefetch chain is now terminated at cache line 10e. Stated another way, the prefetch window 1650b is now extended to encompasses an additional member (i.e., cache line 10e) of the data structure 5; however, a demand miss was not incurred to fetch the additional member. Thus, reinforcement has enabled the prefetch chain on linked data structure 5 to be perpetuated without incurring demand misses and, therefore, without increasing processor latency.

[0079] Referring now to FIG. 16C, successive prefetch hits have occurred at cache lines 10c and 10d, respectively. In response to each of the prefetch hits at cache lines 10c and 10d, the prefetch chain was reinforced and the request depth of each of lines 10c and 10d was promoted to zero. Reinforcement of the prefetch chain in response to the prefetch hit at cache line 10c expanded the prefetch window 1650c to include cache line 10f, whereas reinforcement of the prefetch chain in response to the prefetch hit at cache line 10d expanded the prefetch window 1650c to include cache line 10 g, where the prefetch chain was again terminated.

[0080] As some later point in time, as also illustrated in FIG. 16C, a prefetch hit occurred at cache line 10e, and the prefetch chain will again be reinforced. The request depth of line 10e is promoted to zero (0), and cache line 10e is re-scanned for candidate virtual addresses. The scan of cache line 10e reveals candidate virtual address 90e, which results in a prefetch request being issued for cache line 10f, the request depth of cache line 10f being promoted to a request depth of one (1). Cache line 10f is also re-scanned for candidate virtual addresses, and the identification of candidate virtual address 90f in cache line 10f will lead to the prefetching of cache line 10g. Cache line 10g, which is promoted a request depth of two (2), is subsequently scanned for candidate virtual addresses. Virtual address 90g is identified in cache line 10 g and, in response, cache line 10h is prefetched. Cache line 10h has a request depth of three (3) and, because the threshold request depth has been reached, the prefetch chain is again terminated. However, the prefetch window 1650c has been extended down to encompass cache lines 10f-h without incurring the latency associated with a demand miss.

[0081] Another embodiment 1700 of the method of reinforcing a prefetch chainas illustrated by the example of FIGS. 16A-Cis shown in FIG. 17. Referring to block 1705, a prefetch hit has occurred. The request depth of the hit cache line is promoted, as shown at block 1710. Generally, the request depth of the hit cache line is promoted to that associated with a demand miss (i.e., a request depth of zero). However, it should be understood that the request depth of a hit cache line may be promoted to any other suitable value (e.g., one). Referring to block 1715, the cache line is then scanned (or re-scanned). Note that, as illustrated in FIG. 2, the content prefetcher 290 may have access to the L1 fill traffic as well as the L1 miss traffic. Thus, a cache line stored in L2 cache 230 and being forwarded to L1 cache 220 in response to a demand request that missed at L1 cache 220 (an L1 miss)i.e., the cache line stored in L2 cache 230 is the subject of a prefetch hitcan be re-scanned during reinforcement.

[0082] Referring to reference numeral 1720, if a candidate virtual address is identified, the request depth of the cache line corresponding to the candidate virtual address is promoted (see block 1730) if this cache line is stored in cache (see block 1725)i.e., the corresponding cache line was the subject of a prior prefetch request and is a member of the prefetch chain. However, if the cache line corresponding to the candidate virtual address is not in cachesee block 1725a prefetch request is issued to prefetch this cache line, as shown at block 1735. Referring to block 1740, a request depth is assigned to (and/or determined for) the prefetched cache line. The request depth to which the cache line is promoted, or the request depth that is assigned, will be one greater than the request depth of the preceding cache line.

[0083] Referring to reference numeral 1745 in FIG. 17, if the request depth (whether promoted or assigned) is less than the threshold request depth, the cache line is scanned for candidate virtual addressessee block 1715and the process repeated for any candidate virtual addresses (see reference numerals 1720, 1725, 1730, 1735, 1740). Referring again to reference numeral 1745, if the request depth equals (or exceeds) the threshold request depth, the prefetch chain is terminated, as illustrated by block 1750. Also, note that if a candidate virtual address is not identified during the scan of a cache linesee reference numeral 1720the prefetch chain is similarly terminated, as shown at block 1750.

[0084] Referring again to block 1735 in FIG. 17, a prefetch request issued for a cache line during reinforcement may match an in-flight memory transaction (i.e., a prior prefetch request was already issued for that cache line). In the event of two such matching memory transactions, the memory transactions are merged to form a single prefetch request. The cache line retrieved from memory based upon this merger of prefetch requests will have a reinforced request depthi.e., a promoted request depth. In other words, reinforcement transactions take precedence over regular memory prefetch transactions.

[0085] A further embodiment 1800 of the method of reinforcing a prefetch chain is illustrated in FIG. 18. The method 1800 of FIG. 18 is similar to the method 1700 shown and described with respect to FIG. 17, and those elements in FIG. 18 that are the same as those illustrated in FIG. 17 have retained the same numerical designation. Further, discussions of those elements described above with respect to FIG. 17 are not repeated in following description of the method 1800 shown in FIG. 18.

[0086] The method 1800 of FIG. 18 incorporates the concept of a scan threshold.If the request depth of a hit cache line is less than the scan threshold, the prefetch chain will not be reinforced and no members (e.g., elements of a linked data structure) will be added to the prefetch chain. Thus, if a hit cache line's request depth is less than the scan threshold, that cache line will not be scanned (or re-scanned) and its request depth will not be promoted. However, if the request depth of a hit cache line is greater than or equal to the scan threshold, promotion will occur and the hit cache line will be scanned for candidate virtual addresses, such that the prefetch chain can be reinforced.

[0087] Referring now to FIG. 18, a prefetch hit has occurred, as shown at block 1705. If the request depth of the hit cache line is less than the scan thresholdsee reference numeral 1805the prefetch chain is not reinforced, as shown at block 1810. Conversely, referring again to reference numeral 1805, if the request depth of the hit cache line is greater than or equal to the scan threshold, the hit cache line's request depth is promoted (see block 1710). The hit cache line is then scanned (or re-scanned), as shown at block 1715, and the process for reinforcing the prefetch chain is performed, as described above (see reference numerals 1720, 1725, 1730, 1735, 1740, 1745, 1750).

[0088] The method 1800 of FIG. 18 may be better understood with reference to the example presented in FIGS. 19A and 19B. These figures depict the linked data structure 5 (see FIGS. 16A-C) at various states in the memory hierarchy. A first instance 1900a of the memory hierarchy is illustrated in FIG. 19A, and a second instance 1900b of the memory hierarchy is illustrated in FIG. 19B. For all cache lines 10a-j of data structure 5, only a single candidate virtual addresses is shown, and, once again, it should be understood that any of the cache lines 10a-j may include multiple candidate virtual addresses. Also, for the example of FIGS. 19A-B, the threshold request depth is again set to three (3), and the scan threshold is set to two (2).

[0089] Referring to FIG. 19A, a demand miss has occurred, causing cache line 10a to be retrieved from main memory 120 (or other element of the memory hierarchy) and stored in cache. The issuance of subsequent prefetch requests has resulted in cache lines 10b, 10c, and 10d being loaded from memory and cached, these cache lines initially having requests depths of one (1), two (2), and three (3), respectively. The prefetch chain has been terminated at cache line 10d, which has a request depth equal to the threshold request depth (i.e., three). Again, note that cache line 10e would have a request depth greater than the threshold and, because cache line 10d was not scanned, a prefetch request for cache line 10e has essentially been squashed. Other members of the linked data structure 10a-10j have not been prefetched, and one those cache lines that have been loaded from memory and cached (i.e., cache lines 10a-d) are encompassed within a prefetch window 1950a.

[0090] Still referring to FIG. 19A, a prefetch hit has occurred at cache line 10b, which has a request depth of one (1). However, because the hit cache line's request depth is less than the scan threshold (i.e., two), the hit cache line's request depth is not promoted and the prefetch chain is not reinforced. Thus, the prefetch window 1950a is not enlarged and no members (of data structure 5) are added to the prefetch chain. The request depth of cache line 10b is unchanged and remains at one (1).

[0091] Referring now to FIG. 19B, a prefetch hit has occurred at cache line 10c. The hit cache line has a request depth of two (2), which equals the scan threshold of two. Thus, the request depth of the hit cache line 10c is promoted (e.g., to zero) and the hit cache line 10c is also scanned for candidate virtual addresses, thereby reinforcing the prefetch chain. The scan of cache line 10c leads to a chain of prefetches that results in cache lines 10e and 10f being added to the prefetch chain, which are within the prefetch window 1950b. The cache line 10f has a request depth of three (3), which is equal to the threshold request depth, and the prefetch chain is again terminated at cache line 10f. However, a demand miss was not incurred to add the additional members (10e, 10f) to the prefetch chain on linked data structure 5.

[0092] The threshold request depth may be set to any suitable value. The threshold request depth provides an indication of the degree to which a prefetch request is speculative, and setting the threshold request depth to high may result in a prefetch window that is highly speculative (i.e., that includes prefetched data unlikely to be needed by the CPU core 210). Efficiency issues should also be considered in setting the threshold request depth. Without reinforcement, a low threshold request depth may lead to premature termination of a prefetch chain and, hence, to missed prefetch opportunities, but the capability to reinforce and re-establish a terminated prefetch chain alleviates the problem of premature termination. However, it is much more desirable to incur a prefetch hit (followed by reinforcement of the prefetch chain) than to incur a demand miss. Thus, the threshold request depth should be set sufficiently large to provide a prefetch window that is likely to include data imminently needed by CPU core 210. Stated another way, the threshold request depth should be set at value that is large enough to provide a prefetch hit efficient prefetch window that results in minimal demand misses, but that is not so large as to cause highly speculative prefetches. A threshold request depth in the range of three (3) to nine (9) is believed suitable.

[0093] The scan threshold will be less than or equal to the threshold request depth. For example, where the threshold request depth is three (3), the scan threshold could be two (2). Similarly, where the threshold request depth is five (5), the scan threshold could be three (3). Efficiency considerations also play a role in selection of the scan threshold, as the scan threshold delays reinforcement until a prefetch chain has been traversed to a request depth equal to the scan threshold, thereby conserving memory resources. However, care should be taken in setting the scan threshold to insure that the CPU core 210 does not have to wait on data that, absent a high scan threshold, would otherwise have been prefetched and timely made available to the CPU core 210.

[0094] Embodiments of a content prefetcher 290 having a reinforcement mechanism and embodiments 1500, 1700, 1800 of a method of reinforcing a prefetch chain having been herein described, those of ordinary skill in the art will appreciate the advantages thereof. Reinforcement of a prefetch chain insures that good prefetch chains are traversed, whereas bad prefetch chains are dropped. Often times, a prefetch chain is prematurely terminated due to the threshold request depth, as well as a other causes, including data losses and/or a full arbiter buffer. The reinforcement mechanism allows such a terminated prefetch chain to be re-established. Further, prefetch chain reinforcement minimizes demand misses and decreases processing latency, thereby improving processor efficiency.

[0095] The foregoing detailed description and accompanying drawings are only illustrative and not restrictive. They have been provided primarily for a clear and comprehensive understanding of the disclosed embodiments and no unnecessary limitations are to be understood therefrom. Numerous additions, deletions, and modifications to the embodiments described herein, as well as alternative arrangements, may be devised by those skilled in the art without departing from the spirit of the disclosed embodiments and the scope of the appended claims.