Impedance adjustment circuit

[0001] The present invention relates to an impedance adjustment circuit which can adjust an input impedance on a data reception side of a data transmission system having a plurality of data transmission channels and. More particularly, this invention relates to an impedance adjustment circuit which is frequently used in a differential output circuit for TMDS (Transmission Minimized Differential Signaling).

[0002] The configuration of a conventional data transmission system for adjusting an input impedance on a data reception side is shown in FIG. 10. In general, when propagation delay times of a transmission line is longer at the leading edge of a signal than at the trailing edge of the signal, the transmission line is treated as a distribution constant line. In this case, it is necessary to considered the influence of noise generated due to reflection or the like.

[0003] FIG. 11 is a diagram showing the configuration of a data transmission system which suppresses reflection. In order to obtain impedance matching, for example, a terminal resistor is used as illustrated in FIG. 11. When there is a match between the output impedance (Z1) of the transmission-side device, characteristic impedance (Z0) of the transmission line, and terminal resistance (ZL), reflection should not occur.

[0004] However, in the conventional data transmission system, data buses of a transmission-side device and a reception-side device are frequently constituted by multi-bit buses such as 8-bit buses or 16-bit buses. For this reason, terminal resistors are added to all the input terminals of the reception-side device. As a result, the number of elements on the substrate disadvantageously increase. Thus, cost of the system increases, and mounting area on the substrate increases.

[0005] On the other hand, when terminal resistors are incorporated in the reception-side device to solve the above problem, the resistors incorporated in the device generally vary in manufacture. For this reason, impedance mismatching caused by the variations in manufacture occurs disadvantageously. In this case, since the resistances have specific values, a problem that this device cannot be used in systems having different characteristic impedances of transmission lines is posed.

[0006] It is an object of this invention to obtain an impedance adjustment circuit which can absorb the variations of internal resisters in manufacture even though terminal resistors are incorporated in a reception-side device and which can realize optimum impedance matching.

[0007] The impedance adjustment circuit according to one aspect of this invention comprises a reception-side semiconductor device including at least a terminal resister, the impedance adjustment circuit achieving impedance matching between the terminal resister and a transmission line; and a reference resistor provided externally to the reception-side semiconductor device, the reference resistor having a first resistance which is in proportion to an impedance of the transmission line. The terminal resistor is constituted by a resistor having a second resistance and an ON resistor of a MOS transistor. Resistance of the terminal resistor is adjusted by referring to the reference resistor.

[0008] The impedance adjustment circuit according to another aspect of this invention comprises a reception-side semiconductor device including at least a terminal resister, the impedance adjustment circuit achieving impedance matching between the terminal resister and a transmission line; and a reference resistor provided externally to the reception-side semiconductor device, the reference resistor having a first resistance which is in proportion to an impedance of the transmission line. The terminal resistor is constituted by an ON resistor of a MOS transistor. Resistance of the terminal resistor is adjusted by referring to the reference resistor.

[0009] Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.

[0010] FIG. 1 is a block diagram showing the concept of an impedance adjustment circuit according to the present invention;

[0011] FIG. 2 is a block diagram showing the configuration of a first embodiment of the impedance adjustment circuit according to the present invention;

[0012] FIG. 3 is a block diagram showing the configuration of a second embodiment of the impedance adjustment circuit according to the present invention;

[0013] FIG. 4 is a block diagram showing the configuration of a third embodiment of the impedance adjustment circuit according to the present invention;

[0014] FIG. 5 is a table showing a relationship between a common potential V(3) and a reference potential Vc;

[0015] FIG. 6 is a graph showing the manner of a variation of a bias voltage V(8);

[0016] FIG. 7 is a block diagram showing the concept of the impedance adjustment circuit according to the present invention;

[0017] FIG. 8 is a block diagram showing the configuration of a fourth embodiment of the impedance adjustment circuit according to the present invention;

[0018] FIG. 9 is a block diagram showing the configuration of a fifth embodiment of the impedance adjustment circuit according to the present invention;

[0019] FIG. 10 is a block diagram showing the configuration of a conventional data transmission system; and

[0020] FIG. 11 is a block diagram showing the configuration a conventional data transmission system which suppresses reflection.

[0021] Embodiments of an impedance adjustment circuit according to the present invention will be described below with reference to the accompanying drawings. The present invention is not limited to these embodiments.

[0022] FIG. 1 is a block diagram showing the concept of an impedance adjustment circuit according to the present invention. Reference numeral denotes a reference resistor additionally attached to a semiconductor device, reference numeral 2 denotes a MOS transistor incorporated in the semiconductor device, and reference numeral 3 denotes a resistor incorporated in the semiconductor device.

[0023] In general, when terminal resistors are incorporated in semiconductor devices, the resistances of the terminal resistors are varied by the variations of the resistors in manufacture. Accordingly, mismatching of characteristic impedances occurs. Even though an output impedance of a transmission-side semiconductor device, a characteristic impedance (Z0) of a transmission line, and a terminal resistor of a reception-side semiconductor device are matched to each other, when the characteristic impedance of the transmission line changes, the semiconductor devices cannot be used.

[0024] In the present invention, the reference resistor 1 having a resistance Rref which is in proportion to the impedance to the transmission line is additionally attached to the reception-side semiconductor device. More specifically, the reference resistor 1 and the internal terminal resistor are matched to each other.

[0025] In order to suppress the variation of the resistor 3, it is assumed that the terminal resistor is constituted by the resistor 3 having a resistance RA and an ON resistor (resistance Ron) of the MOS transistor 2. More specifically, when the terminal resistor is constituted by the resistor 3, the variation of the resistance in manufacture is large. For this reason, the terminal resistor is designed such that the variation is absorbed by the ON resistor of the MOS transistor 2.

[0026] FIG. 2 is a block diagram showing the configuration of a first embodiment of the impedance adjustment circuit according to the present invention. Reference numeral 11 denotes a reference voltage generation section, reference numeral 12 denotes a step-up circuit section, reference numeral 13 denotes an external resistor connection section, reference numeral 14 denotes a first mirror circuit section, and reference numeral 15 denotes a second mirror circuit section.

[0027] Operation of the impedance adjustment circuit will be described below. In the reference voltage generation section 11, even though a variation in power supply voltage, a variation in temperature, and a variation in manufacture occur, an operation is performed such that an almost constant reference voltage Vref can be obtained. In general, a band gap reference circuit is applied.

[0028] In the step-up circuit section 12, a standard voltage Vc (>Vref) is generated by using a reference voltage Vref of an output from the reference voltage generation section 11. In this case, the increased standard voltage Vc is set to be a central voltage (common potential in a differential signal) of a transmission signal amplitude. More specifically, due to the negative feedback principle of an operational amplifier, a connection-point voltage between a resistor having a resistance R(1) and a resistor having a resistance R(2) is equal to the reference voltage Vref. For this reason, when a current flowing in a MOS transistor M(1) is represented by I(1), the standard voltage Vc is expressed by equation (1): $\begin{array}{cc}\begin{array}{c}Vc=\mathrm{Vref}+I\left(1\right)R\left(1\right)\\ =\mathrm{Vref}+\mathrm{Verf}/R\left(2\right)R\left(1\right)\end{array}& \left(1\right)\end{array}$

[0029] This embodiment illustrates a case in which the central voltage of the transmission signal amplitude is higher than the reference voltage Vref.

[0030] In this manner, the standard voltage Vc can be calculated by a ratio of the reference voltage Vref, the resistance R(1), and the resistance R(2). In the semiconductor device, since elements having the same shapes and adjacently arranged in the semiconductor device have almost equal characteristics, as is apparent from equation (1), the standard voltage Vc can be accurately determined like the reference voltage Vref without being influenced by a variation in power supply voltage, a variation in temperature, and a variation in manufacture.

[0031] In the external resistor connection section 13, due to the negative feedback principle of the operational amplifier, a terminal PAD(1) is biased to the standard voltage Vc. Therefore, a current I(2) flowing in a MOS transistor M(2) is expressed by equation (2):

[0032] where Vcc denotes a power supply voltage. The resistance RrefZ0 (reference resistor 1) represents a value which is in proportion to the impedance of the transmission line as described above.

[0033] In the first mirror circuit section 14, a voltage equal to the gate voltage of the MOS transistor M(2) is set to be a gate voltage of a MOS transistor M(3), and the MOS transistor M(3) is biased to a saturation region, so that a current I(3) flowing in the MOS transistor M(3) is equal to the current I(2).

[0034] The drain voltage of the MOS transistor M(3) is equal to the standard voltage Vc due to the negative feedback principle of the operational amplifier. Furthermore, since a resistance RB between the power supply voltage Vcc and the drain voltage of the MOS transistor M(3) is given by:

[0035] according to equation (2), $\begin{array}{cc}\begin{array}{c}RB=\left(Vcc-Vc\right)/I\left(3\right)\\ =\left(Vcc-Vc\right)/I\left(2\right)\\ =\mathrm{Rref}\end{array}& \left(4\right)\end{array}$

[0036] is satisfied. More specifically,

[0037] is satisfied. In this equation, the resistance R(4) is equal to the resistance of the ON resistor of the MOS transistor M(4).

[0038] In the second mirror circuit section 15, a configuration (combination of the MOS transistor 2 and the resistor 3 having the resistance RA) having the same shape as that of a combination of the MOS transistor M(4) and a resistor having a resistance R(3) is arranged adjacent to the first mirror circuit section 14. A voltage equal to the gate voltage of the MOS transistor M(4) is set to be the gate voltage of the MOS transistor 2. Reference symbol PAD(2) denotes an input terminal for a transmission signal of the reception-side semiconductor device, and has an AC potential which is determined by a central voltage (common voltage when a differential signal is used) of a transmission signal amplitude.

[0039] The MOS transistor M(4) and the MOS transistor 2 must be biased to a linear region. In the linear region, an ON resistance Ron of the MOS transistor 2 is given by equation (6):

[0040] where d is a drain, s is a source, and g is a gate.

[0041] In this manner, the terminal resistance (RARon) of this embodiment is equal to the sum of resistances of the MOS transistor M(4) and the resistance R(3). More specifically, in this embodiment, the terminal resistance (RARonZ0) can be made equal to the reference resistance Rref (Z0).

[0042] As described above, in this embodiment, since the terminal resistor is incorporated in the semiconductor device, a reduction in cost of the entire system and a reduction in substrate mounting area can be realized. Since the variations of the terminal resistances are absorbed by using the ON resistor of the MOS transistor, the impedance matching of the system can be kept at the same level as that of a conventional technique using an external resistor. In addition, only one reference resistor which is in proportion to the characteristic impedance of the transmission line is additionally attached, terminal resistors corresponding to all signals on a data bus can be adjusted to be equal to the characteristic impedance of the transmission line. Furthermore, even in a system having a characteristic impedance of a transmission line different from the above characteristic impedance, a semiconductor device need not be designed again, and the semiconductor device can cope with the different characteristic impedance by only changing the value of the reference resistor.

[0043] In the first embodiment described above, a terminal resistor is realized by a pull-up resistor. In contrast to this, in a second embodiment, the terminal resistor is realized by a pull-down resistor.

[0044] FIG. 3 is a block diagram showing the configuration of a second embodiment of the impedance adjustment circuit according to the present invention. In FIG. 3, reference numeral 13a denotes an external resistor connection section, reference numeral 14a denotes a first mirror circuit section, and reference numeral 15a denotes a second mirror circuit section. The same reference numerals as in the embodiment described above denote the same parts in the second embodiment, and a description thereof will be omitted.

[0045] Operation of the impedance adjustment circuit will be described below. In the external resistor connection section 13a, due to the negative feedback principle of an operational amplifier, a terminal PAD(1) is biased to the standard voltage Vc. Therefore, a current I(2) flowing in a MOS transistor M(2) is expressed by equation (7):

[0046] where resistance RrefZ0 represents a value which is in proportion to the impedance of the transmission line.

[0047] In the first mirror circuit section 14a, a voltage equal to the gate voltage of the MOS transistor M(2) is set to be a gate voltage of a MOS transistor M(3), and the MOS transistor M(3) is biased to a saturation region, so that a current I(3) flowing in the MOS transistor M(3) is equal to the current I(2).

[0048] The drain voltage of the MOS transistor M(3) is equal to the standard voltage Vc due to the negative feedback principle of the operational amplifier. Furthermore, since a resistance RB between the power supply voltage Vcc and the drain voltage of the MOS transistor M(3) is given by: $\begin{array}{cc}RB=R\left(3\right)+R\left(4\right),& \left(8\right)\\ \begin{array}{c}RB=Vc/I\left(3\right)\\ =Vc/I\left(2\right)\\ =\mathrm{Rref}\end{array}& \left(9\right)\end{array}$

[0049] is satisfied. More specifically,

[0050] is satisfied. In this equation, the resistance R(4) is equal to the resistance of the ON resistor of the MOS transistor M(4).

[0051] In the second mirror circuit section 15a, a configuration (combination of a MOS transistor 2a and a resistor 3a having the resistance RA) having the same shape as that of a combination of the MOS transistor M(4) and a resistor having a resistance R(3) is arranged adjacent to the first mirror circuit section 14a. A voltage equal to the gate voltage of the MOS transistor M(4) is set to be the gate voltage of the MOS transistor 2a. Reference symbol PAD(2) denotes an input terminal for a transmission signal of the reception-side semiconductor device, and has an AC potential which is determined by a central voltage (common voltage when a differential signal is used) of a transmission signal amplitude.

[0052] The MOS transistor M(4) and the MOS transistor 2 must be biased to a linear region. In the linear region, an ON resistance Ron of the of the MOS transistor 2a is given by equation (6) as in the first embodiment described above.

[0053] In this manner, the terminal resistance (RARon) of this embodiment is equal to the sum of resistances of the MOS transistor M(4) and the resistance R(3). More specifically, in this embodiment, the terminal resistance (RARonZ0) can be made equal to the reference resistance Rref (Z0).

[0054] As described above, in this embodiment, the same effect as that of the first embodiment described above, and a terminal resistor can be realized by a pull-down resistor.

[0055] In a third embodiment, a terminal resistor is realized by a pull-up resistor, and an input impedance Zin is kept constant even though the amplitude (common potential) of an input signal varies.

[0056] FIG. 4 is a block diagram showing the configuration of a third embodiment of the impedance adjustment circuit according to the present invention. In FIG. 4, reference numeral 21 denotes a first source follower amplifier, reference numeral 22 denotes a second source follower amplifier, reference numeral 23 denotes a differential common potential detection section, reference numeral 24 denotes a differential circuit section, reference numeral 25 denotes a common-side current mirror section, reference numeral 26 denotes a Z0 detection section, reference numeral 27 denotes a mirror circuit section, and reference numeral 28 denotes an input impedance section. The same reference numerals as in the first embodiment described above denote the same parts in the third embodiment, and a description thereof will be omitted.

[0057] Operation of the impedance adjustment circuit will be described below. In this embodiment, signal inputs are differential signal inputs, and a differential common potential is detected, so that a bias voltage of an input impedance is adjusted.

[0058] In the first source follower amplifier 21, the voltage levels of the differential input signals are shifted to voltages V(1) and V(2), respectively, such that the voltage levels are matched to an input range of the differential circuit section 24 (to be described later). In the second source follower amplifier 22, a standard voltage Vc received from the step-up circuit section 12 is shifted to a voltage V(4) such that the standard voltage Vc is matched to the input range of the differential circuit section 24 (to be described later). Note that, when the differential input signals satisfy typ conditions, the value of the standard voltage Vc is set such that V(4)Vc is satisfied.

[0059] In the differential common potential detection section 23, in order to detect the amplitude levels of the differential input signals, a common potential V(3) is extracted from the voltages V(1) and V(2). In this case, divided voltages obtained by two resistors having equal resistances R(3) are set as the common potential V(3).

[0060] In the Z0 detection section 26, an impedance Z0 of the transmission line is detected, and a standard current I(4) of this circuit by using an external resistor (having the impedance Z0) which is in proportion to the impedance of the transmission line. More specifically, the source voltage of a MOS transistor M(7) is equal to the standard voltage Vc due to the negative feedback principle of an operational amplifier. Therefore, the standard current I(4) flowing in a MOS transistor M(5) can be expressed by equation (11):

[0061] In the differential circuit section 24, the common potential V(3) and the standard voltage Vc (corresponding to V(4)) are compared with each other, a current value corresponding to the difference between the common potential V(3) and the standard voltage Vc is extracted. That is, the current I(2) corresponding to the common potential V(3) and the current I(3) corresponding to the standard voltage Vc are extracted. More specifically, since I(4)I(4) is satisfied by making the MOS transistors M(5) and M(5) equal to each other in size, equation (12) is satisfied:

[0062] FIG. 5 is a table showing a relationship between the common potential V(3) and the reference potential Vc. In this case, for example,

[0063] (I) when V(3)Vc, I(2)I(3) is satisfied,

[0064] (II) when V(3)>Vc, I(2)>I(3) is satisfied, and

[0065] (III) when V(3)<Vc, I(2)<I(3) is satisfied.

[0066] In this state, a differential voltage Vin between the common potential V(3) and the standard voltage Vc and a differential current Iin between the current value I(2) and the current value I(3) satisfy a relationship expressed by equation (13):

[0067] In the common-side current mirror section 25, the MOS transistors M(3) and M(3) are made equal to each other in size, so that a current value I(3) equal to the current value I(3) corresponding to the standard voltage Vc is flowed in the MOS transistor M(3).

[0068] In the mirror circuit section 27, MOS transistors M(6) and M(6) are made equal to each other in size, so that a current value I(3) equal to the current I(3) corresponding to the standard voltage Vc and the current I(3) is flowed in the MOS transistor M(6) to reflect a variation of a common potential. The size of a MOS transistor M(5) is made the size of the MOS transistor M(5), a current value I(4)/2 which is 2/1 the standard current I(4) is flowed in the MOS transistor M(5) to reflect a variation of the impedance of the transmission line.

[0069] Therefore, in the mirror circuit section 27, a current value I(5) flowing in a MOS transistor M(8) can be expressed by equation (14):

[0070] The relationship between the common potential V(3) and the standard voltage Vc in the mirror circuit section 27 is shown by using FIG. 5. In this case, for example,

[0071] (I) when V(3)Vc, then I(3)I(4)/2 is satisfied,

[0072] (II) when V(3)>Vc, then I(3)<I(4)/2 is satisfied, and

[0073] (III) when V(3)<Vc, then I(3)>I(4)/2 is satisfied.

[0074] When the amplitudes of the differential signal inputs, i.e., the common voltage varies, a voltage Vds of the MOS transistor M(8) varies. When the MOS transistor M(8) is used as a resistor (On resistor having a resistance rds), the MOS transistor M(8) must be biased to a linear region. However, since the MOS has quadratic characteristics, the resistance rds is influenced by a variation of the voltage Vds even in the linear region. For this reason, in the mirror circuit section 27, a bias voltage V(8) must be adjusted.

[0075] More specifically, in the mirror circuit section 27, a contact-point voltage between the resistor having the resistance R(4) and the MOS transistor M(6) is equal to the standard voltage Vc due to the negative feedback principle of an operational amplifier, thereby adjusting the bias voltage V(8). For example, when a resistance RA between the power supply voltage Vcc and the standard voltage Vc is given by RARonR(4), then

[0076] (I) the bias voltage V(8) is determined such that RAZin when V(3)Vc,

[0077] (II) the bias voltage V(8) is increased such that RA>Zin when V(3)>Vc, and

[0078] (III) the bias voltage V(8) is reduced such that RA<Zin when V(3)<Vc.

[0079] FIG. 6 is a graph showing the manner of a variation of the bias voltage V(8). In FIG. 6, the gate voltage of the MOS transistor M(8) is varied by the variation of the bias voltage V(8) by a magnitude corresponding to the variation of the voltage Vds of the MOS transistor M(8), so that the resistance rds is always kept constant.

[0080] In the input impedance section 28, configurations each having the same shape as that of a combination of the MOS transistor M(8) and the resistor having the resistance R(4) are arranged on terminals PAD(1) and PAD(2), respectively. The gate voltages of the respective MOS transistors M(8) are equal to each other.

[0081] In this manner, the same effect as that obtained in the first embodiment described above can be obtained. In addition, even though the amplitudes of the differential signal inputs, i.e., the common voltage varies, the input impedance Zin (terminal resistance) can be kept constant while linking the reference resistor Rref. In particular, in a transmission system using differential signals, an input impedance can be accurately adjusted.

[0082] FIG. 7 is a block diagram showing the concept of the impedance adjustment circuit according to the present invention. In a fourth embodiment, a terminal resistor is realized by a MOS transistor 2.

[0083] FIG. 8 is a block diagram showing the configuration of the fourth embodiment of the impedance adjustment circuit according to the present invention. Reference numeral 14b denotes a first mirror circuit section, and reference numeral 15b denotes a second mirror circuit section. The same reference numerals as in the first embodiment described above denote the same parts in the fourth embodiment, a description thereof will be omitted.

[0084] Operation of the impedance adjustment circuit will be described below. Only different points between the operation of the fourth embodiment and the operation of the first embodiment described above will be described below. In the first mirror circuit section 14b, a voltage equal to a gate voltage of a MOS transistor M(2) is set as a gate voltage of a MOS transistor M(3), and the MOS transistor M(3) is biased to a saturation region to make a current I(3) and a current I(2) flowing in the MOS transistor M(3) equal to each other.

[0085] The drain voltage of the MOS transistor M(3) is equal to a standard voltage Vc due to the negative feedback principle of an operational amplifier. Furthermore, since a resistance between a power supply voltage Vcc and a drain voltage of the MOS transistor M(3), i.e., the resistance of an ON resistor of a MOS transistor M(4) is represented by R(4), $\begin{array}{cc}\begin{array}{c}R5=\left(Vcc/Vc\right)/I\left(3\right)\\ =\left(Vcc/Vc\right)/I\left(2\right)\\ =\mathrm{Rref}\end{array}& \left(15\right)\end{array}$

[0086] is satisfied.

[0087] In the second mirror circuit section 15b, a MOS transistor 2 having the same shape as that of the MOS transistor M(4) is arranged adjacent to the first mirror circuit section 14b. A voltage equal to the gate voltage of the MOS transistor M(4) is set to be a gate voltage of the MOS transistor 2. Reference symbol PAD(2) denotes an input terminal for a transmission signal of a reception-side semiconductor device, and has an AC potential which is determined by a central voltage (common voltage when a differential signal is used) of a transmission signal amplitude.

[0088] In this manner, a terminal resistance (Ron) of this embodiment is equal to the ON resistance of the MOS transistor M(4). More specifically, in this embodiment, the terminal resistance (RonZ0) and the reference resistance Rref (Z0) can be made equal to each other.

[0089] As described above, in this embodiment, the same effect as that obtained in the first embodiment described above. Since the resistance constituting an input impedance is only the ON resistance of the MOS transistor, the mounting area of a semiconductor device can be reduced.

[0090] A fifth embodiment is a case in which the central voltage of a transmission signal amplitude is lower than Vref. In this embodiment, for the sake of descriptive convenience, a configuration will be described as an application of the first embodiment. However, this configuration can also be applied to the second embodiment to the fourth embodiment.

[0091] FIG. 9 is a block diagram showing the configuration of the fifth embodiment of the impedance adjustment circuit according to the present invention. Reference numeral 31 denotes a step-down circuit section. The same reference numerals as in the first embodiment described above denote the same parts in the fifth embodiment, and a description thereof will be omitted.

[0092] Operation of the impedance adjustment circuit will be described below. Only different points between the operation of the fifth embodiment and the operation of the first embodiment described above will be described below. In the step-up circuit section 31, a standard voltage Vc (<Vref) is generated by using an output voltage Vref of a reference voltage generation section 11. More specifically, the standard voltage Vc can be expressed by equation (16):

[0093] In this manner, the standard voltage Vc can be calculated by a ratio of a reference voltage Vref, a resistance R(1), and a resistance R(2). In a semiconductor device, since elements having the same shapes and adjacently arranged in the semiconductor device have almost equal characteristics, as is apparent from equation (1), the voltage Vc can be accurately determined like the reference voltage Vref without being influenced by a variation in power supply voltage, a variation in temperature, and a variation in manufacture.

[0094] As described above, in this embodiment, the same effect as that obtained in the first embodiment described above. Furthermore, even though the amplitude of a transmitted signal is small, an input impedance can be accurately adjusted.

[0095] In the first to fifth embodiments described above, the potential of the standard voltage Vc is set to be the central voltage (common potential when a differential signal is used) of a transmission signal amplitude, and any one of a step-up circuit section and a step-down circuit section is selectively used on the basis of the central voltage and an output voltage from the standard voltage generation section. The present invention is not limited to these embodiments, and a voltage which satisfies VrefVc may be given from an external circuit. In this manner, a standard voltage generation circuit section and the step-down circuit section (or the step-up circuit section) are not required, a circuit scale can be considerably reduced.

[0096] As has been described above, according to the present invention, a reference resistor having a resistance which is in proportion to the impedance of a transmission line is additionally attached to a reception-side semiconductor device. More specifically, the reference resistor and an internal terminal resistor are matched to each other. In order to suppress a variation of a resistor in manufacture, the terminal resistor is constituted by a resistor having a resistance and an ON resistor of a MOS transistor. More specifically, when the terminal resistor is constituted by only a resistor, since the variation of the resistance in manufacture is large, the terminal resistor is designed such that the variation is absorbed by the ON resistor of the MOS transistor. In this manner, even though the terminal resistor is incorporated in the reception-side device, a variation of the internal resistor in manufacture is absorbed, and an optimum impedance can be advantageously realized.

[0097] Furthermore, since the terminal resistor is incorporated in the semiconductor device, a reduction in cost of an entire system and a reduction in substrate mounting area can be advantageously realized. Since a variation of the terminal resistance is absorbed by using the ON resistor of the MOS transistor, impedance matching of the system can be advantageously kept at the same level as that of a conventional technique using an external resistor. Only one reference resistor which is in proportion to the characteristic impedance of the transmission line is additionally attached, terminal resistors corresponding to all signals on a data bus can be advantageously adjusted to be equal to the characteristic impedance of the transmission line. Even in a system having a characteristic impedance of a transmission line different from the above characteristic impedance, a semiconductor device need not be designed again, and the semiconductor device can advantageously cope with the different characteristic impedance by only changing the value of the reference resistor.

[0098] Furthermore, the terminal resistor can be advantageously realized by the pull-down resistor.

[0099] Furthermore, even though the amplitudes of the differential signal inputs, i.e., the common voltage varies, the input impedance (terminal resistance) can be advantageously kept constant while linking the reference resistor. In particular, in a transmission system using differential signals, an input impedance can be advantageously accurately adjusted.

[0100] Furthermore, since the reference voltage generation unit and the voltage control unit is not necessary, a circuit scale can be advantageously considerably reduced.

[0101] Moreover, according to this invention, a reference resistor having a resistance which is in proportion to the impedance of a transmission line is additionally attached to a reception-side semiconductor device. More specifically, the reference resistor and an internal terminal resistor are matched to each other. In order to suppress a variation of a resistor in manufacture, the terminal resistor is constituted by an ON resistor of a MOS transistor. In this manner, even though the terminal resistor is incorporated in the reception-side device, optimum impedance matching can be advantageously realized.

[0102] Furthermore, since the resistor constituting the input impedance is only the ON resistor, the mounting area of the semiconductor device can be advantageously considerably reduced.

[0103] Furthermore, the reference voltage generation unit and the voltage control unit are not necessary, a circuit scale can be advantageously considerably reduced.

[0104] Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.