Thermal interface material and heat sink configuration

[0001] This application claims the benefit of U.S. Provisional Application No. 60/293,457, filed May 24, 2001 and U.S. Provisional Application No. 60/306,218, filed Jul. 18, 2001.

[0002] Thermal interface materials (TIMs) are critical to protect active semiconductor devices, such as microprocessors, from exceeding the operational temperature limit. They enable bonding of the heat generating device (e.g., a silicon semiconductor) to a heat sink or a heat spreader (e.g, copper and/or aluminum components) without creating an excessive thermal barrier. The TIM may also be used in the assembly of other components of the heat sink or the heat spreader stack that comprise the overall thermal impedance path.

[0003] Formation of a small thermal barrier is an important property of a TIM. The thermal barrier can be described in terms of effective thermal conductivity through the TIM and is preferably as high as possible. The effective thermal conductivity of the TIM is primarily due to the interfacial heat transfer coefficient as well as the (intrinsic) bulk thermal conductivity of the TIM. A variety of other properties are also important for a TIM depending on the particular application, for example: an ability to relax thermal expansion stresses when joining two materials (also referred to as compliance), an ability to form a mechanically sound joint that is stable during thermal cycling, a lack of sensitivity to moisture and temperature changes, manufacturing feasibility, and cost.

[0004] Several classes of materials are being currently used as TIMs, for example, thermal greases, thermal gels, adhesives, elastomers, thermal pads, and phase change materials. Although the foregoing TIMs are adequate for many current semiconductor devices, the increased performance of semiconductor devices in the near future will render the presently known TIMs inadequate. Specifically, the thermal conductivity of current TIMs generally does not exceed about 5 W/mK and is typically less than about 1 W/mK. However, TIMs that form thermal interfaces with effective thermal conductivities of about 15 W/mK or greater will soon be needed.

[0005] One alternative to the foregoing TIMs is a solid metal sheet or preform made of indium or other low melting temperature alloys that act as the thermal interface layer. The metal TIMs ensure high thermal conductivity value (e.g., about 80 W/mK for an indium sheet). Metal TIMs may also exhibit a favorable solder or wetting behavior upon reflow which facilitates a low thermal interfacial resistance. During reflow, the solder and substrate are heated, the solder melts and wets by surface tension and/or local surface alloying. The interfaces consist of intermetallics or interdiffused metals with thermal properties that are frequently less desirable than those of the bulk TIM metal but much better than existing (polymer based) TIMs. In most cases, metallic TIMs have to be subjected to reflow in order to form reliable thermal interfaces. Metallic TIMs, however, can fail in certain applications due to the relatively large difference(s) between the coefficients of thermal expansion (CTEs) of the TIM and the semiconductor and/or heat sink components and the lack of compliance.

[0006] The present invention is directed to materials, processes and designs to improve the performance of a semiconductor to heat sink interface thereby increasing the flow of heat from an electronic (heat generating) device. Among the objects and features of the present invention, therefore, is the provision of a TIM which has a high thermal conductivity (e.g., greater than about 15 W/mK); the provision of a TIM which has a high interfacial heat transfer coefficient (i.e., greater than about 50 W/cm² C.); the provision of a TIM with a coefficient of thermal expansion (CTE) that is a compromise between semiconductor devices and heat sink components so that the TIM will resist separation from the semiconductor substrate or the heat sink components or resist damaging the semiconductor substrate; the provision of a TIM with improved resistance to thermal cycling induced stress failure; the provision of a TIM with improved resistance to moisture changes; the provision of a TIM with improved resistance to temperature changes; the provision of a TIM which bonds to a heat sink component and a semiconductor device at a temperature less than the failure temperature of an active (electronic) device; the provision of a TIM which enables bonding to a semiconductor substrate and a heat sink component without the use of a flux (i.e., the TIM preferably comprises a fluxless or active solder); and the provision of a TIM which is readily compatible with active semiconductor device manufacturing processes. In short, the provision of a TIM in which the bulk properties and the interface properties are optimal for heat transfer and reliability.

[0007] Briefly, therefore, the present invention is directed to a thermal interface material comprising a solder and a CTE modifying component.

[0008] The present invention is also directed to an active solder that wets at a temperature below about 300 C. without extrinsic fluxing, the active solder comprises indium and an intrinsic oxygen getter selected from the group consisting of alkali metals, alkaline-earth metals, refractory metals, rare earth metals and zinc and mixtures and alloys thereof.

[0009] Further, the present invention is directed to an active solder that wets at a temperature below about 300 C. without extrinsic fluxing, the solder comprises about 80% by weight gold, and about 20% by weight tin and an intrinsic oxygen getter selected from the group consisting of alkali metals, alkaline-earth metals, refractory metals, rare earth metals and zinc and mixtures and alloys thereof.

[0010] Additionally, the present invention is directed to an electronic device package comprising: a semiconductor substrate having a front surface and a back surface; an electronic device on the front surface of the semiconductor substrate; a heat sink component having a front surface and a back surface; and a thermal interface material bonding the back surface of the semiconductor substrate to the front surface of the heat sink component, the thermal interface material comprising a solder and a CTE modifying component that has a coefficient of thermal expansion that is less than about 10 m/m C.

[0011] The present invention is also directed to an electronic device package comprising: a semiconductor substrate having a front surface and a back surface; an electronic device on the front surface of the semiconductor substrate; a lid having a front surface and a back surface and a recess for receiving an insert; the insert being sized and shaped to fit within the recess in the lid, the insert having a front surface, a back surface, a surface in contact with the lid and a coefficient of thermal expansion that is between about that of the lid and about that of the semiconductor substrate; and a first thermal interface material bonding the back surface of the semiconductor substrate to at least a portion of the front surface of the insert.

[0012] FIG. 1 is a cross-sectional view of a conventional semiconductor device/heat sink configuration.

[0013] FIG. 2 is a cross-sectional view of an embodiment of the semiconductor device/heat sink configuration of the present invention.

[0014] FIG. 3 is a cross-sectional view of an embodiment of the semiconductor device/heat sink configuration of the present invention.

[0015] Improvements in electronic device performance are frequently accompanied by increased power consumption and decreased device size, which independently or cooperatively may result in increased power densities. Therefore, the flow of heat from the operating electronic device must be increased to keep the device below its operational temperature limit. The present invention is directed to high performance TIM materials and processes which increase the flow of heat from an electronic device and designs which improve the semiconductor to heat sink interface.

[0016] I. High Performance Thermal Interface Material

[0017] A. High Effective Bulk Thermal Conductivity

[0018] The high performance TIM comprises a solder that allows the TIM to bond to a substrate. As used herein, the term substrate refers to a semiconductor and/or a heat sink component and/or any other article, device, apparatus, etc. which is joined to another such substrate with the TIM. When thermally processed, the TIM should bond to the substrate at a temperature less than the failure temperature of an active (electronic) device (e.g., below about 350 C., preferably below about 250 C. and more preferably below about 200 C.). The solder melts below the active device failure temperature, wets to the substrate and allows the formation of a chemical and/or mechanical bond between the TIM and the substrate when solidified. In general, the solder melts at a temperature less than about 300 C., preferably less than about 225 C., more preferably less than about 170 C., and still more preferably between about 160 C. and about 115 C.

[0019] The solder may comprise a conventional soldering material which requires an adjustment of the CTE (see infra). For example, the solder may comprise lead, bismuth, tin, gold, silver, gold-tin, gold-silicon, gold-germanium, etc. Preferably, the solder comprises a bonding component with a low melting temperature and a relatively high thermal conductivity compared to conventional TIM materials (less than about 5 W/mK). For example, indium (melting point is about 155 C., thermal conductivity is about 80 W/mK), tin (melting point is about 230 C., thermal conductivity is about 70 W/mK) and mixtures and alloys thereof. In a particularly preferred embodiment, the bonding component consists essentially of indium because of its low melting temperature and its ability to readily wet many oxides, ceramics, and cermets without the use of organic fluxing agents (see infra).

[0020] To further increase the heat flow through the TIM, the TIM may also comprise a thermal conductivity enhancement component. The thermal conductivity enhancement component preferably has a thermal conductivity above about 100 W/mK. Exemplary thermal conductivity enhancement component materials include silver, copper and gold which have thermal conductivities of about 425 W/mK, about 400 W/mK and about 315 W/mK, respectively. Such metals typically have relatively high melting temperatures (e.g., the melting point of silver is about 960 C., copper is about 1,085 C. and gold is about 1,065 C.).

[0021] B. Interfacial Heat Transfer Coefficient

[0022] In addition to increasing the heat flow through the TIM by selecting highly conductive materials (i.e., reducing the intrinsic thermal resistance of the TIM), a significant improvement in the heat flow from the source to substrate is realized by increasing the heat transfer coefficient at the interface. In fact, the resistance to heat flow at such an interface can be up to about two orders of magnitude greater than the resistance of the TIM.

[0023] The primary cause of a low interfacial heat transfer coefficient is often the formation of areas at the interface in which the substrate and the TIM are not in intimate contact. Thus, those areas act as insulation and reduce the heat flow away from the heat source. A secondary cause of reduced heat transfer through the interface is the presence of various intermetallic phases exhibiting higher thermal resistance. Preferably, the interfacial heat transfer coefficient of the TIM is greater than about 50 W/cm² C. and more preferably greater than about 500 W/cm² C.

[0024] Typically, a TIM used to join a semiconductor (or a metalized semiconductor) and a heat sink requires mechanical and/or chemical fluxing to remove oxygen from the surfaces of the TIM, the semiconductor substrate and the heat sink component to activate the joining process and allow the TIM to wet the surfaces. Chemical fluxing is typically used when attempting to join items with conventional solders at temperatures below about 300 C. A typical chemical flux comprises compounds which upon being heated become active and remove surface oxides. However, some of the flux materials do not escape and form insulating pockets or voids at the interfacial region and/or form residues that may be harmful for the operation of the device.

[0025] 1. Active Solders

[0026] In accordance with the present invention, the TIM (including the solder) preferably does not require extrinsic fluxing (i.e., mechanical fluxing and organic and inorganic fluxing compounds are not needed). Rather, the solder in the TIM of the present invention is preferably activated by an intrinsic oxygen getter that is mixed or alloyed with the bonding component. The intrinsic oxygen getter is more reactive with oxygen than the bonding component thereby preventing or minimizing the formation of bonding component-oxygen compounds. Exemplary intrinsic oxygen getters include alkali metals (e.g., Li, Na, and K), alkaline-earth metals (e.g., Mg and Ca), zinc, refractory metals (e.g., Ti, Zr, Hf, Ta, V, and Nb), rare earth metals (e.g., La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy and Yb), and mixtures and alloys thereof (e.g. misch metal which is available, for example, from Alfa Aesar of Ward Hill, Mass., USA at a composition that comprises about 50% by weight Ce, about 22% La, about 18% Nd, about 6% Pr and about 0-4% of Yb, Sm, Gd, Eu, Tb and Dy). Preferably, the total concentration of refractory metals in the solder is less than about 10% by weight, the total concentration of rare earth metals is less than about 5% by weight, and the total concentration of alkali, alkaline-earth and zinc is less than about 20% by weight.

[0027] The selection of the materials and their relative amounts for incorporation in the solder and the thermal conductivity enhancement component will depend upon the nature of materials joined, the necessary effective thermal conductivity and the maximum bonding temperature for the particular application. Additionally, the selection of materials may depend on other factors including material cost, ease of recycle, as well as overall influence on important solder properties such as hardness, modulus of elasticity, ductility, intermetallic phase formation, corrosion resistance, coefficient of thermal expansion, influence on creep resistance and oxide formation.

[0028] In a preferred embodiment, the active solder comprises indium, titanium and misch metal to provide a compliant yet high CTE alloy that is substantially molten above about 157 C. Preferably, it comprises about 0.5 to about 2% by weight Ti and about 0.1 to about 2.0% by weight misch metal with remainder being In. More preferably, it comprises about 1% by weight Ti, and about 0.2% by weight misch metal with the remainder being In. Such a compliant TIM soldered with a very low level of interfacial defects is less likely to fail at the interface as a result of thermal cycling (see infra).

[0029] In yet another preferred embodiment, the active solder is a rigid gold-based solder with a relatively low CTE (about 13-14 m/m C.) that is typically used to attach submounts or secure fiber optics (e.g., gold-tin, gold-silicon and gold-germanium solders). Typically, for gold-tin alloys the concentrations of gold and tin range from about 75 to about 85% by weight and from about 15 to about 25% by weight, respectively. For gold-silicon alloys the concentration of gold is at least about 90% and the concentration of silicon ranges from about 1 to about 5% by weight. For gold-germanium alloys the concentration of gold is at least about 80% and the concentration of germanium ranges from about 5 to about 15% by weight. To provide relatively low melting or reflow temperatures the solder compositions are preferably near the eutectic composition (e.g., the constituents are within about 3% by weight of the eutectic composition). The eutectic compositions are about 80Au-20Sn, about 97Au-3Si and about 88Au-12Ge. The near eutectic gold-tin alloy is particularly preferred for many applications because it is molten above about 280 C. Because these gold-based solders contain significantly less oxidizable material, less intrinsic oxygen getter materials are needed. Specifically, the concentration of intrinsic oxygen getter materials is preferably about half that of the indium based solder. Preferably the total concentration of refractory metals in the solder is less than about 5% by weight, the total concentration of rare earth metals is less than about 3% by weight, and the total concentration of alkali, alkaline-earth and zinc is less than about 10% by weight. More preferably, the total concentration of refractory metals is about 0.5 to about 1.5% by weight, the total concentration of rare-earth metals is about 0.01 to about 0.5% by weight, the total concentration of alkali metals is about 0.1 to about 0.5% by weight , the total concentration of alkaline-earth metals is about 0.1 to about 0.5% by weight, and the total concentration of zinc is about 0.1 to about 0.5% by weight. These lower CTE alloys are also less likely to fail than non-compliant high-CTE alloys at a semiconductor/solder interface as a result of thermal cycling (see infra).

[0030] In addition to eliminating the need for extrinsic fluxing, the active solder and the thermal interface material comprising the active solder are able to wet non-metallic surfaces such as, but not limited to, Si, SiO2, SiN, and II-IV and III-V semiconductor. As a result, wettable metallizations such as, but not limited to, Au, Au/Ni, Ni, Cu, Sn and combinations thereof are not required to be deposited on such non-metallic surfaces before a soldering/bonding operation. This ability to bond to nonmetallic surface provides a significant materials and process benefits.

[0031] The TIM and active solder of the present invention are particularly suited for thermal processing at temperatures below about 300 C. and preferably below about 200 C. However, the TIM and active solder of the present invention may be thermal processed at elevated temperatures (e.g., greater than about 500 C.) to provide more effective wetting (e.g., shorter wetting time).

[0032] In addition to improving solder processes where the heat flow across the interface is critical, the foregoing active solders are particularly useful in the manufacture of opto-electronic packages. Specifically, active opto-electronic packages comprise lasing devices. If the beam intercepts any organic residue from a chemical flux, the laser readily carbonizes the residue which can disable the device. The use of a fluxless soldering process eliminates this potential failure mechanism.

[0033] The active solder may be formed by any available inert melting method such as melting by induction in an inert crucible or by arc melting. The system is evacuated and back filled with a non-reactive inert gas such as argon. The metals are heated preferably above about 1000 C. to ensure adequate dissolution of the alloy constituents. The molten alloy is cast or formed and during cooling the submicron intermetallic precipitates typically form. Frequently, the cooled alloy is mechanically worked into a wire, a tape or a preform for use in the production of the TIM.

[0034] 2. CTE Mismatch

[0035] Another method for maintaining enhanced heat flow through the TIM is to prevent degradation in the intimate contact at the interfacial region over the life of the electronic device. Specifically, the differences between the coefficients of thermal expansion for the various components in an electronic package create stress during thermal cycling which can lead to partial or complete separation at the interfacial region. This problem is particularly acute for TIMs comprising materials with high coefficients of thermal expansion compared to typical semiconductor materials such as silicon, germanium, gallium arsenide, cadmium sulfide and indium antimonide and light emitting diode material including solid state emitters for photonic and fiber optic laser applications (e.g., In/As/GaAs and InAs/Al/Sb). Typically, the bonding component materials and thermal conductivity enhancement component materials have CTEs that are greater than about 16 m/m C. and the substrate material has a CTE less than about 10 m/m C.

[0036] The TIM of the present invention minimizes the negative impact of the CTE mismatch by preferably comprising a CTE modifying component. The CTE modifying component has a CTE that is more compatible with the substrate thereby decreasing the thermal stress upon thermal cycling. The CTE modifying component has a CTE that is preferably less than about 10 m/m C. and more preferably less than about 8 m/m C. Exemplary CTE modifying component materials include beryllium oxide (about 8.8 m/m C.), aluminum oxide (about 6.5-7.0 m/m C.), aluminum nitride (about 4.2 um/m C.), silicon carbide (about 4.0 m/m C.), silicon dioxide (about 0.5 m/m C.), coppertungsten alloys (about 5.6 m/m C.), low expansion iron-nickel alloys commonly referred to as KOVAR or INVAR (about 5.2 m/m C. to about 6.0 m/m C.), low expansion ceramic or glass powders (about 1.0 m/m C. to about 9.0 m/m C.) and mixtures thereof. In a preferred embodiment of the present invention the CTE modifying component comprises low expansion iron-nickel alloys because they have a low or negative CTE, are readily wetted by and incorporated into the solder alloy, have a relatively high thermal conductivity, and have a relatively high ductility which makes them amenable to post-alloying processing (e.g., rolling and extrusion). Preferably, the CTE mismatch between the TIM and the substrate is between about 5 m/m C. and about 30 m/m C. More preferably, the CTE mismatch between the TIM and the substrate is between about 5 m/m C. and about 20 m/m C. Still more preferably, the CTE mismatch between the TIM and the substrate is less than about 10 m/m C. Most preferably, the TIM is tailored for the desired CTE mismatch for the particular application.

[0037] Although the amount of solder and CTE modifying component depends on the particular application, the TIM preferably comprises about 30% to about 90% by volume of solder and about 10% to about 70% by volume of CTE modifying component. More preferably, the TIM comprises about 50% to about 90% by volume of the solder and about 10% to about 50% by volume of the CTE modifying component.

[0038] C. TIM Manufacturing ProcessOptimizing CTE

[0039] The high performance TIM of the present invention may be manufactured and applied to the substrate by any applicable method. For example, the particles of the CTE modifying component may be incorporated into the solder and/or thermal conductivity enhancement component to form a composite TIM. The composite TIM is typically then rolled into a thin sheet preform (e.g., less than 0.25 mm thick). To form the thermal interface, the TIM preform is heated, and while molten, contacted with a substrate and allowed to cool, solidify and bond. Another method is the use of a foil or a mesh of desired thickness comprising a bonding component and/or a thermal conductivity enhancement component in which openings are formed (e.g., by punching or etching) and the openings are filled with the CTE modifying component. For example, an indium-based foil with hexagonally spaced openings may be filled with beryllium oxide. In the case of a copper foil or mesh, the copper is coated with a bonding component such as indium (e.g., by dipping or plating). A suitable diffusion barrier component (e.g., nickel, titanium or other transitional metals) may be required to prevent rapid dissolution of copper into the indium during the melting/bonding process. An additional method is the use of a sponge comprising a bonding component and/or a thermal conductivity enhancement component (e.g., 90% theoretical density) filled with the CTE modifying component. If necessary, the sponge may be cut into thin sheets to achieve the desired thickness.

[0040] Typically, the CTE modifying component particles are pre-wet with a solder to ensure bonding with the bonding component during reflow. Specifically, the CTE modifying component particles are coated with a thin layer of the solder by any appropriate method such as plating, thermal spraying, vacuum deposition or reduction processing.

[0041] II. CTE Mismatch Resistant Semiconductor Substrate/Heat Sink Interface

[0042] The present invention is also directed to an improved interface for connecting the semiconductor substrate and heat sink components, the improved interface reduces or eliminates the negative impact of the CTE mismatch between a TIM and the substrates. Thus, the improved interface increases the critical range of the CTE mismatch.

[0043] Referring now to FIG. 1, the typical semiconductor/heat sink configuration of an electronic device package 1 comprises a semiconductor substrate 2 having a front surface 3 and a back surface 4, an electronic device (not pictured) being located on the front surface, a first thermal interface material 5 which bonds the back surface of the semiconductor substrate 4 to a heat sink component 6 having a front surface 7, the heat sink component comprises a heat exchanger 8 having a back surface 9 and a front surface 10, and optionally, a lid 11 having a back surface 12 and a front surface 13. If the optional lid 11 is included, a second thermal interface material 14 bonds the back surface of the lid 12 to the front surface of the heat exchanger 10. In accordance with the present invention, the above-described high performance thermal interface material may be used to compensate for the CTE mismatch between the substrate and the lid and between the lid and the heat exchanger in such a typical electronic device package.

[0044] Referring now to FIG. 2, the present invention is directed to an electronic device package 1 comprising a semiconductor substrate 2 having a front surface and a back surface, and electronic device (not pictured) on the front surface of the semiconductor substrate. The package also comprises a lid 11 which comprises a recess 15 for receiving an insert 16 which is sized and shape to fit within the recess. In this embodiment, the recess extends inward from the front surface of the lid to a point between the front surface and the back surface of the lid. The insert comprises a front surface 17, a back surface 18, and a surface in contact with the lid 19. The electronic device package further comprises a first thermal interface material 5 which bonds the back surface of the substrate 2 to the front surface of the insert 17. Preferably, the package also comprises a second thermal interface material 14 which bonds the back surface of the lid 12 to the heat exchanger 8. The insert comprises a thermal stress relieving material that has a CTE that more closely matches the CTE of the substrate than does the CTE of the lid (see supra). Stated another way, the CTE of the insert is between the CTE of the lid and the CTE of the substrate. Therefore, the first thermal interface material need only accommodate the relatively small CTE mismatch between the insert and the substrate rather than the larger CTE mismatch between the substrate and the lid. As a result, the greatest CTE mismatch is typically between the insert/lid interface and because the CTE of the insert is typically smaller than that of the lid, the insert can be compression mounted within the lid.

[0045] Referring now to FIG. 3, the recess 15 may extend through the lid 11 (i.e., the recess extends from the front surface to the back surface of the lid) and likewise the insert 16 may extend completely through the lid 11. As a result, the second thermal interface material 14 also bonds the insert 16 to the heat exchanger 8.

[0046] In view of the above, it will be seen that the several objects of the invention are achieved. As various changes could be made in the above compositions and processes without departing from the scope of the invention, it is intended that all matter contained in the above description be interpreted as illustrative and not in a limiting sense.