Multifinger silicon controlled rectifier structure for electrostatic discharge protection

[0001] This patent application claims the benefit of U.S. Provisional Application, serial No. 60/239,203, filed Oct. 10, 2000, the contents of which are incorporated by reference herein.

[0002] This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry and, more specifically, improvements for silicon controlled rectifier (SCR) structures in the protection circuitry of an integrated circuit (IC).

[0003] Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to the high voltages that may be generated by contact with an electrostatic discharge (ESD) event. As such, ESD protection circuitry is essential for integrated circuits. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (a few amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC's and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.

[0004] FIG. 1 depicts a schematic diagram of a prior art multi-fingered SCR ESD protection device 101, which serves as protection circuitry for an integrated circuit (IC) 100. As the distances between the pads (i.e., pad pitches) become smaller the ESD protection circuitry has been provided with multiple SCR fingers. An illustrative prior art integrated circuit 100 includes a SCR protection circuit 101 having multiple SCR fingers, and is illustratively depicted in FIG. 1 having two SCR fingers 102₁ and 102₂. Generally, prior to an ESD event, the SCR fingers are in a nonconductive state. Once the high voltage of an ESD event is encountered, the SCR fingers then change to a conductive state to shunt the current to ground. Each of the SCR fingers maintains this conductive state until the voltage is discharged to a safe level.

[0005] In particular, the SCR protection circuit 101 is connected from a pad 132 to ground 124. The pad 132 is also connected to the protected circuitry of the IC, optionally through a current limiting resistor R_L (not shown). The SCR protection circuit 101 comprises a trigger device 105 (discussed further below), a first SCR 102₁ (i.e., first finger), and a second SCR 102₂ (i.e., second finger). The first SCR 102₁ further comprises a NPN transistor QN1 131₁ and a PNP transistor QP1 132₁. In particular, the SCR protection device 101 includes an anode 122, which is connected to the pad 132 and to one side of a resistor R_n1 142. The resistor R_n1 142 represents the resistance of the N-well, which is seen at the base of the PNP transistor QP1 132₁ of the SCR 102₁, which is discussed in further detail below. Additionally, the anode 122 is coupled to an emitter 108₁ of the PNP transistor QP1 132₁, which is parallel to the N-well resistance R_n1 142₁.

[0006] A first node 134₁ includes the base of the PNP transistor QP1 132₁, the other side of the resistor R_n1 142₁, and the collector 104₁ of the NPN transistor QN1 131₁. A second node 136₁ includes the collector 106₁ of the PNP transistor QP1 132₁, the base of the NPN transistor QN1 131₁, and connects to one side of a resistor R_p1 141₁. The resistor R_p1 141 represents the resistance of the P-well, which is seen at the base of the NPN transistor QN1 of the SCR 102₁ and is discussed in further detail below. The other side of resistor R_p1 141₁ is connected to a third node 124, which is grounded and serves as the cathode of the SCR 102₁. Furthermore, the emitter 112₁ of the NPN transistor QN1 131₁ is also connected to the grounded third node 124.

[0007] A second SCR 102₂ is formed exactly in the same manner as described with regard to the first SCR 102₁. In particular, an emitter 108₂ of a second PNP transistor QP2 132₂ is coupled to the anode 122, which is common to all of the multi-finger SCR's 102 and the pad 132. Furthermore, an emitter 112₂ of a second NPN transistor QN2 131₂ is coupled to the cathode 124, which is common to all of the multi-finger SCR's 102 and ground. In addition, the two fingers 102₁ and 102₂ of the multi-finger SCR protection circuit 101 are coupled together by a common P-substrate and shared N-well regions therein. That is, the bases of the first and second NPN transistors QN1 131₁ and QN2 131₂ are coupled via a P-well coupling resistance R_pc 103_p. Similarly, the bases of the first and second PNP transistors QP1 132₁ and QP2 132₂ are coupled via a N-well coupling resistance R_nc 103_n. The coupling resistances R_pc and R_nc typically have high resistance values in the range of 100 to 2000 Ohms.

[0008] A single triggering device providing a positive trigger current to the trigger gate 105 has been used to turn on all of the SCR fingers 102. Alternatively, a single trigger device providing a negative trigger current to the trigger gate 107 may be used. It has been observed however, that providing the trigger current to the trigger gate 105 (or 107) has not been sufficient to trigger all of the SCR fingers 102 as is discussed below.

[0009] In operation, each protective multi-finger SCR circuit 102, which illustratively comprise the NPN and PNP transistors QN1 131₁ and QP1 132₁, will not conduct current between the anode 122 and the grounded cathode 124. That is, the SCR fingers 102 are turned off, since there is no high voltage (e.g., ESD voltage) applied to the SCR 102, but only the regular signal voltage of the functional parts of the IC. Once an ESD event occurs at the pad 132, a high voltage potential appears on the anode 122. A triggering device senses the high voltage potential and provides a trigger current to the trigger gate 105 and causes the base potential of the NPN transistor QN1 131₁ to rise, which subsequently turns on the NPN transistor QN1 131₁. Furthermore, the collector of the NPN transistor QN1 131₁ is coupled to the base of the PNP transistor QP1 132₁, which turns on the PNP transistor QP1 132₁.

[0010] As such, once the NPN transistor QN1 131₁ is turned on, the collector 104₁ provides the base current to the PNP transistor QP1 132₁. Therefore, the base current of the PNP transistor QN2 132₁ is greater than the base current of the NPN transistor QN1 131₁. Moreover, the current gain of the PNP transistor QP1 132₁ is realized as the QP1 132₁ collector current, which is then fed back to the base of the NPN transistor QN1 131₁, thereby amplifying the base current of the NPN transistor QN1 131₁. Amplification of the base currents in the SCR 102 progressively continues to increase in a feedback loop between both transistors QN1 131₁ and QP1 132₁. Therefore, the conduction in a turned on SCR is also called a regenerative process.

[0011] The SCR 102₁ becomes highly conductive and sustains (i.e., holds) the current flow with a very small voltage drop (i.e., holding voltage) between the anode and cathode (typically, 1-2 V). Accordingly, once the SCR 102₁ is turned on, the current from the ESD event passes from anode 122 to the grounded cathode 124. Once the ESD event has been discharged from the anode 122 to the cathode 124, the SCR 102 turns off because it cannot sustain its regenerative conduction mode.

[0012] There is usually a large voltage difference between the triggering point and holding point. One problem that has been observed is that the multiple SCR fingers 102 do not always trigger. That is, even though the first SCR finger 102₁ may trigger, the other SCR fingers (e.g., SCR 102₂) may not trigger because almost the entire triggering voltage quickly collapses, which fails to enable the other SCR fingers (e.g., SCR 102₂) to reach their trigger voltages. Also the coupling through the relatively high-ohmic resistors Rnc and Rpc is too weak to turn on the other finger(s). In particular, a typical triggering voltage (depending on a trigger device connected to the trigger gate) is in a range of 7-10 volts, while the holding voltage for an SCR is in a range of 1 to 2 volts. If the first SCR finger 102₁ triggers at 7-10 volts and then drops to the holding voltage of 1 to 2 volts, then there is not enough voltage to trigger the other SCR fingers 102. Thus, when the SCR fingers 102 carry large ESD currents, the voltage differences may lead to non-uniform current distribution and premature failure of the SCR fingers 102 and, ultimately, the IC 100 itself.

[0013] Such failure to trigger all of the multiple SCR fingers in an ESD protection device is especially prominent in epitaxial technologies. Specifically, wafers with an epitaxially grown layer of low-doped p material have a very low substrate resistance due to the high-doped p-region underneath the p-epitaxial layer. The objective of epitaxial wafers is to have exceptionally good coupling of the substrate to the ground potential. However, the low substrate resistance makes the triggering of the SCR fingers in an ESD protection circuit difficult. The very good coupling of the substrate to the ground potential impedes the current to flow to the other SCR fingers 102, such that only the first SCR finger 102₁ will trigger, which may result in the remaining portion of the protection circuit 101 from not protecting the IC 100.

[0014] Therefore, there is a need in the art for a multi-fingered SCR protection device having a reliable triggering mechanism.

[0015] The disadvantages heretofore associated with the prior art are overcome by the present invention of an electrostatic discharge (ESD) protection circuit including a silicon controlled rectifier (SCR) having a plurality of SCR fingers. Each SCR finger includes at least one interspersed high-doped first region formed within a first lightly doped region.

[0016] At least one interspersed high-doped second region are formed within a second lightly doped region, where the first and second lightly doped regions are adjacent one another. At least one first trigger-tap is coupled to the second lightly doped region. Additionally, at least one first low-ohmic connection is respectively coupled between the at least one first trigger tap of each SCR finger.

[0017] FIG. 1 depicts a schematic diagram of a prior art multi-fingered SCR included within an integrated circuit to provide ESD protection;

[0018] FIG. 2 depicts an illustrative schematic diagram of a multi-fingered SCR ESD protection device of the present invention;

[0019] FIG. 3 depicts a top view of an embodiment of the multi-fingered SCR ESD protection device of FIG. 2;

[0020] FIG. 4 depicts a cross-sectional view taken along line 4--4 of the multi-fingered SCR ESD protection device of FIG. 3; and

[0021] FIG. 5 depicts a cross-sectional view taken along line 5--5 of the multi-fingered SCR ESD protection device of FIG. 3.

[0022] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

[0023] The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections and layouts of portions of an IC during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. The present invention is described with reference to CMOS devices. However, those of ordinary skill in the art will appreciate that selecting different dopant types and adjusting concentrations allows the invention to be applied to bipolar and other processes that are susceptible to damage caused by ESD.

[0024] FIG. 2 depicts an illustrative schematic diagram embodiment of a multi-fingered SCR ESD protection device 201 of the present invention. The embodiment depicts an integrated circuit (IC) 200 having an IC pad 132 coupled to a trigger device (not shown) and a multi-fingered SCR device 202. An optional current limiting resistor R_L (not shown) may be positioned between the circuitry to be protected and the multi-fingered SCR ESD protection device 201. The triggering device, which senses the ESD voltage and provides a trigger current, and multi-fingered SCR 202 together serve as a protection device for the IC circuitry. In particular, the triggering device and multi-fingered SCR 202 protect the IC circuitry from electrostatic discharges (ESD) that may occur at the pad 132, which is coupled to the IC circuitry. When turned on, the multi-fingered SCR 202 functions as a shunt to redirect any ESD currents from the pad 132 to ground. That is, the multi-fingered SCR 202 quickly dissipates such over-voltage ESD condition.

[0025] In particular, the SCR protection circuit 201 is connected from a pad 132 to ground 124. The SCR protection circuit 201 comprises a first SCR 202₁ (i.e., first finger) and a second SCR 202₂ (i.e., second finger) (collectively SCR fingers 202). The first SCR finger 202₁ further comprises a NPN transistor QN1 231₁ and a PNP transistor QP2 232₁. In particular, the SCR protection device 201 includes an anode 222, which is connected to the pad 132 and to one side of a resistor R_n1 242₁. The resistor R_n1 242₁ represents the intrinsic resistance of the N-well, which is seen at the base of the PNP transistor QP1 of the first SCR finger 202₁. Additionally, the anode 222 is coupled to an emitter 208₁ of a PNP transistor QP1 232₁, which is parallel to the intrinsic N-well resistance R_n1 242₁.

[0026] A first node 234₁ is formed by the base of the PNP transistor QP1 232₁, the other side of the resistor R_n1 242₁, and the collector 204₁ of the NPN transistor QN1 231₁. A second node 236₁ is formed by the collector 206₁ of the PNP transistor QP1 232₁, the base of the NPN transistor QN1 231₁, and one side of a resistor R_p1 241₁. The resistor R_p1 241 represents the intrinsic resistance of the P-well, which is seen at the base of the NPN transistor QN1 of the SCR 202₁. The other side of resistor R_p1 241₁ is connected to a third node 224, which is grounded and serves as the cathode. Furthermore, the emitter 212₁ of the NPN transistor QN1 231₁ is also connected to the grounded third node 224.

[0027] A second SCR 202₂ is formed exactly in the same manner as described with regard to the first SCR 202₁. In particular, an emitter 208₂ of a second PNP transistor QP2 232₂ is coupled to the anode 222, which is common to all of the multi-finger SCR's 202 and the pad 132. Furthermore, an emitter 212₂ of a second NPN transistor QN2 231₂ is coupled to the cathode 224, which is common to all of the multi-finger SCR's 202 and grounded. In addition, the two fingers 202₁ and 202₂ of the multi-finger SCR protection circuit 201 are coupled together by a common P-substrate and shared N-well regions therein as discussed below with regard to FIGS. 3-5. Furthermore, the bases, which are each formed by a P-well of the first and second NPN transistors QN1 231₁ and QN2 231₂, are coupled via a low-ohmic (metal or poly silicon) connection 203_p. Similarly, the bases, which are each formed by a N-well of the first and second PNP transistors QP1 232₁ and QP2 232₂, are coupled via a similar low-ohmic connection 203_n.

[0028] A single triggering device is either connected to a first trigger gate 205 or a second trigger gate 207. The single triggering device, in conjunction with the inventive features as discussed below, is used to proficiently and reliably trigger all of the SCR fingers 202 in the ESD protection device 201.

[0029] FIG. 3 depicts a top view of an embodiment of the multi-fingered SCR ESD protection device 201, and FIG. 4 depicts a cross-sectional view of an embodiment of the multi-fingered SCR ESD protection device 201. FIGS. 3 and 4 should be viewed together. The multi-fingered SCR protection device 201 is formed on a P-substrate 302 having an optional N doped isolation layer N-ISO 404 (see FIG. 4) implanted in a portion of the P-substrate 302. Implanted in the P-substrate layer 302 (or over an optional N-ISO layer 404) are a plurality of P and N wells 306 and 308. In particular, the first SCR finger 202₁ comprises a first P-well 306₁ and first N-well 308₁, which are positioned adjacent to one another to form a junction 307₁ as shown in FIGS. 4 and 5. Additionally, the first P-well 306₁ has a plurality of interspersed first high-doped N regions 310_1-1 through 310_1-4 implanted therein, while the first N-well 308₁ has a plurality of interspersed first high-doped P regions 312_1-1 through 312_1-4 implanted therein.

[0030] Furthermore, where an optional N-ISO layer (see N-ISO layer 404 in FIG. 4) is implanted in the P-substrate 302 beneath the P and N wells 306 and 308, an additional N-well region 314 is provided adjacent to the sides of the P-wells 306. The additional N-well region 314 is provided to isolate the sides of the P-wells 306 from the P-substrate 302. Conversely, when the optional N-ISO layer 404 is not implanted in the P-substrate 302, the additional N-well region 314 is not required.

[0031] Likewise, the second SCR finger 202₂ comprises a second P-well 306₂ and second N-well 308₂, which are also positioned adjacent to one another to form a junction 307₂ as shown in FIGS. 4 and 5. Additionally, the second P-well 306₂ has a plurality of interspersed second high-doped N regions 310_2-1 through 310_2-4 implanted therein, while the second N-well 308₂ has a plurality of interspersed second high-doped P regions 312_2-1 through 312_2-4 implanted therein. It is noted that the P and N wells 306 and 308 of each SCR finger 202 are formed adjacent to each other and form a junction 309 in a similar manner as the junctions 307. For example, the N-well 308₁ of the first SCR finger 202₁ is positioned adjacent to the second P-well 306₂, and so forth for each SCR finger 202 in the protective SCR device 201.

[0032] Referring to FIG. 3, the anode 222 of each SCR finger 202 comprises a plurality of contacts 328_A1 through 328_An, which are coupled together via external wiring 330_A to the pad 132. Furthermore, the anode 222 of each SCR finger 202 is coupled together via external metallic anode connections 324_An. Likewise, the cathode 224 of each SCR finger 202 comprises a plurality of contacts 328_C1 through 328_Cn, which are coupled together via external wiring 330_C to ground. Furthermore, the cathode 224 of each SCR finger 202 is coupled together via external metallic cathode connections 324_Cn. The external, but on-chip wiring 330_A and 330_C and metallic connections 324_An and 324_Cn are preferably fabricated by metallization processes known in the art, where each end of the wire is connected to a single contact 328.

[0033] FIG. 4 depicts a cross-sectional view taken along line 4--4 of the multi-fingered SCR ESD protection device 201 of FIG. 3. The first SCR finger 202₁ is formed by the first P-well 306₁ and first N-well 308₁, having the plurality of alternating first N doped regions (only region 310_1-1 shown) interspersed with a plurality of P doped regions (only region 312_1-1 shown) respectively disposed therein. In particular, the plurality of first P doped regions 312₁, N-well region 308₁, and P-well region 306₁ forms the first PNP transistor QP1 232₁ of the first SCR finger 202₁. Similarly, the plurality of first N doped regions 310₁, P-well region 306₁, and N-well region 308₁ forms the first NPN transistor QN1 231₁ of the first SCR finger 202₁. The intrinsic resistance R_n1 and R_p1 of the N-well 308₁ and P-well 306₁ are also shown as coupled to the bases of the respective transistors QP1 232₁ and QN1 231₁. Typically, the intrinsic resistances R_n1 and R_p1 are in the range of 100 to 2000 Ohms.

[0034] Likewise, the second SCR finger 202₂ is formed by the second P-well 306₂ and second N-well 308₂ respectively having the plurality of second N doped regions 310_2-1 through 310_2-4 interspersed with an alternating plurality of second P doped regions 312_2-1 through 312_2-4 disposed therein. In particular, the plurality of second P regions 312₂, N-well region 308₂, and P-well region 306₂ form the second PNP transistor QP2 232₂ of the second SCR finger 202₂. Similarly, the plurality of second N regions 310₂, P-well region 306₂, and N-well region 308₂ form the second NPN transistor QN2 231₂ of the second SCR finger 202₂. The intrinsic resistance R_n2 and R_p2 of the N-well 308₂ and P-well 306₂ are also shown as coupled to the bases of the respective transistors QP2 232₂ and QN2 231₂. Typically, the intrinsic resistances R_n2 and R_p2 are in the range of 100 to 2000 Ohms. The metallic connections 324_An and 324_Cn externally connect the anodes 222 and cathodes 224 of the first and second SCR fingers 202₁ and 202₂ together.

[0035] The anode 222 and cathode 224 of each SCR finger are formed by the interspersed high-doped P and N regions 312 and 310 respectively disposed in the N-well 308 and P-well 306. For example, the second SCR finger 202₂ in FIG. 3 depicts four P regions 312_2-1 through 312_2-4, which collectively form the anode 222₂. The four P regions 312_2-1 through 312_2-4 are disposed in line in the N-well 308₂ and have 5 exemplary contacts 328 thereon. Similarly, four N regions 310_2-1 through 310_2-4 collectively form the cathode 224₂. The four N regions 310_2-1 through 310_2-4 are disposed in line in the P-well 306₂ and have 5 exemplary contacts 328 thereon. The same interspersed anode 222 and cathode 224 structures are provided for all of the SCR fingers 202 in the ESD protection device 201. Although, the P anode 222 and N cathode 224 are illustratively shown in FIG. 3 as having four regions and each region with 5 contacts, one skilled in the art will understand that the number of regions and contacts is not considered as limiting.

[0036] Disposed between each P region 312_2-1 through 312_2-4 and N region 310_2-1 through 310_2-4 are smaller interspersed high-doped N and P regions (hereinafter called trigger taps 320 and 322). Recall, that a single trigger gate 205 or 207 is used and is coupled to either the base of the NPN transistor QN1 231₁ (in the case of gate G1 205) or the base of the PNP transistor QP1 232₁ (in the case of gate G2 207). In the illustrative embodiment of FIG. 3, three P trigger tap regions 322₂ are disposed between the four N regions 310_2-1 through 310_2-4 in the P-wells 306₁ and 306₂. The three trigger P tap regions 322 correspond to the NPN transistor QN1 231₁ and are being coupled to a trigger device connected at the first trigger gate G1 205 of FIG. 2.

[0037] Similarly, three N trigger tap regions 320₂ are disposed between the four P anode regions 312_2-1 through 312_2-4 in the N-wells 308₁ and 308₂. These N and P trigger taps 320 and 322 respectively form low ohmic connections to and between the N-wells 308_1-2 as well as to and between the P-wells 306_1-2. The three N trigger tap regions 320 correspond to the PNP transistor QP1 232₁ and are coupled to a trigger device connected at the second trigger gate G2 207 of FIG. 2. That is, the P and N trigger taps 322 and 320 serve as first and second SCR trigger gates G1 and G2 205 and 207. The trigger taps 322 and 320 may be alternatively or both used to inject a hole current (at gate G1 205) or an electron current (at gate G2 207) to trigger the SCR.

[0038] It is also noted that where the optional N-ISO layer 404 is implanted in the P-substrate 302, the additional N-well 314 is required adjacent to the P-wells 306. For example, the additional N-well 314 is implanted adjacent to the first P-well 306₁ as shown in FIG. 4, as well as at the ends of the in-line P-wells 306₁ and 306₂, thereby completely isolating the P-wells 306 from the P-substrate 302.

[0039] FIG. 5 depicts a cross-sectional view taken along line 5-5B of the multi-fingered SCR ESD protection device of FIG. 3. FIG. 5 should be viewed along with FIG. 3. In particular, the cross-sectional view shows the first P trigger tap (i.e., SCR trigger gate G1) 322₁ disposed in the first P-well 306₁ and the first N trigger tap (i.e., SCR gate G2) 320₁ disposed in the first N-well 308₁ of the first SCR finger 202₁. Likewise, the second P trigger tap 322₂ is disposed in the second P-well 306₂, while the second N trigger tap 320₂ is disposed in the second N-well 308₂ of the second SCR finger 202₂. An external, but on-chip P-well low-ohmic connector 203_p connects the first P trigger 322₁ of the first SCR finger 202₁ to the second P trigger tap 322₂ of the second SCR finger 202₂. Similarly, an external, but on-chip N-well low-ohmic connector 203_n connects the first N trigger 320₁ of the first SCR finger 202₁ to the second N trigger 320₂ of the second SCR finger 202₂. The P and N-well low-ohmic connections 203_p and 203_n are preferably fabricated from metal (typically aluminum or copper) or poly silicon (e.g., silicided poly silicon) or any other material available in the IC processing technology having a high electrical conductivity. Each end of the P and N-well metallic connections 203_p and 203_n is connected to a single contact 328 disposed over the P and N trigger taps 322 and 320.

[0040] FIG. 2 depicts the schematic representation of the low-ohmic connections 203_n and 203_p between PNP transistors QP1 232₁ and QP2 232₂, and between NPN transistors QN1 231₁ and QN2 231₂, respectively. As such, a single trigger device (e.g., an NMOS device, not shown) is coupled to each P-well 306 of each SCR finger 202 via the low-ohmic connectors 203_p (see also, FIG. 5). That is, a trigger current is injected into each P trigger tap 322₁ and 322₂ in the P-wells 306₁ and 306₂ via the interspersed connectors 203_n and 203_p. It is noted that in the configuration as shown in FIG. 2, a ESD overvoltage condition causes the trigger device (not shown) to provide a positive trigger current at the trigger gate 205 and as such to the base of all NPN transistors QN 231 which turns on the NPN transistor QN 231. Subsequently, the PNP transistors QP 232 of each SCR finger 202 turn on. Accordingly, only the first trigger gate G1 of the SCR finger 202 is used for triggering. As such, the N trigger taps 320 (i.e., second SCR gates G2) are not used for injecting the initial trigger current for triggering the SCR fingers 202. However, the low-ohmic connections 203_n between the N trigger taps 320 closely link the base regions of the PNP transistors QP1 together. As such the connections 203_n and the N trigger taps 320 promote propagating the triggering to all of the SCR fingers 202. This is similar to the injection of the initial trigger current at the first trigger gate G1 205. The current flow in all the SCR fingers 202₁ and 202₂ is increased, thereby providing quicker turn-on time for the entire multi-fingered SCR device 201.

[0041] In a second embodiment, the trigger gate G2 207 is utilized. For example, a PMOS device (not shown) is coupled to the N trigger taps 320 of each SCR finger 202. It is noted that in this second embodiment, a negative current is provided from the trigger device the trigger gate G2 207. This trigger current causes the PNP transistors QP 232 to turn on, which subsequently turns on the NPN transistors QN 231 of each SCR finger 202. When the trigger gate G2 207 is utilized, the trigger current is alternately coupled to the N trigger taps 320, instead of the P trigger taps 322 for the trigger gate G1 205. Accordingly, only the second gate G2 207 of the SCR finger 202 is used for triggering. As such, the N trigger taps 322 (i.e., the first SCR gates G1) are not used for injecting the initial trigger current for triggering the SCR fingers 202. However, the low-ohmic connections 203_p between the P trigger taps 322 closely link the base regions of the NPN transistors QN together. As such the connections 203_p and the P trigger taps 322 promote propagating the triggering to all of the SCR fingers 202. This is similar as the injection of the initial trigger current at trigger gate G2 207. The current flow in all the SCR fingers 202₁ and 202₂ is increased thereby providing quicker turn-on time for the entire multi-fingered SCR device 201.

[0042] The inventive embodiment differs from the prior art of FIG. 1, since there is a direct coupling of the triggering voltage to the bases of, illustratively, each NPN transistor 231, for example, transistors QN1 and QN2 231₁ and 231₂. Additionally, the inventive embodiment provides direct coupling of the PNP transistors of each SCR finger 202 (e.g., QP1 and QP2 232₁ and 232₂). In this manner, the inventive embodiment differs over the prior art because the direct coupling of the P and N well regions 306 and 308 between each SCR finger 202 ensures that if the potential in one well rises (i.e., the P-well 306) or falls (e.g., the N-well 308) from triggering a first SCR finger (e.g., first SCR finger 202₁), then the other SCR fingers 202_n will also trigger. As such, the SCR fingers 202 may carry large ESD current without any significant voltage differences, which could lead to non-uniform current distribution and premature failure.

[0043] It is further noted that the N-ISO layer 404 is optionally provided to isolate the P-wells 306 from the P-substrate 302. Isolating the P-wells 306 from the P-substrate 302 is beneficial because the P-wells 306 may be tied to the same voltage potentials via the connections 203, while being different from the substrate potential normally tied to ground. It is also noted that it is beneficial to use only one trigger device to ensure a well-defined trigger point.

[0044] Although various embodiments that incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.