Drive substrates and display panels

[0001] This application claims priority to Chinese Patent Application No. 202310801687.8, filed on Jun. 30, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to the field of display technologies, and in particular, to drive substrates and display panels.

[0003] During the research and practice of the related art, it is found that when a thin-film transistor of a Mini-LED or Micro-LED panel is a top-gate type, on a condition that the gate of the thin-film transistor operates at a high voltage, such as at a voltage of about 30 volts, a temperature at an area where the thin-film transistor is located may be as high as 150 degrees Celsius. Under such a high-voltage operation, hot carriers in an oxide semiconductor of an active layer will deteriorate, resulting in a shift in a threshold voltage (Vth).

[0004] In view of above, drive substrates are provided according to embodiments of the present disclosure. The drive substrate includes a base, a first gate, a first insulation layer, a first active layer, a second active layer, a second gate, a second insulation layer, an input electrode, and an output electrode. The first gate is disposed on the base. The first insulation layer is disposed on the base and covers the first gate. The first active layer is disposed on the first insulation layer and includes a first channel overlapping the first gate. The second active layer includes a second channel, a first contact portion, and a second contact portion. The second channel includes a first portion and a second portion connected with each other. The first contact portion is connected to a side of the first portion away from the second portion, and the second contact portion is connected to a side of the second portion away from the first portion. The first portion is directly connected to the first channel. The second portion and the first channel are both attached to the first insulation layer. The second portion is disposed on peripheral sides of the first channel and the first gate. The second insulation layer is disposed on the second active layer. The second gate is disposed on the second insulation layer and includes a first sub-gate and a second sub-gate connected with each other. The first sub-gate overlaps the first portion, and the second sub-gate overlaps the second portion. The input electrode is connected to the second contact portion, and the output electrode is connected to the first contact portion.

[0005] Display panels are further provided according to embodiments of the present disclosure. The display panel includes the above-mentioned drive substrate and a light emitting element disposed on the drive substrate, and the light emitting element is connected to the output electrode.

[0014] Technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure. In the present disclosure, unless stated to the contrary, the orientation terms such as “up” and “down” generally refer to up and down in an actual use or working state of the devices, and the terms “inside” and “outside” refer to an outline of an installation.

[0015] Embodiments of the present disclosure provide a drive substrate and a display panel, which will be described in detail below. It should be noted that a description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.

[0016] Referring to FIG. 1, a drive substrate 100 is provided according to an embodiment of the present disclosure. The drive substrate 100 includes a base 11, a first gate 121, a second gate 122, a first insulation layer 131, a first active layer 141, a second active layer 142, a second insulation layer 132, an input electrode 151, and an output electrode 152.

[0017] The first gate 121 is disposed on the base 11. The first insulation layer 131 is disposed on the base 11 and covers the first gate 121. The first active layer 141 is disposed on the first insulation layer 131. The first active layer 141 includes a first channel 41a overlapping the first gate 121.

[0018] The second active layer 142 includes a second channel 42a, a first contact portion 42b, and a second contact portion 42c. The second channel 42a includes a first portion 42a1 and a second portion 42a2 connected with each other. The first contact portion 42b is connected to a side of the first portion 42a1 away from the second portion 42a2. The second contact portion 42c is connected to a side of the second portion 42a2 away from the first portion 42a1. The first portion 42a1 is directly connected to the first channel 41a. The second portion 42a2 and the first channel 41a are both attached to the first insulation layer 131, and the second portion 42a2 is disposed on peripheral sides of the first channel 41a and the first gate 121.

[0019] The second insulation layer 132 is disposed on the second active layer 142.

[0020] The second gate 122 is disposed on the second insulation layer 132. The second gate 122 includes a first sub-gate 22a and a second sub-gate 22b connected with each other. The first sub-gate 22a overlaps the first portion 42a1. The second sub-gate 22b overlaps the second portion 42a2.

[0021] The output electrode 152 is connected to the first contact portion 42b. The input electrode 151 is connected to the second contact portion 42c.

[0022] In the thin film transistor TFT of the drive substrate 100 in the embodiments of the present disclosure, a structure with double-gate and double-active layer is formed by the first active layer 141, the first gate 121, the first sub-gate 22a, and a part of the second active layer 142 in an area adjacent to the output electrode 152, and a structure with single active layer and top gate is formed by the second sub-gate 22b and a part of the second active layer 142 in an area adjacent to the input electrode 151. Since the first gate 121 and the second gate 122 together control the first channel 41a of the first active layer 141 and the first portion 42a1 of the second channel 42a of the second active layer 142, a resistance and a voltage drop of the area are reduced, so that an electric field intensity of the area is weakened during operation, thereby suppressing the movement of the hot carriers and improving the stability of the threshold voltage (Vth) of the thin film transistor TFT.

[0023] In some embodiments, a material of the base 11 include one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene dicarboxylate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, and polyimide or polyurethane.

[0024] In some embodiments, materials of the first active layer 141 and the second active layer 142 may be formed of single crystal silicon, polycrystalline silicon, or oxide semiconductor. The oxide semiconductor may include one of the oxides based on titanium, hafnium, zirconium, aluminum, tantalum, germanium, zinc, gallium, tin or indium, and their composite oxides (such as indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, indium tin oxide, indium zirconium oxide, indium zirconium zinc oxide, indium zirconium tin oxide, indium zirconium gallium oxide, indium aluminum oxide, indium zinc aluminum oxide, indium tin aluminum oxide, indium aluminum gallium oxide, indium tantalum One of germanium tin oxide, indium germanium gallium oxide, titanium indium zinc oxide, and hafnium indium zinc oxide).

[0025] In some embodiments, the materials of the first active layer 141 and the second active layer 142 are both oxide semiconductors.

[0026] In some embodiments, one of the input electrode 151 and the output electrode 152 is a source, and the other is a drain.

[0027] Optionally, in the embodiment, the first contact portion 42b and the first channel 41a are both attached to the first insulation layer 131, and the first contact portion 42b is connected to a lateral surface of the first channel 41a.

[0028] That is to say, the first active layer 141 only includes the first channel 41a. The first active layer 141 and the second active layer 142 share the first contact portion 42b, which may save materials and subsequent doping or ion implantation time.

[0029] In some embodiments, based on an upper surface of the first insulation layer 131, the first contact portion 42b is overlapped with the lateral surface of the first channel 41a, and a height of the first contact portion 42b is greater than a height of the first channel 41a.

[0030] That is, the first contact portion 42b is in oblique contact with the first channel 41a, which increases a contact area and also increases an area of the first contact portion 42b.

[0031] In some embodiments, a resistance value of the first contact portion 42b and a resistance value of the second contact portion 42c are both less than a resistance value of the first channel 41a and less than a resistance value of the second channel 42a.

[0032] Since the resistance value of the first contact portion 42b is less than the resistance value of the first channel 41a and less than the resistance value of the second channel 42a, a resistance value of the first contact portion 42b is less than a resistance value of an overlapping area of the first channel 41a and the second channel 42a, which may improve the conductivity of the thin film transistor TFT.

[0033] In some embodiments, a doping concentration of the first contact portion 42b is greater than a doping concentration of the second contact portion 42c. Such arrangement may have a stronger suppression effect on the carriers. A lower resistance may be achieved by doping more doping ions to the first contact portion 42b.

[0034] In some embodiments, in an orthographic projection of the drive substrate 100, both of a projection of the first sub-gate 22a and a projection of the first gate 121 completely cover a projection of the first channel 41a and a projection of the first portion 42a1. Such arrangement may improve a mobility of the thin film transistor TFT under a joint action of the first gate 121 and the second gate 122.

[0035] In some embodiments, a length of the first channel 41a is 15% to 30% of a length of the second channel 42a. Such arrangement makes a resistance value of an entire channel (the first channel 41a combined with the second channel 42a) presents a decreasing trend from the second portion 42a2 to an overlapping portion (the first portion 42a1 overlapping the first channel 41a) to the first contact portion 42b, which is conducive to weakening the electric field intensity of the area where the output electrode 152 is located without affecting the electric field of the area where the input electrode 151 is located, thereby ensuring the conduction effect of the thin film transistor TFT.

[0036] In some embodiments, the length of the first channel 41a may be 15%, 20%, 25%, or 30% of the length of the second channel 42a.

[0037] In some embodiments, a carrier concentration of the first active layer 141 is less than or equal to a carrier concentration of the second active layer 142. Since the second active layer 142 occupies a higher proportion as the channel, it covers an entire area of the channel and is located on a side of the first channel 41a adjacent to the second gate 122, so the carrier concentration of the second active layer 142 is higher, which may improve the mobility of the thin film transistor TFT.

[0038] On a condition that the thin film transistor TFT is N-type, the carriers are electrons. On a condition that the thin film transistor TFT is P-type, the carriers are holes.

[0039] In some embodiments, the drive substrate 100 may further include a passivation layer 134 and a conductive layer 153. The passivation layer 134 covers the input electrode 151 and the output electrode 152. The conductive layer 153 is disposed on the passivation layer 134 and connected to the output electrode 152.

[0040] In some embodiments, the conductive layer 153 may be served as a bonding pad for bonding a light emitting element.

[0041] In addition, a preparation process of the drive substrate 100 in the above embodiments is as follows.

[0042] Step B11, referring to FIG. 2, a first gate 121, a first insulation layer 131, and a first active layer 141 are sequentially formed on a base 11.

[0043] The first insulation layer 131 covers the first gate 121 and the base 11.

[0044] The first gate 121 may be a single-layer or a multi-layer stacked structure. For example, the first gate 121 may be Mo, Mo/Al, Mo/Cu, MoTi/Cu, MoTi/Cu/MoTi, Ti/Al/Ti, Ti/Cu/Ti, Mo/Cu/IZO, IZO/Cu/IZO, or Mo/Cu/ITO, etc.

[0045] The first insulation layer 131 is a buffer layer, which may be a single-layer or a multi-layer stacked structure, such as SiO_x, Al₂O₃/SiN_x/SiO_x, SiO_x/SiN_x/SiO_x, or the like.

[0046] The first active layer 141 includes an oxide semiconductor, such as IGTO, IGZO, IGO, IZO, AIZO, ATZO, or metal oxides doped with rare earth lanthanides.

[0047] Then a step B12 is subjected.

[0048] Step B12, referring to FIG. 3, a second active layer 142 is formed on the first active layer 141.

[0049] The second active layer 142 includes a second channel 42a, a first contact portion 42b, and a second contact portion 42c. The second channel 42a includes a first portion 42a1 and a second portion 42a2 connected with each other. The first contact portion 42b is connected to a side of the first portion 42a1 away from the second portion 42a2. The second contact portion 42c is connected to a side of the second portion 42a2 away from the first portion 42a1. The first portion 42a1 is directly connected to the first channel 41a. The second portion 42a2 and the first channel 41a are both attached to the first insulation layer 131, and the second portion 42a2 is disposed on peripheral sides of the first channel 41a and the first gate 121.

[0050] In some embodiments, the second active layer 142 includes an oxide semiconductor, such as IGTO, IGZO, IGO, IZO, AIZO, ATZO, or metal oxides doped with rare earth lanthanides.

[0051] Then a step B13 is subjected.

[0052] Step B13, referring to FIG. 4, a second insulation layer 132 and a second gate 122 are sequentially formed on the second active layer 142, and the first contact portion 42b and the second contact portion 42c are conducted by using the second gate 122 as a mask.

[0053] The second gate 122 blocks the first channel 41a and the second channel 42a, and exposes the first contact portion 42b and the second contact portion 42c. Subsequently, the first contact portion 42b and the second contact portion 42c are conducted by ion doping or ion implantation. The doped or implanted ions may be P-type or N-type.

[0054] In some embodiments, a material of the second insulation layer 132 may be SiO_x, Al₂O₃/SiN_x/SiO_x, SiO_x/SiN_x/SiO_x, or the like.

[0055] The second gate 122 may be a single-layer or a multi-layer stacked structure. For example, the second gate 122 may be Mo, Mo/Al, Mo/Cu, MoTi/Cu, MoTi/Cu/MoTi, Ti/Al/Ti, Ti/Cu/Ti, Mo/Cu/IZO, IZO/Cu/IZO, or Mo/Cu/ITO, etc.

[0056] Then a step B14 is subjected.

[0057] Step B14, referring to FIG. 5, an interlayer dielectric layer 133 and a source-drain metal layer are sequentially formed on the second gate 122. The source-drain metal layer includes an input electrode 151 and an output electrode 152.

[0058] The interlayer dielectric layer 133 covers the second gate 122, the second active layer 142, and the first insulation layer 131. The input electrode 151 is connected to the second contact portion 42c, and the output electrode 152 is connected to the first contact portion 42b.

[0059] In some embodiments, the interlayer dielectric layer 133 may be a single-layer or a multi-layer stacked structure, and its material may be SiO_x, SiN_x, SiN_x/SiO_x, SiNO_x, or the like.

[0060] The source-drain metal layer may be a single-layer or a multi-layer stacked structure. For example, the source-drain metal layer may be Mo, Mo/Al, Mo/Cu, MoTi/Cu, MoTi/Cu/MoTi, Ti/Al/Ti, Ti/Cu/Ti, Mo/Cu/IZO, IZO/Cu/IZO, or Mo/Cu/ITO, etc.

[0061] Then a step B15 is subjected.

[0062] Step B15, referring to FIG. 6, a passivation layer 134 and a conductive layer 153 are sequentially formed on the source-drain metal layer.

[0063] The passivation layer 134 covers the source-drain metal layer and interlayer dielectric layer 133. The conductive layer 153 is connected to the output electrode 152.

[0064] In some embodiments, the passivation layer 134 may be a single-layer or a multi-layer stacked structure, and its material may be SiO_x, SiN_x, SiN_x/SiO_x, SiNO_x, or the like.

[0065] The conductive layer 153 may be a single-layer or a multi-layer stacked structure, and its material may be ITO, IZO, Cu, Al, Ag, Ti, Mo, Mo/Al, Mo/Cu, MoTi/Cu, MoTi/Cu/MoTi, Ti/Al/Ti, Ti/Cu/Ti, Mo/Cu/IZO, IZO/Cu/IZO, Mo/Cu/ITO, ITO/Ag/ITO, IZO/Ag/IZO, or the like.

[0066] In this way, the preparation process of the drive substrate 100 of the embodiment is completed.

[0067] Referring to FIG. 7, compared with the above embodiment, another embodiment of the present disclosure is different from the above embodiment in that: the first active layer 141 further includes a third contact portion 41b connected to a side of the first channel 41a, and the first contact portion 42b is stacked on and connected to the third contact portion 41b.

[0068] In the embodiment, the first contact portion 42b and the third contact portion 41b are superimposed to improve the overall conductivity and reduce the resistance value of the device, which is beneficial to weaken the electric field of the area where the output electrode 152 is located, thereby suppressing the movement of the hot carriers.

[0069] In addition, the superposition of the first contact portion 42b and the third contact portion 41b reduces a depth of a hole, so that the output electrode 152 is more stably connected to the first contact portion 42b.

[0070] In some embodiments, a resistance value of the first contact portion 42b stacked with the third contact portion 41b as a whole is less than a resistance value of the second contact portion 42c. Such arrangement may further suppress the movement of the hot carriers.

[0071] In some embodiments, the drive substrate 100 further includes a photo-generated carrier injection portion disposed near a junction area of the first channel 41a and the first contact portion 42b and extending beyond the second gate 122.

[0072] The carriers provided by photo-generated carrier injection portion have a type different from that of the carriers in the first channel 41a, and the carriers in the first channel 41a and the carriers in the second channel 42a have the same type.

[0073] It should be noted that, the photo-generated carrier injection portion is introduced in the embodiment, so that carriers may be provided in time with a change of a gate voltage of the second gate 122, so as to suppress a formation of a non-equilibrium state in the area where the output electrode 152 is located, reduce an emission number of defect states in a pn junction depletion area at the first contact portion 42b and the first channel 41a, thereby suppressing the dynamic hot carrier effect.

[0074] Correspondingly, referring to FIG. 8, a display panel 1000 is further provided according to embodiments of the present disclosure. The display panel 1000 includes the drive substrate 100 as in any of the above embodiments and a light emitting element 200 disposed on the drive substrate 100. The light emitting element 200 is connected to the output electrode 152.

[0075] The drive substrate 100 further includes a conductive layer 153 connected to the output electrode 152. The light emitting element 200 is bonded and connected to the conductive layer 153.

[0076] In some embodiments, the light emitting element 200 may be a submillimeter level light emitting diode, a micro light emitting diode, an organic light emitting diode, or the like.

[0077] It should be explained that the structure of the drive substrate 100 of the display panel 1000 in the embodiments is similar or identical to the structure of the drive substrate 100 in the above-mentioned embodiments, and will not be repeated here.

[0078] For the display panel 1000 of the embodiments of the present disclosure, in the thin film transistor TFT of the drive substrate 100, a structure with double-gate and double-active layer is formed by the first active layer 141, the first gate 121, the first sub-gate 22a, and a part of the second active layer 142 in an area adjacent to the output electrode 152, and a structure with single active layer and top gate is formed by the second sub-gate 22b and a part of the second active layer 142 in an area adjacent to the input electrode 151. Since the first gate 121 and the second gate 122 together control the first channel 41a of the first active layer 141 and the first portion 42a1 of the second channel 42a of the second active layer 142, a resistance and a voltage drop of the area are reduced, so that an electric field intensity of the area is weakened during operation, thereby suppressing the movement of the hot carriers and improving the stability of the threshold voltage (Vth) of the thin film transistor TFT.

[0079] The drive substrates and display panels according to embodiments of the present disclosure have been described above in detail. In this paper, specific examples are used to illustrate the principle and implementation of the invention. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. Those skilled in the art can make various changes and modifications without departing from the spirit of the present disclosure. Therefore, the described embodiments are not intended to limit the present disclosure.