Apparatus and method with image processing for sparse dual-pixel image data

[0001] This application claims the benefit under 35 USC § 119(a) of Korean Patent Application No. 10-2022-0013529, filed on Jan. 28, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] The following description relates to an apparatus and method with image processing for sparse dual-pixel image data.

[0003] An autofocus method based on image data from a dual-pixel image sensor may be used for capturing an image using a camera. Among various autofocus methods, a method referred to as phase-difference auto-focus (PDAF) has been widely used.

[0004] The PDAF method uses a sensor with pixels dedicated to detecting pixel-level phase differences. With the PDAF method, increasing the number of dedicated pixels in a sensor may be advantageous for auto-focusing, however, an increase in pixels dedicated to detecting phase differences may cause image quality degradation.

[0005] A dual-pixel sensor is a sensor where each pixel may be used for both image capture and phase-difference detection. In a dual-pixel sensor, each pixel includes two photodiodes. By configuring a sensor to have all (or, many) of its pixels configured as dual-pixels, PDAF may be performed while reducing image quality degradation.

[0006] Disparity information (e.g., a disparity map) may be detected from left and right images obtained by the two photodiodes in respective pixels. Since the disparity information of a scene can be readily used to derive depth information (e.g., a depth map) of the scene, which is useful for autofocusing. That is, the dual-pixel method may support an autofocus function, as well as other techniques or applications that may use depth information. A disparity between left and right images may be obtained by stereo matching algorithms.

[0007] In contrast to a dual-pixel sensor (or, 2 photodiode (2PD) sensor), a super photodiode (PD) sensor has only some pixels configured as dual-pixels (e.g., 1 in 16 or 1 in 32). A super PD sensor that includes more typical pixels (i.e., non-dual pixels, e.g., ordinary color pixels, IR pixels, monochrome pixels, etc.) may have better image quality than a super PD sensor with fewer typical pixels, however, a super PD sensor may produce lower quality disparity information than a 2PD sensor since the number of dual-pixels is less than that of a 2PD sensor.

[0008] The principle of disparity between a left and right image may correspond to differences in point spread functions (PSF) of the left and right images, whereas a blur area may occur when an object is not within the focal plane (or focal range). Since a super PD sensor may include sparsely distributed dual-pixels capturing the area of blur, disparity quality for the blur area may be less than the disparity quality that would be provided by a 2PD sensor (which includes densely distributed dual-pixels). Accordingly, the quality of an estimated disparity map (and a related function such as auto-focus) may vary depending on how the sparsely distributed dual-pixels are used to generate left and right images (i.e., a dual-image). For example, a conventional method to generate a dual-image for a super PD sensor may involve reordering values of pixels. However, using this technique, the resolution of disparity information may be degraded or the accuracy of disparity estimation may be deteriorated.

[0009] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0010] In one general aspect, an apparatus includes a processor configured to generate a first interpolated image by performing interpolation on a first image and generate a second interpolated image by performing interpolation on a second image, wherein the first image and the second image comprise pixel values obtained by dual-pixels of an image sensor, and generate a disparity map based on the first interpolated image and the second interpolated image.

[0011] The first image may be a left image, and the second image may be a right image.

[0012] The processor may be further configured to generate the first interpolated image based on a position of a first dual-pixel of the dual-pixels, a first pixel value obtained by the first dual-pixel, a position of a second dual-pixel of the dual-pixels, and a second pixel value obtained by the second dual-pixel.

[0013] The processor may be configured to generate the second interpolated image based on the position of the first dual-pixel, a third pixel value obtained by the first dual-pixel, the position of the second dual-pixel, and a fourth pixel value obtained by the second dual-pixel.

[0014] Each of the dual-pixels respectively may include a first photodiode, a second photodiode, and a single lens configured to refract light to the first photodiode and the second photodiode.

[0015] The first pixel value may be obtained by the first photodiode of the first dual-pixel, the second pixel value may be obtained by the first photodiode of the second dual-pixel, the third pixel value may be obtained by the second photodiode of the first dual-pixel, and the fourth pixel value may be obtained by the second photodiode of the second dual-pixel.

[0016] The apparatus may include the image sensor.

[0017] The processor may be further configured to generate an interpolation pixel at an intermediate position between the position of the first dual-pixel and the position of the second dual-pixel.

[0018] The processor may be further configured to determine an average of the first pixel value and the second pixel value and to set a pixel value of the interpolation pixel to the average.

[0019] The processor may include an adder configured to perform addition of the first pixel value and the second pixel value, and a shifter configured to perform a division operation by performing a bit-shift operation on a result of the addition that may be outputted from the adder.

[0020] The processor may be further configured to perform interpolation such that a ratio of a number of interpolation pixels in a horizontal direction to a number of interpolation pixels in a vertical direction may be the same as, or a multiple of, a ratio of a number of pixels in a horizontal direction of the image sensor to a number of pixels in a vertical direction of the image sensor.

[0021] The apparatus may include a smartphone.

[0022] In one general aspect, a processor-implemented method may include accessing a first image and a second image, the first image and the second image generated by an image sensor including pixels that include dual-pixels and that include pixels that may be not dual-pixels, wherein each dual-pixel respectively may include a first photodiode, a second photodiode, and a single lens, wherein the first image may include pixel values obtained from the first photodiodes and wherein the second image may include pixel values obtained from the second photodiodes, generating a first interpolated image by generating first interpolated pixels based on interpolation of the pixel values in the first image, and generating a second interpolated image by generating second interpolated pixels based on interpolation of the pixel values in the second image, and generating a disparity map based on the first interpolated image and the second interpolated image.

[0023] The first image may be a left image, and the second image may be a right image, and wherein the first image and the second image may be captured by the image sensor at the same time.

[0024] The first interpolated pixels may be positioned in the first interpolated image based on positions of respective pairs of pixels in the first image, and wherein the second interpolated pixels may be positioned in the second interpolated image based on positions of respective pairs of pixels in the second image.

[0025] The pairs of pixels may correspond to pairs of the dual-pixels of the image sensor.

[0026] Each pixel of the first interpolated image may have a position therein that corresponds to a position between the pixels of a corresponding pair of pixels of the first image.

[0027] The first interpolated pixels comprise respective averages of the pixel values in the first image.

[0028] The generating of the first and second interpolated pixels may include performing, by an adder, additions of the pixel values in the first image and additions of the pixel values in the second image, and performing, by a shifter, bit-shift operations on results of the additions outputted from the adder.

[0029] The generating of the first interpolated image and the second interpolated image may include performing interpolation such that a number of pixels in a horizontal direction in each of the first image and the second image may be the same as a number of pixels in a horizontal direction in each of the first image and the second image.

[0030] The generating of the first interpolated image and the second interpolated image may include performing interpolation such that an image aspect ratio of each of the first image and the second image may be the same as, or a multiple of, an image aspect ratio of the image sensor.

[0031] In one general aspect, a method may include accessing a first image comprising first pixels, wherein each first pixel may include a first value, wherein the first image may be generated by an image sensor comprising pixels, wherein the pixels of the image sensor comprise dual-pixels and non-dual-pixels, each dual-pixel respectively including first and second photodiodes, wherein the first values may be provided by the respective first photodiodes, and generating a first interpolated image by interpolating pairs of the first pixels.

[0032] Each first photodiode may have a different point spread function than its corresponding second photodiode.

[0033] The first photodiodes may be left photodiodes and the second photodiodes may be right photodiodes.

[0034] Each dual-pixel further may include a lens configured to refract light to the corresponding first and second photodiodes.

[0035] A smartphone may include the camera, wherein the camera may include the image sensor, and wherein the camera may be auto-focused based on the disparity map.

[0036] The non-dual-pixels may sense a color and the first and second images may include color pixels having color values provided by color sensing of the non-dual-pixels.

[0037] In one general aspect, a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform any of the methods.

[0038] Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.

[0051] Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same or like elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

[0052] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known after an understanding of the disclosure of this application may be omitted for increased clarity and conciseness.

[0053] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

[0054] The terminology used herein is for describing various examples only and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items. As non-limiting examples, terms “comprise” or “comprises,” “include” or “includes,” and “have” or “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

[0055] Throughout the specification, when a component or element is described as being “connected to,” “coupled to,” or “joined to” another component or element, it may be directly “connected to,” “coupled to,” or “joined to” the other component or element, or there may reasonably be one or more other components or elements intervening therebetween. When a component or element is described as being “directly connected to,” “directly coupled to,” or “directly joined to” another component or element, there can be no other elements intervening therebetween. Likewise, expressions, for example, “between” and “immediately between” and “adjacent to” and “immediately adjacent to” may also be construed as described in the foregoing.

[0056] Although terms such as “first,” “second,” and “third”, or A, B, (a), (b), and the like may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Each of these terminologies is not used to define an essence, order, or sequence of corresponding members, components, regions, layers, or sections, for example, but used merely to distinguish the corresponding members, components, regions, layers, or sections from other members, components, regions, layers, or sections. Thus, a first member, component, region, layer, or section referred to in the examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.

[0057] Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and based on an understanding of the disclosure of the present application. Terms, such as those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure of the present application and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein. The use of the term “may” herein with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists where such a feature is included or implemented, while all examples are not limited thereto.

[0058] FIG. 1 illustrates an example of an image processing apparatus, according to one or more embodiments. Referring to FIG. 1, an image processing apparatus 10 may process an image. The image may be an image of an object or scene formed by sensing the refraction or reflection of light, and may represent the shape of an object or scene using lines, colors, etc. For example, the image may be in a digital form typically processed by a computer (e.g., a matrix of pixel values). In an example, the image processing apparatus 10 may be included in an electronic device 5. In an example, the image processing apparatus may itself be an electronic device, e.g., with the image sensor 400 being a component of the electronic device 5 or separate from the electronic device 5.

[0059] The image processing apparatus 10 may process an image obtained by an image sensor 400 configured with a plurality of pixels (as used herein, depending on the context, the term “pixel” may refer to an individual point sensor in an image sensor or an element of an image). Among the plurality of sensor pixels, some pixels (e.g., 1 in 16, 1 in 32, etc.) are implemented as dual-pixels, and other sensor pixels are ordinary non-dual pixels (e.g., color-sensing pixels). For example, the image sensor 400 may be a super photodiode (PD) image sensor. In some implementations, the dual-pixels of a super PD image sensor may be somewhat evenly distributed among the pixels of the super PD image sensor. In some implementations, the dual-pixels of a super PD image sensor may provide a left and right value (raw disparity data) but may not provide color data, and a color image produced by a super PD image sensor may have “empty” pixels at locations corresponding to the dual-pixels. An empty pixel may be colored based on colors of neighboring pixels.

[0060] The image processing apparatus 10 may be implemented in various electronic devices 5 using a super PD type of image sensor. For example, the electronic device 5 or the image processing apparatus 10 may be, or may be included in, a personal computer (PC), a data server, or a portable device. The portable device may be a laptop computer, a mobile phone, a smartphone, a tablet PC, a mobile internet device (MID), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, an e-book, a smart device, an on-board computing system of a vehicle, an advanced driver-assist system/autonomous-driving (ADAS/AD) system, or the like. The smart device may be a smart watch, a smart band, a smart ring, or the like.

[0061] The image processing apparatus 10 may generate a disparity map by processing an image. The disparity map may be helpful for a variety of applications, for example, image processing (e.g., de-blurring), object detection/recognition, auto-focusing, etc. As noted, a dual-pixel of the image sensor 400 may include two photodiodes (e.g., left and right, up and down, upper-left and lower-right, etc.) under a single microlens that refracts light to the two photodiodes. Due to different angles of incidence on the microlens, the two photodiodes of a dual-pixel may have different point spread functions (PSFs). That is, a left photodiode and a right photodiode may have different respective PSFs corresponding to their different microlens incidence angles. When blur has occurred in an area of an image due the focal depth of the area being out of the focal range of the camera when the image was captured, corresponding disparity may occur due to a difference between the PSFs. Through processing described below, this disparity may be conveniently represented in the form of a disparity map, which may be an image representing the disparity (i.e., an image whose pixels are disparity values). Examples of disparity maps are described in detail with reference to FIGS. 8 and 9.

[0062] The image processing apparatus 10 may generate a disparity map by using interpolation on a left image and a right image obtained by the image sensor 400. The terms “left” and “right” are used herein to discuss relative arrangement with respect to stereo pairing and do not imply any particular orientation of an image, a pixel, an image sensor, or the like. In some examples, the left image may be an image from the image sensor 400 that includes the values of the left photodiodes of the dual-pixels and the right image may be an image from the image sensor 400 that includes the values of the right photodiodes of the dual-pixels (where the left and right images are captured concurrently by the image sensor 400). In other examples, the left and right images may be images of only the left dual-pixel values and the right dual-pixel values, respectively. Regardless of the form of the left and right images (which at the least contain dual-pixel values), the left and right images comprise data sensed at the same time by the image sensor 400. That is, the left and right images are images of a same scene/object captured at a same time.

[0063] The image processing apparatus 10 may include a receiver 100 and a processor 200. The image processing apparatus 10 may further include a memory 300.

[0064] The receiver 100 may receive an image, for example a dual-image, from the image sensor 400. The receiver 100 may receive a first image and a second image from the image sensor 400. The first image may be the left image, and the second image may be the right image.

[0065] The receiver 100 may include a receiving interface. The receiver 100 may output the received first image and the received second image to the processor 200.

[0066] The processor 200 may process data stored in the memory 300. The data for the processor 200 may include computer-executable instructions, source code, bytecode, intermediate code, instructions triggered by the processor 200, etc.

[0067] The processor 200 may be a data processing device implemented by hardware including a circuit having a physical structure configured to perform desired operations. For example, the desired operations may be represented as code or instructions in a program.

[0068] For example, the hardware-implemented data processing device may be a microprocessor, a central processing unit (CPU), a processor core, a multi-core processor, a multiprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor, an image processor, or the like.

[0069] The processor 200 may generate a first interpolated image and a second interpolated image by performing interpolation on the first image and the second image, respectively, based on pixel values obtained by the dual-pixels.

[0070] The processor 200 may generate the first interpolated image by interpolating pixels of the first image and may generate the second interpolated image by interpolating pixels of the second image. The first and second interpolated images may include interpolation pixels. The interpolation pixels may be generated using a same interpolation technique for the first image and for the second image. The first interpolated image may include first interpolation pixels interpolated from the first image, and the second interpolated image may include second interpolation pixels interpolated from the second image. An interpolation pixel for the first interpolated image may be generated based on (i) a position corresponding to a position of a first dual-pixel included in a plurality of pixels of the image sensor 400, (ii) a first pixel value obtained by the left photodiode of the first dual-pixel, (iii) a position corresponding to a position of a second dual-pixel included in the plurality of pixels of the image sensor 400, and (iv) a second pixel value obtained by the left photodiode of the second dual-pixel. Similarly, an interpolated pixel for the second interpolated image may be generated based on (i) a position corresponding to the position of the first dual-pixel, (ii) a first pixel value obtained by the right photodiode of the first dual-pixel, (iii) a position corresponding to the position of the second dual-pixel, and (iv) a second pixel value obtained by the right photodiode of the second dual-pixel. The positions corresponding to the dual-pixel locations may be positions in the first and second images, for example. As described below, an interpolated image (first or second) may include interpolation pixels generated from respective pairs of many (or all) values/locations obtained by corresponding neighboring pairs of dual-pixels. In other words, the first and second pixels and the locations noted above represent arbitrary pairs of neighboring positions and values for which respective interpolation pixels may be generated. Note that “neighboring” as used herein does not imply strict adjacency, as shown in FIGS. 2A and 3A.

[0071] The processor 200 may generate an interpolation pixel at an intermediate position between the position of the first dual-pixel and the position of the second dual-pixel. In some implementations, the intermediate position may be a point equidistant from the position of the first dual-pixel and the position of the second dual-pixel. In other implementations, the intermediate position of an interpolation pixel may be positioned between the first and second dual-pixels but closer towards one of the dual-pixels, and the value of the interpolation pixel may be generated by giving greater weight to the value of the nearer dual-pixel.

[0072] In some examples, the processor 200 may determine an average value of the first pixel value and the second pixel value and use the average value as the pixel value corresponding to the interpolation pixel. In other words, the processor 200 may calculate the pixel value of the interpolation pixel by adding the first pixel value to the second pixel value and then dividing the result by 2. Other interpolation techniques, for example weighted averages, may be used.

[0073] In some examples, the processor 200 may include an adder configured to perform addition of the first pixel value and the second pixel value, and a shifter configured to perform a division operation by performing a bit-shift operation on an output from the adder.

[0074] As noted above, interpolation pixels may be generated for various respective pairings of dual-pixels, and different schemes for pairings may produce different patterns of interpolation pixels. That is, different selections of pairings may correspond to different patterns and/or densities of interpolation pixels in interpolation images. For example, the processor 200 may perform interpolation such that the ratio of a number of interpolation pixels in a horizontal direction of the first interpolation image (or the second interpolation image) to a number of interpolation pixels in a vertical direction of the first image (or the second interpolation image) is the same as the ratio of a number of pixels in a horizontal direction of the image sensor 400 to a number of pixels in a vertical direction of the image sensor 400.

[0075] In another example, the processor 200 may perform interpolation such that the ratio of the number of interpolation pixels in the horizontal direction to the number of interpolation pixels in the vertical direction is an integer multiple of a ratio of the number of pixels in the horizontal direction of the image sensor 400 to the number of pixels in the vertical direction of the image sensor 400. In other words, the processor 200 may perform interpolation such that a value obtained by dividing a number of interpolation pixels in the horizontal direction of an interpolation image by a number of interpolation pixels in the vertical direction of the interpolation image is greater than a value obtained by dividing a number of horizontal pixels of an image obtained by the image sensor 400 by a number of vertical pixels of the image. For example, the processor 200 may perform interpolation such that the ratio of the number of interpolation pixels in the horizontal direction to the number of interpolation pixels in the vertical direction is twice the ratio of the number of pixels in the horizontal direction of the image sensor 400 to the number of pixels in the vertical direction of the image sensor 400.

[0076] The processor 200 may calculate a disparity based on the first interpolated image and the second interpolated image. A process of calculating the disparity is described with reference to FIGS. 5 and 6. Moreover, the processor 200 may generate a disparity map based on the disparity.

[0077] The memory 300 may store data for an operation or an operation result. The memory 300 stores instructions (or programs) executable by the processor 200. For example, the instructions include instructions to perform an operation of the processor 200 and/or an operation of each element of the processor 200.

[0078] The memory 300 may be implemented as a volatile memory device or a non-volatile memory device. A volatile memory device may be implemented as dynamic random-access memory (DRAM), static random-access memory (SRAM), thyristor RAM (T-RAM), zero capacitor RAM (Z-RAM), or twin transistor RAM (TTRAM). A non-volatile memory device may be implemented as electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM (MRAM), spin-transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, polymer RAM (PoRAM), nano floating gate Memory (NFGM), holographic memory, a molecular electronic memory device, or insulator resistance change memory.

[0079] FIG. 2A illustrates an example of an interpolation operation performed by an image processing apparatus, according to one or more embodiments. For example, the image processing apparatus may be the image processing apparatus of FIG. 1. FIG. 2B illustrates an example of an image generated by the interpolation operation of FIG. 2A.

[0080] Referring to FIGS. 2A and 2B, a processor (for example, the processor 200 of FIG. 1) may generate an interpolated image by generating interpolation pixels thereof using interpolation. Such interpolation is described with reference to an interpolation pixel 250, which is representative of the interpolation pixels of an interpolated image. For example, the processor 200 may dispose the interpolation pixel 250 at an intermediate position of two adjacent (or neighboring, or nearby) dual-pixels and may compute a value of the interpolation pixel 250 by averaging pixel values of the two adjacent dual-pixels (e.g., a left value of first dual-pixel 210 and a left value of a second dual-pixel 230).

[0081] The processor 200 may generate a first interpolated image and a second interpolated image, based on a position of the first dual-pixel 210 included in a plurality of pixels, a first pixel value obtained by the first dual-pixel 210, a position of the second dual-pixel 230 included in the plurality of pixels, and a second pixel value obtained by the second dual-pixel 230.

[0082] The processor 200 may, for example, generate the interpolation pixel 250 at an intermediate position between the position of the first dual-pixel 210 and the position of the second dual-pixel 230. The processor 200 may, for example, determine an average value of the first pixel value and the second pixel value to be a pixel value corresponding to the interpolation pixel 250. For example, if the interpolation pixel 250 is for an interpolated right image, the first pixel value may correspond to a right photodiode of the first dual-pixel 210 and the second pixel value may correspond to a right photodiode of the second dual-pixel 230.

[0083] The processor 200 may perform interpolation such that the ratio of a number of interpolation pixels in the horizontal direction and a number of interpolation pixels in the vertical direction is the same as the ratio of a number of pixels disposed in the horizontal direction of an image sensor and a number of pixels disposed in the vertical direction of the image sensor. In other words, the interpolation images may have a same aspect ratio as the image sensor.

[0084] The processor 200 may generate the interpolated image with a lattice pattern of interpolation pixels as shown in FIG. 2A and may thereby avoid creating a wave pattern; a wave pattern may not be optimal for some applications of disparity data. The example of FIG. 2B is an interpolated image without a wave-pattern artifact.

[0085] For example, raw pixel values of the first image and the second image may be 10 bits, and the pixel values may be stored in a 16-bit container, word, element, etc. The processor 200 may efficiently calculate an average of two pixel values contained in 16 bits by configuring bit-shift for adding the two pixel values and dividing them by 2. The processor 200 may accelerate calculating an interpolated pixel value through a single instruction multiple data (SIMD) operation.

[0086] FIG. 3A illustrates another example of an interpolation operation performed an image processing apparatus, according to one or more embodiments. The image may be the image processing apparatus of FIG. 1, for example. FIG. 3B illustrates an example of an image generated by the interpolation operation of FIG. 3A.

[0087] Referring to FIGS. 3A and 3B, the processor 200 may generate a first interpolation pixel 370 (representing any arbitrary interpolation pixel of the interpolation image) based on (i) a position of a first dual-pixel 310 included in a plurality of pixels, (ii) a first pixel value obtained by the first dual-pixel 310, (iii) a position of a second dual-pixel 330 included in the plurality of pixels, and (iv) a second pixel value obtained by the second dual-pixel 330.

[0088] The processor 200 may generate a second interpolation pixel 390 based on (i) the position of the second dual-pixel 330, (ii) the second pixel value of the second dual-pixel 330, (iii) a position of a third dual-pixel 350, and (iv) a third pixel value obtained by the third dual-pixel 350.

[0089] The processor 200 may generate the first interpolation pixel 370 at an intermediate position between the position of the first dual-pixel 310 and the position of the second dual-pixel 330. The processor 200 may generate the second interpolation pixel 390 at an intermediate position between the position of the second dual-pixel 330 and the position of the third dual-pixel 350.

[0090] The processor 200 may determine an average of the first pixel value and the second pixel value and may set the pixel value of the first interpolation pixel 370 to be that determined average. The processor 200 may determine an average of the second pixel value and the third pixel value and may set the pixel value of the second interpolation pixel 390 to be that determined average.

[0091] The processor 200 may perform interpolation for pairs of dual-pixels such that the ratio of the number of interpolation pixels in a horizontal direction of the first/second interpolated image to the number of interpolation pixels in a vertical direction of the first/second image is an integer multiple (e.g., two) of the ratio of the number of pixels in a horizontal direction of an image sensor to the number of pixels in a vertical direction of the image sensor.

[0092] The processor 200 may generate a first interpolated image and a second interpolated image by increasing a horizontal resolution of each interpolated image, for example, as shown in FIG. 3A. In case an interpolated image is generated as shown in FIG. 3A, a wave pattern may occur in the horizontal direction but not the vertical direction.

[0093] In case interpolation is performed as shown in FIG. 3A and a wave pattern occurs in the horizontal direction of an interpolation image, waviness in the horizontal direction thereof may not be as pronounced as the waviness of the dual-pixels in the horizontal resolution.

[0094] FIG. 3B shows an example of an interpolated image generated by performing interpolation as described with reference to FIG. 3A. Since the example interpolation image of FIG. 3B has a higher resolution in the horizontal direction than the interpolation image in the example of FIG. 2B, the processor 200 may obtain a high-resolution disparity map by using the interpolated image shown in FIG. 3B.

[0095] FIG. 4 illustrates an example of an operation of generating a disparity map, according to one or more embodiments.

[0096] Referring to FIG. 4, a processor (for example, the processor 200 of FIG. 1) may generate left and right interpolated images using a raw image obtained by dual-pixels of an image sensor (for example, the image sensor 400 of FIG. 1). The raw image may be an image with left values and right values, for example, of pixels generated by the left and right photodiodes, respectively, of the dual-pixels of the image sensor. In some examples, the raw image may contain both a right image and a left image. In other examples, the left-right values may be provided in separate respective raw left and right images.

[0097] The processor 200 may obtain a disparity map (for example, a disparity image or a depth image) by processing the generated left and right interpolated images by using a disparity estimation algorithm. A resolution and quality of the estimated disparity map may vary based on the resolution and quality of the generated left and right interpolated images.

[0098] The processor 200 may generate a relatively high-resolution and high-quality disparity map based on a raw image (or images) from a super PD image sensor configured with sparse dual-pixels, by generating the left and right interpolated images through any of the interpolation methods described herein.

[0099] The processor 200 may generate relatively high-resolution left and right interpolated images with less likelihood of artifacts by using any of the interpolation methods described herein, and may perform interpolation through, for example, addition and bit-shift of pixel values, for example.

[0100] A receiver (for example, the receiver 100 of FIG. 1) may receive a raw image. The raw image may include a first image and a second image (e.g., captured by the image sensor at the same time). The receiver 100 may output the received raw image to the processor 200.

[0101] In operation 410, the processor 200 may perform interpolation on the received raw image. The interpolation may be performed, for example, by any of the methods described with reference to FIGS. 2A and 3A.

[0102] The processor 200 may generate left and right interpolated images through the interpolation. The left and right interpolated images may correspond to the first interpolated image and the second interpolated image described with reference to FIG. 1, respectively.

[0103] In operation 430, the processor 200 may calculate a disparity based on the left and right interpolated images. The processor 200 may then generate a disparity map using the disparity.

[0104] FIGS. 5 and 6 illustrate examples of a process of calculating a disparity, according to one or more embodiments. Referring to FIGS. 5 and 6, a processor (for example, the processor 200 of FIG. 1) may calculate a disparity based on a first interpolated image and a second interpolated image. The example of FIG. 5 may represent the first interpolated image, and the example of FIG. 6 may represent the second interpolated image.

[0105] The first interpolated image may correspond to a left image, and the second interpolated image may correspond to a right image. The examples of FIGS. 5 and 6 are images interpolated by the method described with reference to FIG. 3A, however, disparity for an image interpolated by the method described with reference to FIG. 2A may be calculated in the same way.

[0106] The processor 200 may calculate the disparity using Equations 1 to 7. Equations 1 to 7 are examples of calculating the disparity; the disparity may be calculated by a different method. The processor 200 may calculate a raw disparity based on Equation 1.

[0107] $\begin{array}{cc}\begin{array}{c}\mathrm{Raw}\mathrm{disparity}\\ \left(1~11\right)\end{array}{d}_{\mathrm{ij}}^{\mathrm{raw}}=\underset{\mathrm{idx}}{\mathrm{argmin}}\mathrm{SAD}\left(510,\stackrel{\stackrel{\mathrm{idx}}{︷}}{\begin{array}{c}1\\ \underset{-1}{610}\end{array}\begin{array}{c}2\\ \underset{-2}{610}\end{array}\dots \begin{array}{c}2*\mathrm{shift}+1\\ \square \end{array}}\right)& \mathrm{Equation}1\end{array}$

[0108] Here, 510 denotes a pixel value corresponding to a rectangle 510 of FIG. 5, and 610-1, 610-2, . . . denotes pixel values obtained by seeking a rectangle 610 of FIG. 6 in left and right. “SAD” refers to the sum-of-absolute-differences operation. A seeking shift, a template size, and a stride may be Shift=5, template_size=(ts_y,ts_x)=(16, 16), stride=(st_y,st_x)=(4, 8).

[0109] The processor 200 may calculate textureness based on Equations 2 to 4.

[0110] $\begin{array}{cc}\begin{array}{c}\mathrm{Textureness}\\ \left(0~255\right)\end{array}{d}_{\mathrm{ij}}^{\mathrm{text}}=\mathrm{MapTo}8\mathrm{bit}\left(\sum ❘{\mathrm{Sobel}}_{x-\mathrm{dir}}\left(510\right)❘\right)& \mathrm{Equation}2\end{array}$

[0111] $\begin{array}{cc}\mathrm{MapTo}8\mathrm{bit}=\mathrm{CLIP}\left({\mathrm{SHIFT}}_{\mathrm{right}}\left(·,{\mathrm{div}}_{\mathrm{shift}}\right),0,255\right)& \mathrm{Equation}3\end{array}$

[0112] $\begin{array}{cc}{\mathrm{div}}_{\mathrm{shift}}={\log }_2\left({\mathrm{ts}}_y·{\mathrm{ts}}_x\right)-4& \mathrm{Equation}4\end{array}$

[0113] The processor 200 may calculate a texture map based on Equations 5 and 6.

[0114] $\begin{array}{cc}\begin{array}{c}\mathrm{Texture}\mathrm{map}\\ \left(0,1\right)\end{array}{d}_{\mathrm{ij}}^{\mathrm{tmap}}=d_{\mathrm{ij}}^{\mathrm{text}}>{\mathrm{Th}}_{\mathrm{texture}}& \mathrm{Equation}5\end{array}$

[0115] Here, Th_texture may be calculated by Equation 6.

[0116] $\begin{array}{cc}{\mathrm{Th}}_{\mathrm{texture}}=\mathrm{INT}\left(1.1·\left(\frac{{\mathrm{ts}}_y·{\mathrm{ts}}_x}{2^{\mathrm{shift}}}\right)\right)& \mathrm{Equation}6\end{array}$

[0117] The processor 200 may calculate the disparity based on the raw disparity and the texture map, as shown in Equation 7.

[0118] $\begin{array}{cc}\begin{array}{c}\mathrm{Conf}.\mathrm{disparity}\\ \left(0~11\right)\end{array}{d}_{\mathrm{ij}}^{\mathrm{conf}}=d_{\mathrm{ij}}^{\mathrm{raw}}·d_{\mathrm{ij}}^{\mathrm{tmap}}& \mathrm{Equation}7\end{array}$

[0119] FIG. 7 illustrates an example of a grayscale image 700 before performing image processing, FIG. 8 illustrates an example of a disparity map 800 generated by the interpolation operation of FIG. 3A, and FIG. 9 illustrates an example of a disparity map 900 generated by the interpolation operation of FIG. 2B.

[0120] Referring to FIGS. 7 to 9, a processor (for example, the processor 200 of FIG. 1) may generate relatively high-resolution left and right interpolated images without minimal artifacts by using sparsely distributed dual-pixels as in the example of a super PD image sensor.

[0121] The processor 200 may perform interpolation by using an interpolation pattern method considering a dual-pixel distribution pattern of a super PD image sensor and may perform interpolation through an addition operation and a bit-shift operation. Through this process, the processor 200 may obtain a detailed disparity map with reduced noise.

[0122] The processor 200 may generate left and right interpolated images (for example, a first interpolated image and a second interpolated image) by processing raw data obtained by a super PD image sensor and may calculate a disparity from the generated interpolated images.

[0123] A conventional method may generate left and right images by, for example, using pixel reordering, however, this may degrade a resolution or may cause artifacts, and the quality of an estimated disparity may be degraded due to the artifacts. However, the processor 200 may improve a resolution and accuracy of a disparity map by generating an interpolated image using an interpolation method.

[0124] FIG. 10 illustrates an example of an operation of an image processing apparatus, according to one or more embodiments. The image processing apparatus may be the image processing apparatus of FIG. 1. Referring to FIG. 10, in operation 1010, a receiver (for example, the receiver 100 of FIG. 1) may receive a first image and a second image from an image sensor (for example, the image sensor 400 of FIG. 1) that includes a plurality of pixels of which some pixels are configured as dual-pixels and some are configured as ordinary non-dual-pixels (e.g., color-sensing pixels).

[0125] In operation 1030, the processor 200 may generate a first interpolated image and a second interpolated image by performing interpolation on the first image and the second image, respectively, based on pixel values obtained by the dual-pixels.

[0126] The processor 200 may generate the first interpolated image and the second interpolated image based on a position of a first dual-pixel included in the plurality of pixels, a first pixel value obtained by the first dual-pixel, a position of a second dual-pixel included in the plurality of pixels, and a second pixel value obtained by the second dual-pixel.

[0127] The processor 200 may represent the first pixel value and the second pixel value by using a 16-bit container, word, etc.

[0128] The processor 200 may generate an interpolation pixel at an intermediate position between the position of the first dual-pixel and the position of the second dual-pixel.

[0129] The processor 200 may determine an average of the first pixel value and the second pixel value and set a pixel value of the corresponding interpolation pixel to the average.

[0130] The processor 200 may include an adder configured to perform addition of the first pixel value and the second pixel value, and a shifter configured to perform a division operation by performing a bit-shift operation on an output from the adder.

[0131] The processor 200 may perform interpolation such that the ratio of the number of interpolation pixels in a horizontal direction of the first image and of the second image and the number of interpolation pixels in a vertical direction of the first image and of the second image is the same as (or an integer multiple of) the ratio of the number of pixels disposed in a horizontal direction of the image sensor 400 and the number of pixels disposed in a vertical direction of the image sensor 400.

[0132] In operation 1050, the processor 200 may calculate a disparity based on the first interpolated image and the second interpolated image.

[0133] In operation 1070, the processor 200 may generate a disparity map based on the disparity.

[0134] The computing apparatuses, the vehicles, the electronic devices, the processors, the memories, the image sensors, the vehicle/operation function hardware, the displays, the information output system and hardware, the storage devices, and other apparatuses, devices, units, modules, and components described herein with respect to FIGS. 1-10 are implemented by or representative of hardware components. Examples of hardware components that may be used to perform the operations described in this application where appropriate include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to execution of the instructions or software. For simplicity, the singular term “processor” or “computer” may be used in the description of the examples described in this application, but in other examples multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. A hardware component may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

[0135] The methods illustrated in FIGS. 1-10 that perform the operations described in this application are performed by computing hardware, for example, by one or more processors or computers, implemented as described above implementing instructions or software to perform the operations described in this application that are performed by the methods. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller, may perform a single operation, or two or more operations.

[0136] Instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions or any combination thereof, for individually or collectively instructing or configuring the one or more processors or computers to operate as a machine or special-purpose computer to perform the operations that are performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by the one or more processors or computers, such as machine code produced by a compiler. In another example, the instructions or software includes higher-level code that is executed by the one or more processors or computer using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and the flow charts illustrated in the drawings and the corresponding descriptions herein, which disclose algorithms for performing the operations that are performed by the hardware components and the methods as described above.

[0137] The instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of a non-transitory computer-readable storage medium include read-only memory (ROM), random-access programmable read only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROMs, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, blue-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, a card type memory such as multimedia card micro or a card (for example, secure digital (SD) or extreme digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers.

[0138] While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents.

[0139] Therefore, in addition to the above disclosure, the scope of the disclosure may also be defined by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.