Imaging device, endoscope, and imaging method

[0001] Priority is claimed on U.S. Provisional Patent Application No. 63/523,263, filed on Jun. 26, 2023, the content of which is incorporated herein by reference.

[0002] The present invention relates to an imaging device, an endoscope, and an imaging method.

[0003] A power source voltage and a reference voltage are provided to a complementary metal-oxide-semiconductor (CMOS) image sensor (hereinafter, image sensor) in order to drive the image sensor. The image sensor includes two or more pixels. In some cases, a driving voltage between the power source voltage and the reference voltage is provided to a transistor of each of the pixels in order to improve the characteristics of the pixels.

[0004] There are two methods of generating the driving voltage between the power source voltage and the reference voltage. A first method is to generate the driving voltage outside the image sensor and input the driving voltage to the image sensor. A second method is to generate the driving voltage inside the image sensor.

[0005] In the first method, an input terminal of the driving voltage needs to be disposed in the image sensor in addition to an input terminal of the power source voltage and an input terminal of the reference voltage. According to the first method, miniaturization of the image sensor is inhibited since the number of input terminals of the image sensor increases.

[0006] In general, a power source voltage is divided by using a resistor in the second method. For example, Japanese Unexamined Patent Application, First Publication No. 2017-123971 discloses an imaging device including a circuit that generates a lower voltage than a power source voltage by using a resistor. The generated voltage is provided to a transistor in a pixel included in the imaging device.

[0007] According to a first aspect of the present invention, an imaging device is configured to operate by using a power source voltage. The imaging device includes two or more pixels and a voltage generation circuit. Each of the two or more pixels includes a photoelectric conversion element and a transistor. The photoelectric conversion element is configured to perform photoelectric conversion and generate an electric charge in accordance with an amount of received light. The transistor is driven by using a driving voltage. The voltage generation circuit is configured to generate the driving voltage that is lower than the power source voltage and gradually decreases.

[0008] According to a second aspect of the present invention, in the first aspect, the imaging device may be driven by using a clock signal. The voltage generation circuit may be configured to generate the driving voltage included in a predetermined voltage range from a first timing synchronized with the clock signal to a second timing that is synchronized with the clock signal and is different from the first timing.

[0009] According to a third aspect of the present invention, in the first aspect, the voltage generation circuit may include a capacitor and a voltage-current conversion circuit. The capacitor is configured to hold a voltage. The voltage-current conversion circuit is configured to convert the voltage held in the capacitor into a current. The voltage-current conversion circuit may be configured to start conversion into the current after the power source voltage is held in the capacitor. The voltage held in the capacitor may gradually decrease and may be output as the driving voltage while the voltage-current conversion circuit converts the voltage held in the capacitor into the current.

[0010] According to a fourth aspect of the present invention, in the first aspect, each of the two or more pixels may include a floating diffusion configured to hold the electric charge generated by the photoelectric conversion element. The transistor may be configured to transfer the electric charge generated by the photoelectric conversion element to the floating diffusion.

[0011] According to a fifth aspect of the present invention, in the first aspect, the imaging device may include two or more of the voltage generation circuits. The two or more pixels may be disposed in a matrix shape including two or more rows and two or more columns. Each of the two or more of the voltage generation circuits may be disposed so as to correspond to any one of the two or more rows.

[0012] According to a sixth aspect of the present invention, in the fifth aspect, the imaging device may include a vertical selection circuit configured to output a signal for each row of the two or more rows. Each of the two or more of the voltage generation circuits may be configured to output the driving voltage to a pixel included in the two or more pixels when the signal output from the vertical selection circuit has been received.

[0013] According to a seventh aspect of the present invention, in the fifth aspect, each of the two or more of the voltage generation circuits may include a capacitor and a voltage-current conversion circuit. The capacitor is configured to hold a voltage. The voltage-current conversion circuit is configured to convert the voltage held in the capacitor into a current. The voltage-current conversion circuit may be configured to start conversion into the current after the power source voltage is held in the capacitor. The voltage held in the capacitor may gradually decrease and may be output as the driving voltage while the voltage-current conversion circuit converts the voltage held in the capacitor into the current.

[0014] According to an eighth aspect of the present invention, in the first aspect, the imaging device may operate by using a reference voltage lower than the power source voltage. The driving voltage may be lower than the power source voltage and may be higher than the reference voltage.

[0015] According to a ninth aspect of the present invention, in the first aspect, the imaging device may operate by using a reference voltage lower than the power source voltage. The driving voltage may gradually decrease from a first voltage lower than the power source voltage to a second voltage that is lower than the first voltage and is higher than the reference voltage.

[0016] According to a tenth aspect of the present invention, an endoscope includes: a scope to be inserted into a living body; and the imaging device disposed in a distal end of the scope.

[0017] According to an eleventh aspect of the present invention, an imaging method uses an imaging device that includes two or more pixels and operates by using a power source voltage. The imaging method includes an imaging step. Each of the two or more pixels includes a photoelectric conversion element and a transistor. The photoelectric conversion element is configured to perform photoelectric conversion and generate an electric charge in accordance with an amount of received light. The transistor is driven by using a driving voltage. The imaging step includes: generating the driving voltage that is lower than the power source voltage and gradually decreases; and outputting the driving voltage to the transistor.

[0028] Embodiments of the present invention will be described with reference to the drawings. Hereinafter, an example of an endoscope system including an imaging device will be described.

[0029] FIG. 1 shows a configuration of an endoscope system 1 according to a first embodiment of the present invention. The endoscope system 1 shown in FIG. 1 includes an endoscope insertion unit 2, a transmission cable 3, an operation unit 4, a connector unit 5, a control unit 6, and a display device 7. The endoscope insertion unit 2, the transmission cable 3, the operation unit 4, and the connector unit 5 constitute a scope 8 (endoscope).

[0030] The endoscope insertion unit 2 includes an insertion unit 2a. The insertion unit 2a is part of the transmission cable 3. The insertion unit 2a is to be inserted inside a living body, which is a subject. The endoscope insertion unit 2 generates a video signal by imaging the inside of the subject. The endoscope insertion unit 2 outputs the generated video signal to the control unit 6. A camera unit 9 shown in FIG. 2 is disposed in a distal end 2b of the insertion unit 2a. In the insertion unit 2a, the operation unit 4 is connected to the end part opposite the distal end 2b. The operation unit 4 receives various operations for the endoscope insertion unit 2 from a user.

[0031] The transmission cable 3 connects the camera unit 9 and the connector unit 5. The video signal generated by the camera unit 9 is output to the connector unit 5 via the transmission cable 3.

[0032] The connector unit 5 is connected to the transmission cable 3 and the control unit 6. The connector unit 5 performs predetermined processing on the video signal output from the endoscope insertion unit 2. The connector unit 5 outputs the video signal to the control unit 6.

[0033] The control unit 6 performs image processing on the video signal output from the connector unit 5. Furthermore, the control unit 6 centrally controls the entire endoscope system 1.

[0034] The display device 7 displays a video based on the video signal processed by the control unit 6. In addition, the display device 7 displays various kinds of information related to the endoscope system 1.

[0035] The endoscope system 1 includes the camera unit 9 and the control unit 6 shown in FIG. 2. FIG. 2 shows a configuration of the camera unit 9 and the control unit 6. The camera unit 9 is disposed in the distal end 2b of the scope 8. The operation unit 4, the connector unit 5, and the display device 7 are not shown in FIG. 2. The transmission cable 3 shown in FIG. 1 includes a power source line 14, a video signal line 15, and a reference line 16 shown in FIG. 2. The camera unit 9 and the control unit 6 are connected to each other by the power source line 14, the video signal line 15, and the reference line 16.

[0036] The endoscope system 1 includes a light source device that generates illumination light emitted to the subject. The light source device is not shown in FIG. 2.

[0037] The camera unit 9 includes an image sensor 10. The control unit 6 includes a voltage generation circuit 11, a video-signal-processing circuit 12, and a control circuit 13.

[0038] For example, the voltage generation circuit 11 is a voltage regulator. The voltage generation circuit 11 generates a power source voltage VDD that is a direct-current (DC) voltage and outputs the power source voltage VDD to the power source line 14. For example, the power source voltage VDD is 3.3 V. The power source line 14 is a signal line disposed in the transmission cable 3. The power source line 14 transfers the power source voltage VDD to the camera unit 9. The power source voltage VDD transferred by the power source line 14 is input to the image sensor 10 of the camera unit 9.

[0039] The reference line 16 is a signal line disposed in the transmission cable 3. The reference line 16 transfers a lower reference voltage VSS than the power source voltage VDD from the control unit 6 to the camera unit 9. For example, the reference voltage VSS is a ground voltage (0 V). The reference voltage VSS transferred by the reference line 16 is input to the image sensor 10 of the camera unit 9.

[0040] The image sensor 10 generates a video signal based on the power source voltage VDD and the reference voltage VSS and outputs the video signal to the video signal line 15. The video signal line 15 is a signal line disposed in the transmission cable 3. The video signal line 15 transfers the video signal to the control unit 6.

[0041] The video-signal-processing circuit 12 receives the video signal transferred by the video signal line 15. The video-signal-processing circuit 12 performs predetermined signal processing on the video signal and outputs the video signal to the display device 7. The control circuit 13 controls the operations of the voltage generation circuit 11 and the video-signal-processing circuit 12.

[0042] FIG. 3 shows a configuration of the image sensor 10. The image sensor 10 includes an imaging unit 20, a voltage generation circuit 21, a vertical selection circuit 22, a column circuit unit 23, a horizontal selection circuit 24, and an output unit 25. The circuits in the image sensor 10 operate in accordance with a clock signal provided from a clock generation circuit not shown in FIG. 3. The control unit 6 may include a clock generation circuit, and a clock signal generated by the clock generation circuit may be transferred to the camera unit 9.

[0043] The imaging unit 20 includes two or more pixels 26 disposed in a matrix shape. The two or more pixels 26 constitute an array having m rows and n columns. The number (m) of rows is two or more, and the number (n) of columns is two or more. The number of rows and the number of columns are not necessarily the same. Each pixel 26 outputs a first pixel signal having a reset level and a second pixel signal having a signal level.

[0044] The voltage generation circuit 21 generates a driving voltage that is higher than the reference voltage VSS and is lower than the power source voltage VDD based on the power source voltage VDD and the reference voltage VSS. The driving voltage is output to each pixel 26 via the vertical selection circuit 22.

[0045] The vertical selection circuit 22 selects pixels 26 disposed in the row direction in the array of the two or more pixels 26. The vertical selection circuit 22 controls the operations of the selected pixels 26. The vertical selection circuit 22 outputs control signals used for controlling the two or more pixels 26 for each row in the array of the two or more pixels 26.

[0046] The column circuit unit 23 includes two or more column circuits 27. Each column circuit 27 is disposed for each column in the array of the two or more pixels 26. Each column circuit 27 is connected to a vertical signal line 30 extending in the vertical direction, that is, the column direction. The vertical signal line 30 is disposed for each column in the array of the two or more pixels 26. The vertical signal line 30 is connected to pixels 26 of each column. Each column circuit 27 is electrically connected to each pixel 26 via the vertical signal line 30. Each column circuit 27 holds the first pixel signal and the second pixel signal output from each pixel 26.

[0047] Each column circuit 27 is connected to a first horizontal signal line 28 and a second horizontal signal line 29 extending in the horizontal direction, that is, the row direction. A selection pulse is output from the horizontal selection circuit 24 to each column circuit 27. The column circuit 27 selected based on the selection pulse outputs the first pixel signal to the first horizontal signal line 28 and outputs the second pixel signal to the second horizontal signal line 29.

[0048] One column circuit 27 may be disposed for two or more columns in the array of the two or more pixels 26 and may be used in the two or more columns in a time-division manner. Accordingly, the column circuit 27 has only to be disposed so as to correspond to one or more columns in the array of the two or more pixels 26.

[0049] The first horizontal signal line 28 and the second horizontal signal line 29 are connected to the output unit 25. The horizontal selection circuit 24 sequentially selects the column circuits 27 by sequentially outputting selection pulses to the column circuits 27. The first pixel signal and the second pixel signal output from the column circuit 27 selected by the horizontal selection circuit 24 are transferred to the output unit 25.

[0050] The output unit 25 generates a video signal based on the first pixel signal and the second pixel signal. For example, the video signal is the difference between the first pixel signal and the second pixel signal. The output unit 25 outputs the video signal to the video signal line 15.

[0051] FIG. 4 shows a configuration of the voltage generation circuit 21. The voltage generation circuit 21 includes a transistor 210, a current mirror circuit 211, a capacitor 212, and a transistor 213. The power source voltage VDD, the reference voltage VSS, a current control voltage VIB, a transistor control signal VG1, and a transistor control signal VG2 are input to the voltage generation circuit 21.

[0052] The transistors 210 and 213 are switches. The state of each of the transistors 210 and 213 becomes either an ON state or an OFF state. Each of the transistors 210 and 213 can switch between the ON state and the OFF state.

[0053] The transistor 210, the current mirror circuit 211, the capacitor 212, and the transistor 213 are connected to each other. The transistor control signal VG1 is input to the gate terminal of the transistor 210. The state of the transistor 210 is controlled in accordance with the transistor control signal VG1. When the state of the transistor 210 is the ON state, the transistor 210 outputs the power source voltage VDD.

[0054] The capacitor 212 includes a first terminal 212a and a second terminal 212b. The power source voltage VDD output from the transistor 210 is input to the first terminal 212a. The reference voltage VSS is input to the second terminal 212b. The capacitor 212 holds the power source voltage VDD. As described later, the voltage at the first terminal 212a gradually decreases from the power source voltage VDD. The voltage at the first terminal 212a is output as a driving voltage VTGD.

[0055] The current mirror circuit 211 is a current source. A fixed current IS flows through the current mirror circuit 211 in accordance with the current control voltage VIB. When the state of the transistor 210 is the OFF state, the current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS. By doing this, the current mirror circuit 211 consumes the electric charge held in the capacitor 212 as the current IS. While the current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS, the voltage at the first terminal 212a of the capacitor 212 gradually and smoothly decreases from the power source voltage VDD.

[0056] The transistor control signal VG2 is input to the gate terminal of the transistor 213. The state of the transistor 213 is controlled in accordance with the transistor control signal VG2. While the current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS, the state of the transistor 213 is the OFF state. When the state of the transistor 213 has been set to the ON state, the voltage at the first terminal 212a of the capacitor 212 is reset to the reference voltage VSS.

[0057] The vertical selection circuit 22 includes as many buffer circuits 220 as the number of rows in the array of the two or more pixels 26. The driving voltage VTGD output from the voltage generation circuit 21 is input to all the buffer circuits 220. One buffer circuit 220 is shown in FIG. 4. Each buffer circuit 220 includes an input terminal 220a, an output terminal 220b, a power source terminal 220c, and a power source terminal 220d.

[0058] An input signal TGI<n> is input to the input terminal 220a. The driving voltage VTGD is input to the power source terminal 220c, and a predetermined voltage (for example, −1.5 V) is input to the power source terminal 220d. The input signal TGI<n> has a high (H) voltage or a low (L) voltage. For example, the H voltage is the power source voltage VDD, and the L voltage is the reference voltage VSS. When the voltage of the input signal TGI<n> is the H voltage, an output signal TGO<n> having the driving voltage VTGD is output from the output terminal 220b to each pixel 26.

[0059] FIG. 5 shows a configuration of each pixel 26. The pixel 26 shown in FIG. 5 includes a photoelectric conversion element 260, a transfer transistor 261, a floating diffusion (FD) 262, a reset transistor 263, an amplification transistor 264, and a selection transistor 265.

[0060] The photoelectric conversion element 260 is a photodiode. The photoelectric conversion element 260 performs photoelectric conversion on light incident on the photoelectric conversion element 260 and generates an electric charge in accordance with the amount of the light. The transfer transistor 261 transfers the electric charge generated by the photoelectric conversion element 260 to the FD 262. The FD 262 holds the electric charge transferred by the transfer transistor 261.

[0061] The reset transistor 263 resets the voltage of the FD 262 to a voltage in accordance with the power source voltage VDD. By doing this, the reset transistor 263 resets the electric charge held in the FD 262. The amplification transistor 264 amplifies a signal based on the voltage of the FD 262, thus generating a pixel signal. The selection transistor 265 outputs the pixel signal to the vertical signal line 30. A first pixel signal having a reset level and a second pixel signal having a signal level are output from the pixel 26.

[0062] The vertical selection circuit 22 outputs a reset control signal RS, a transfer control signal TX, and a selection control signal SEL. The reset control signal RS is provided to the reset transistor 263. The transfer control signal TX is provided to the transfer transistor 261. The selection control signal SEL is provided to the selection transistor 265.

[0063] The transfer control signal TX corresponds to the output signal TGO<n> shown in FIG. 4. The transfer control signal TX has the driving voltage VTGD. For example, a range of the driving voltage VTGD in which the operation of the transfer transistor 261 is guaranteed is greater than or equal to 2.4 V and less than or equal to 2.6 V.

[0064] The state of each of the transfer transistor 261, the reset transistor 263, and the selection transistor 265 becomes either an ON state or an OFF state. Each transistor can switch between the ON state and the OFF state.

[0065] The state of the reset transistor 263 is controlled in accordance with the reset control signal RS. The state of the transfer transistor 261 is controlled in accordance with the transfer control signal TX. The state of the selection transistor 265 is controlled in accordance with the selection control signal SEL.

[0066] FIG. 6 shows waveforms of a clock signal CLK, the transistor control signal VG1, the transistor control signal VG2, the driving voltage VTGD, the input signal TGI<n>, and the output signal TGO<n>. The horizontal direction in FIG. 6 indicates time, and the vertical direction in FIG. 6 indicates a voltage value of each signal. An operation of the voltage generation circuit 21 will be described by using FIG. 6.

[0067] The clock signal CLK is provided from the clock generation circuit to the voltage generation circuit 21. The clock signal CLK has the H voltage or the L voltage. The voltage of the clock signal CLK periodically changes between the H voltage and the L voltage. Timings of operations of circuits in the voltage generation circuit 21 are synchronized with the clock signal CLK.

[0068] Before a timing T10, the voltage of the transistor control signal VG1 is the H voltage, and the voltage of the transistor control signal VG2 is the L voltage. Therefore, the state of each of the transistor 210 and the transistor 213 is the OFF state. Before the timing T10, the driving voltage VTGD is the same as the reference voltage VSS. Before the timing T10, the voltage of each of the input signal TGI<n> and the output signal TGO<n> is the L voltage.

[0069] At the timing T10, the voltage of the transistor control signal VG1 changes from the H voltage to the L voltage. Therefore, the state of the transistor 210 changes from the OFF state to the ON state. At this time, the power source voltage VDD is output from the transistor 210 and is input to the first terminal 212a of the capacitor 212. The capacitor 212 holds the power source voltage VDD. The voltage generation circuit 21 outputs the same driving voltage VTGD as the power source voltage VDD.

[0070] At a timing T11 after the timing T10, the voltage of the input signal TGI<n> changes from the L voltage to the H voltage. At this time, the voltage of the output signal TGO<n> changes from the L voltage to the same voltage as the driving voltage VTGD.

[0071] At a timing T12 after the timing T11, the voltage of the transistor control signal VG1 changes from the L voltage to the H voltage. Therefore, the state of the transistor 210 changes from the ON state to the OFF state. The current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS and consumes the electric charge held in the capacitor 212 as the current IS. The voltage of the first terminal 212a of the capacitor 212 is output as the driving voltage VTGD. The driving voltage VTGD is shown in the following Expression (1).

[0072] $\begin{array}{cc}\mathrm{VTGD}=\left(\mathrm{Ctg}/\mathrm{IS}\right)*\left(1/t\right)& \left(1\right)\end{array}$

[0073] In Expression (1), Ctg indicates a capacitance value of the capacitor 212, and t indicates time. As shown in Expression (1), the driving voltage VTGD decreases inversely proportional to time. The speed of a change of the driving voltage VTGD can be controlled by controlling the capacitance value Ctg of the capacitor 212. The voltage of the output signal TGO<n> changes similarly to the driving voltage VTGD.

[0074] In a period from a timing T13 to a timing T14 after the timing T12, the driving voltage VTGD and the voltage of the output signal TGO<n> are greater than or equal to 2.4 V and less than or equal to 2.6 V. This period is necessary for driving the transfer transistor 261 of the pixel 26.

[0075] At a timing T15 after the timing T14, the voltage of the transistor control signal VG2 changes from the L voltage to the H voltage. Therefore, the state of the transistor 213 changes from the OFF state to the ON state. At this time, the voltage of the first terminal 212a of the capacitor 212 is reset to the reference voltage VSS.

[0076] The output signal TGO<n> having the driving voltage VTGD is provided to the transfer transistor 261 in a period including a period from the timing T10 to the timing T15. When the output signal TGO<n> having the driving voltage VTGD that is greater than or equal to 2.4 V and less than or equal to 2.6 V has been applied to the transfer transistor 261, the transfer transistor 261 shows predetermined performance. Before the timing T13, the operation of the transfer transistor 261 is insufficient. However, in a period from the timing T13 to the timing T14, the transfer transistor 261 can reliably transfer the electric charge generated by the photoelectric conversion element 260 to the FD 262. The output signal TGO<n> having the driving voltage VTGD may be provided to the transfer transistor 261 only in the period from the timing T13 to the timing T14.

[0077] A period during which the output signal TGO<n> having the driving voltage VTGD is provided to the transfer transistor 261 may be set in consideration of a change of the power source voltage VDD. As shown in FIG. 7, the output signal TGO<n> changes in accordance with a change of the power source voltage VDD. A line L1 shows a change of the output signal TGO<n> when the power source voltage VDD is a predetermined voltage (for example, 3.3 V). A line L2 shows a change of the output signal TGO<n> when the power source voltage VDD has increased. A line L3 shows a change of the output signal TGO<n> when the power source voltage VDD has decreased.

[0078] The transfer transistor 261 needs to reliably operate in a period (transistor operation period) from a timing T16 to a timing T17. At a timing T18 before the timing T16, the voltage of the output signal TGO<n> shown by the line L1 is 2.6 V. At a timing T19 after the timing T17, the voltage of the output signal TGO<n> shown by the line L1 is 2.4 V.

[0079] The voltage of the output signal TGO<n> shown by the line L2 is higher than 2.6 V from the timing T18 to the timing T16. The voltage of the output signal TGO<n> shown by the line L3 is lower than 2.4 V from the timing T17 to the timing T19. When the power source voltage VDD has increased or decreased, the operation of the transfer transistor 261 is insufficient in a period from the timing T18 to the timing T16 or in a period from the timing T17 to the timing T19.

[0080] The voltage of the output signal TGO<n> shown by the line L2 is greater than or equal to 2.4 V and less than or equal to 2.6 V in the transistor operation period. Similarly, the voltage of the output signal TGO<n> shown by the line L3 is greater than or equal to 2.4 V and less than or equal to 2.6 V in the transistor operation period. In other words, even when the power source voltage VDD changes, the voltage of the output signal TGO<n> in the transistor operation period is greater than or equal to 2.4 V and less than or equal to 2.6 V. Therefore, the transfer transistor 261 can reliably operate in the transistor operation period.

[0081] When the power source voltage VDD is a predetermined voltage, the voltage generation circuit 21 outputs the driving voltage VTGD that is greater than or equal to 2.4 V and less than or equal to 2.6 V in a period that includes the transistor operation period and is longer than the transistor operation period. By doing this, the voltage generation circuit 21 can generate the driving voltage VTGD of a predetermined range in the transistor operation period even when the power source voltage VDD changes.

[0082] In the above-described example, the output signal TGO<n> having the driving voltage VTGD is provided to the transfer transistor 261. In a case in which the reset transistor 263 or the selection transistor 265 is driven by using a voltage between the reference voltage VSS and the power source voltage VDD, the output signal TGO<n> having a voltage generated by using a similar method to that of generating the driving voltage VTGD may be provided to the reset transistor 263 or the selection transistor 265.

[0083] In the first embodiment, the image sensor 10 (imaging device) operates by using the power source voltage VDD. The photoelectric conversion element 260 performs photoelectric conversion and generates an electric charge in accordance with the amount of received light. The transfer transistor 261 is driven by using the driving voltage VTGD. The voltage generation circuit 21 generates the driving voltage VTGD that is lower than the power source voltage VDD and gradually decreases.

[0084] An imaging method of each aspect of the present invention includes an imaging step. The imaging step includes a first step and a second step. The voltage generation circuit 21 generates the driving voltage VTGD that is lower than the power source voltage VDD and gradually decreases in the first step (from the timing T12 to the timing T15). The voltage generation circuit 21 outputs the driving voltage VTGD to the transfer transistor 261 in the second step (from the timing T12 to the timing T15).

[0085] Each aspect of the present invention may include the following modified example. The image sensor 10 (imaging device) is driven by using the clock signal CLK. The voltage generation circuit 21 generates the driving voltage VTGD included in a predetermined voltage range (greater than or equal to 2.4 V and less than or equal to 2.6 V) from a first timing (T13) synchronized with the clock signal CLK to a second timing (T14) that is synchronized with the clock signal CLK and is different from the first timing.

[0086] Each aspect of the present invention may include the following modified example. The voltage generation circuit 21 includes the capacitor 212 and the current mirror circuit 211 (voltage-current conversion circuit). The capacitor 212 holds a voltage. The current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS. After the power source voltage VDD is held in the capacitor 212, the current mirror circuit 211 starts conversion into the current IS. While the current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS, the voltage held in the capacitor 212 gradually decreases and is output as the driving voltage VTGD.

[0087] Each aspect of the present invention may include the following modified example. The FD 262 holds the electric charge generated by the photoelectric conversion element 260. The transfer transistor 261 transfers the electric charge generated by the photoelectric conversion element 260 to the FD 262.

[0088] Each aspect of the present invention may include the following modified example. The image sensor 10 (imaging device) operates by using the reference voltage VSS lower than the power source voltage VDD. The driving voltage VTGD is lower than the power source voltage VDD and is higher than the reference voltage VSS.

[0089] Each aspect of the present invention may include the following modified example. The driving voltage VTGD gradually decreases from a first voltage (for example, 2.6 V) lower than the power source voltage VDD to a second voltage (for example, 2.4 V) that is lower than the first voltage and is higher than the reference voltage VSS.

[0090] Each aspect of the present invention may include the following modified example. An endoscope includes both the scope 8 to be inserted inside a living body and the image sensor 10. The image sensor 10 is disposed in the distal end 2b of the scope 8.

[0091] As shown in FIG. 7, the voltage generation circuit 21 can generate the driving voltage VTGD of a predetermined range in the transistor operation period even when the power source voltage VDD changes. Therefore, the voltage generation circuit 21 can generate the stable driving voltage VTGD.

[0092] In a voltage generation circuit that generates a fixed voltage, many transistors are required in order to generate the voltage with high accuracy. Since the voltage generation circuit 21 generates the driving voltage VTGD that gradually decreases, the number of necessary transistors for the voltage generation circuit 21 decreases. Therefore, the image sensor 10 can be miniaturized.

[0093] The voltage generation circuit 21 generates the driving voltage VTGD that is greater than or equal to 2.4 V and less than or equal to 2.6 V from the timing T13 to the timing T14. The timing T13 and the timing T14 are synchronized with the clock signal CLK. The voltage generation circuit 21 can generate the driving voltage VTGD of a predetermined range in a period determined in accordance with the clock signal CLK.

[0094] A second embodiment of the present invention will be described. The image sensor 10 shown in FIG. 3 is changed to an image sensor 10a shown in FIG. 8. FIG. 8 shows a configuration of the image sensor 10a. The same parts as those shown in FIG. 3 will not be described.

[0095] The image sensor 10a includes an imaging unit 20, two or more voltage generation circuits 21a, a vertical selection circuit 22, a column circuit unit 23, a horizontal selection circuit 24, and an output unit 25. The two or more voltage generation circuits 21a are disposed between the vertical selection circuit 22 and the imaging unit 20. Each voltage generation circuit 21a is disposed so as to correspond to any one of two or more rows.

[0096] In the image sensor 10 shown in FIG. 3, one voltage generation circuit 21 is disposed. The driving voltage VTGD output from the voltage generation circuit 21 is input to the buffer circuit 220 disposed for each row of the two or more rows. Since the distance between the voltage generation circuit 21 and the buffer circuit 220 is different between the two or more rows, a delay of the driving voltage VTGD may occur in accordance with a row position.

[0097] In the image sensor 10a shown in FIG. 8, each voltage generation circuit 21a is disposed for each row of the two or more rows. Therefore, the distance between each voltage generation circuit 21a and the buffer circuit 220 is fixed, and a delay of the driving voltage VTGD does not occur in accordance with a row position.

[0098] FIG. 9 shows a configuration of the voltage generation circuit 21a. The same parts as those shown in FIG. 4 will not be described. The voltage generation circuit 21a includes a transistor 210, a current mirror circuit 211, a capacitor 212, a transistor 213, and an inverter 214. The power source voltage VDD, the reference voltage VSS, the current control voltage VIB, and the transistor control signal VG2 are input to the voltage generation circuit 21a.

[0099] The vertical selection circuit 22 includes as many buffer circuits 220 as the number of rows in the array of the two or more pixels 26 as in the first embodiment. One buffer circuit 220 is shown in FIG. 9. The input signal TGI<n> is input to the buffer circuit 220, and the output signal TGO<n> is output from the buffer circuit 220.

[0100] The output signal TGO<n> is input to the inverter 214. The inverter 214 inverts the voltage of the output signal TGO<n>, thus generating the transistor control signal VG1. The transistor control signal VG1 is output to the gate terminal of the transistor 210.

[0101] The voltage of the first terminal 212a of the capacitor 212 is output as the driving voltage VTGD as in the first embodiment. The driving voltage VTGD is provided to the transfer transistor 261 of each pixel 26.

[0102] FIG. 10 shows waveforms of the clock signal CLK, the input signal TGI<n>, the transistor control signal VG2, the transistor control signal VG1, and the driving voltage VTGD. The horizontal direction in FIG. 10 indicates time, and the vertical direction in FIG. 10 indicates a voltage value of each signal. An operation of the voltage generation circuit 21a will be described by using FIG. 10.

[0103] Before a timing T20, the voltage of the input signal TGI<n> is the L voltage. Before the timing T20, the voltage of the transistor control signal VG2 is the L voltage, and the voltage of the transistor control signal VG1 is the H voltage. Therefore, the state of each of the transistor 213 and the transistor 210 is the OFF state. Before the timing T20, the driving voltage VTGD is the same as the reference voltage VSS.

[0104] At the timing T20, the voltage of the input signal TGI<n> changes from the L voltage to the H voltage. The voltage of the output signal TGO<n> changes from the L voltage to the H voltage in accordance with the change of the voltage of the input signal TGI<n>. The voltage of the transistor control signal VG1 changes from the H voltage to the L voltage in accordance with the change of the voltage of the output signal TGO<n>. Therefore, the state of the transistor 210 changes from the OFF state to the ON state. At this time, the power source voltage VDD is output from the transistor 210 and is input to the first terminal 212a of the capacitor 212. The capacitor 212 holds the power source voltage VDD. The voltage generation circuit 21a outputs the same driving voltage VTGD as the power source voltage VDD.

[0105] At a timing T21 after the timing T20, the voltage of the input signal TGI<n> changes from the H voltage to the L voltage. The voltage of the output signal TGO<n> changes from the H voltage to the L voltage in accordance with the change of the voltage of the input signal TGI<n>. The voltage of the transistor control signal VG1 changes from the L voltage to the H voltage in accordance with the change of the voltage of the output signal TGO<n>. Therefore, the state of the transistor 210 changes from the ON state to the OFF state.

[0106] The current mirror circuit 211 converts the voltage held in the capacitor 212 into the current IS and consumes the electric charge held in the capacitor 212 as the current IS. The voltage of the first terminal 212a of the capacitor 212 is output as the driving voltage VTGD. The driving voltage VTGD decreases inversely proportional to time.

[0107] In a period from a timing T22 to a timing T23 after the timing T21, the driving voltage VTGD is greater than or equal to 2.4 V and less than or equal to 2.6 V. This period is necessary for driving the transfer transistor 261 of the pixel 26.

[0108] At a timing T24 after the timing T23, the voltage of the transistor control signal VG2 changes from the L voltage to the H voltage. Therefore, the state of the transistor 213 changes from the OFF state to the ON state. At this time, the voltage of the first terminal 212a of the capacitor 212 is reset to the reference voltage VSS.

[0109] Each aspect of the present invention may include the following modified example. The image sensor 10 (imaging device) includes two or more voltage generation circuits 21a. The two or more pixels 26 are disposed in a matrix shape including two or more rows and two or more columns. Each of the two or more voltage generation circuits 21a is disposed so as to correspond to any one of the two or more rows.

[0110] Each aspect of the present invention may include the following modified example. The vertical selection circuit 22 outputs the output signal TGO<n> for each row of the two or more rows. Each of the two or more voltage generation circuits 21a outputs the driving voltage VTGD to a pixel 26 included in the two or more pixels 26 when the output signal TGO<n> output from the vertical selection circuit 22 has been received.

[0111] As described above, the voltage generation circuit 21a generates the driving voltage VTGD that is lower than the power source voltage VDD and gradually decreases. The voltage generation circuit 21a can generate the stable driving voltage VTGD as in the first embodiment.

[0112] The two or more voltage generation circuits 21a are disposed between the vertical selection circuit 22 and the imaging unit 20. Therefore, delays in the driving voltage VTGD are restricted.

[0113] While preferred embodiments of the invention have been described and shown above, it should be understood that these are examples of the invention and are not to be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit or scope of the present invention. Accordingly, the invention is not to be considered as being limited by the foregoing description, and is only limited by the scope of the appended claims.