Memory system and method for operating the same

[0001] The present application is a continuation of U.S. patent application Ser. No. 17/882,112 filed on Aug. 5, 2022, which claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0032713, filed on Mar. 16, 2022, which is incorporated herein by reference in its entirety.

[0002] The present technology relates to a semiconductor integrated apparatus, and more particularly, to a memory system and a method for operating the same.

[0003] A memory system performs a data input/output operation in response to an external request by using a memory device as a storage medium.

[0004] A memory system may adopt various storage media, and may use, for example, a nonvolatile memory device, such as a flash memory device, as a storage medium.

[0005] A memory system may simultaneously access a plurality of storage areas constituting a storage medium and respond to an external request with high performance. However, performance improvement of a memory system may cause an increase in power consumption and an increase in temperature due to the increase in power consumption.

[0006] Accordingly, it is necessary to control the performance or power consumption of a memory system adaptively to an environment of the memory system and a computing system to which the memory system is applied.

[0007] A memory system in accordance with an embodiment of the present technology may include: a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.

[0008] A memory system in accordance with an embodiment of the present technology may include: a memory device including a plurality of memory dies each including a plurality of memory blocks; and a memory controller configured to generate a zone by grouping the memory blocks selected from at least one of the memory dies included in the memory device, write, according to an external write request, data into an open zone, to which a write buffer is allocated, by simultaneously accessing memory dies associated with the open zone, and determine a number of active target memory dies associated with the open zone on a basis of a number of the memory dies associated with the open zone.

[0009] A method for operating a memory system in accordance with an embodiment of the present technology may include: generating zones by grouping memory blocks selected from at least one of memory areas each configured by a plurality of memory blocks included in a memory device; managing configuration information for each of the generated zones; and determining a number of active target memory areas associated with an open zone on a basis of the configuration information of the open zone in order to perform a write operation on the open zone according to an external write request.

[0010] A method for operating a memory system in accordance with an embodiment of the present technology may include: mapping each zone with one or more of total memory dies; and accessing a number of memory dies, which are selected from the memory dies mapped with a selected zone, according to an interleaving scheme. Wherein the number is expressed by an equation A=B*(C/D), where: ‘A’ represents the number, ‘B’ represents a predetermined number of memory dies, which can become active among the memory dies, ‘C’ represents a number of memory dies, which are mapped with the selected zone and one or more open zones, and ‘D’ represents a number of the total memory dies.

[0022] Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

[0023] FIG. 1 is a configuration diagram of an electronic device 10 in accordance with an embodiment of the present disclosure.

[0024] Referring to FIG. 1, the electronic device 10 in accordance with an embodiment may include a memory system 200 that performs data exchange with the outside. In the following description, the “outside” may be an external device 100, and the electronic device 10 may include, for example, a host device to which the memory system is connected.

[0025] The external device 100 and the memory system 200 may be connected through an interface IF. The IF may provide a physical connection between the external device 100 and the memory system 200.

[0026] The memory system 200 may include a memory controller 210 and a memory device 220.

[0027] The memory controller 210 may control the memory device 220 in response to a request of the external device 100. For example, the memory controller 210 may allow data to be programmed in the memory device 220 according to a write request of the external device 100. Furthermore, the memory controller 210 may provide data written in the memory device 220 to the external device 100 in response to a read request of the external device 100.

[0028] The memory device 220 may write data or output the written data through at least one channel CH in response to a command and/or data transmitted from the memory controller 210. The memory device 220 may be configured as a volatile or a nonvolatile memory device. In an embodiment, the memory device 220 may be implemented using a memory element selected from various nonvolatile memory elements such as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a spin transfer torque magnetic RAM (STT-MRAM). The memory device 220 may include a plurality of dies, a plurality of chips, or a plurality of packages. In addition, the memory device 220 may operate as a single-level cell that stores one-bit data in one memory cell or a multi-level cell that stores multiple bits of data in one memory cell.

[0029] Although not illustrated, the memory system 200 may further include a buffer memory. The buffer memory serves as a space capable of temporarily storing data when the memory system 200 performs a series of operations such as writing or reading data in cooperation with the external device 100. The buffer memory may be provided outside or inside the memory controller 210, or may be allocated as a part of the memory device 220.

[0030] FIG. 2 is a configuration diagram of the memory device 220 in accordance with an embodiment of the present disclosure.

[0031] Referring to FIG. 2, the memory device 220 may include a plurality of memory areas, for example, memory dies DIE.

[0032] Each of the plurality of memory dies DIE may include one or more planes PLANE, and each of the planes PLANE may include one or more memory blocks BLK. Although not illustrated, each of the memory blocks BLK may include a plurality of pages.

[0033] The memory controller 210 may group the plurality of memory blocks BLK selected from the plurality of memory dies DIE to form a block group referred to as a super block (SB) or a zoned name space (ZNS).

[0034] The block group is obtained by logically grouping the plurality of memory blocks BLK included in the memory device 220, and the memory blocks BLK included in the block group may be simultaneously accessed by an interleaving method.

[0035] FIG. 3 is a diagram for describing the concept of the zoned name space in accordance with an embodiment of the present disclosure.

[0036] In the following description, the zoned name space may be referred to as “ZNS” or “zone”.

[0037] The ZNS has been introduced to provide high performance between a plurality of operating systems and a plurality of application programs without interference in a data center of a multi-tenant environment.

[0038] The memory controller 210 may operate the memory device 220 so that each of the plurality of application programs sequentially stores data in a zone allocated to each of the plurality of application programs.

[0039] The zone may be a logically and physically separated memory area. Each of the application programs may sequentially store data in a zone allocated to each of the application programs. Accordingly, it is possible to solve performance degradation due to garbage collection occurring in managing a memory device configured as a nonvolatile memory device.

[0040] Referring to FIG. 3, the memory controller 210 may group memory blocks selected from a plurality of dies DIE1, DIE2, DIE3, DIE4, DIE5, DIE6, DIE7, . . . in response to a write request from a host, and manage the grouped memory blocks as zones ZNS1 to ZNS4. The zones ZNS1 to ZNS4 may be generated with substantially the same size or different sizes for each application program that provides write data.

[0041] In an embodiment, a first zone ZNS1 may include memory blocks selected from first to sixth dies DIE1 to DIE6. Each of a second zone ZNS2 and a third zone ZNS3 may include memory blocks selected from the first to third dies DIE1 to DIE3. A fourth zone ZNS4 may include memory blocks selected from the first to fourth dies DIE1 to DIE4.

[0042] The memory blocks included in each of the zones ZNS1 to ZNS4 may be simultaneously accessed by a die interleaving or channel interleaving method. For example, in order to operate the memory device 220 by a die interleaving method, the memory controller 210 may select memory blocks having substantially the same or different offsets from each plane PLANE of each die DIE to form the zones ZNS1 to ZNS4.

[0043] FIG. 4 is a diagram for describing the state of a zone in accordance with an embodiment of the present disclosure.

[0044] The state of a zone generated according to a request of the external device 100 may be divided into active zones ACTIVE ZONES and inactive zones INACTIVE ZONES as illustrated in FIG. 4.

[0045] Zones included in the active zones may include open zones OPEN in an open state and/or closed zones CLOSED in a closed state. Zones included in the inactive zones INACTIVE ZONES may include empty zones EMPTY in an empty state and/or full zones FULL in a full state.

[0046] In order to write data in a zone, the memory controller 210 may allocate a part of a buffer memory as a write buffer for each write target zone. The open zone OPEN may refer to a zone selected for performing a write operation, that is, a zone to which an area of a write buffer is allocated, and the memory system 200 may perform a program operation on a memory block included in the open zone OPEN.

[0047] When a program command for a zone other than an open zone OPEN is generated in a state in which all areas of the write buffer are allocated to the open zone OPEN, the memory controller 210 may switch at least one of the open zones OPEN to a closed zone CLOSED. That is, the closed zone CLOSED may be switched from the open zone OPEN.

[0048] When data are all programed in all pages of a memory block corresponding to an open zone OPEN, the memory controller 210 switches the open zone OPEN to a closed zone CLOSED and then switches the closed zone CLOSED to a full zone FULL. The full zone FULL refers to a zone in which data are written in all pages within a corresponding memory block. When an application program, that is, the external device 100 provides the memory system 200 with an erase command for a full zone FULL or active zones ACTIVE ZONES, the memory system 200 erases a corresponding full zone FULL and the memory controller 210 switches the full zone FULL to an empty zone EMPTY. The empty zone EMPTY refers to a zone in which a corresponding memory block is an empty memory block.

[0049] The memory system 200 may simultaneously access a plurality of dies mapped to a zone to write data therein, read data therefrom or erase data therefrom according to a die interleaving method, thereby improving the performance of the memory system 200. The performance improvement of the memory system 200 causes an increase in power consumption and heat generation due to the increase in power consumption. Accordingly, the memory system 200 may simultaneously access the optimum number of active dies mapped to a zone. In a normal mode, the optimum number of active dies may be a predefined maximum number of active dies, that is, the maximum number of allowed active dies. In an embodiment, the active die refers to a die selected by a die address included in an active command in order to process a command for a zone.
optimum number of active dies (normal mode)=maximum number of allowed active dies  [Equation 1]

[0050] On the other hand, in a throttling mode in which the temperature of the memory system 200 increases above a threshold value and thermal throttling is required, die management policy may be used to limit the optimum number of active dies to less than the maximum number of allowed active dies.

[0051] In a ZNS environment in which data is stored by allowing zones having substantially the same size or different sizes for each application program, the number of dies to be switched to an active state may vary depending on how an open zone is configured. Accordingly, in a case where the memory system 200 operates based on the ZNS and is not in the throttling mode, when the maximum number of allowed active dies mapped to a zone can be limited to the optimum number of active dies mapped to a zone, power may be unnecessarily consumed.

[0052] In the present technology, it is possible to reduce power consumption of the electronic device 10 in addition to the memory system 200 by dynamically determining the optimum number of active dies mapped to an open zone according to the number of dies associated with the open zone, that is, the number of dies mapped to the open zone.

[0053] FIG. 5 is a configuration diagram of the memory controller 210 in accordance with an embodiment of the present disclosure.

[0054] Referring to FIG. 5, the memory controller 210 in accordance with an embodiment may include a processor 211, an external device interface EXTERNAL DEVICE IF 213, a ROM 2151, a RAM 2153, a memory interface MEMORY IF 217, and an active die manager 30.

[0055] The processor 211 may be configured to transfer various types of control information required for a read or write operation of data on the memory device 220 to the external device IF 213, the RAM 2153, the memory IF 217, and the active die manager 30. In an embodiment, the processor 211 may operate according to firmware provided for various operations of the memory system 200. In an embodiment, the processor 211 may perform a function of a flash translation layer (FTL) for performing garbage collection, address mapping, wear leveling, and the like for managing the memory device 220, a function of detecting and correcting an error of data read from the memory device 220, and the like.

[0056] The external device IF 213 may provide a communication channel for receiving a command and a clock signal from the external device 100 under the control of the processor 211, and controlling input/output of data. Particularly, the external device IF 213 may provide a physical connection between the external device 100 and the memory system 200. Furthermore, the external device IF 213 may provide interfacing with the memory system 200 corresponding to a bus format of the external device 100. The bus format of the external device 100 may include at least one of communication standards or interfaces such as a secure digital, a universal serial bus (USB), a multi-media card (MMC), an embedded MMC (eMMC), a personal computer memory card international association (PCMCIA), a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI), a PCI express (PCI-e or PCIe), and a universal flash storage (UFS).

[0057] The bus format of the external device 100 may further include at least one of a system management bus (SMBus), an inter-integrated circuit (I2C), and improved inter-integrated circuit (I3C) protocols.

[0058] The ROM 2151 may store program codes required for an operation of the memory controller 210, for example, firmware or software, code data used by the program codes, and the like.

[0059] The RAM 2153 may store data required for the operation of the memory controller 210, or data generated by the memory controller 210.

[0060] The MEMORY IF 217 may provide a communication channel for signal transmission/reception between the memory controller 210 and the memory device 220. The memory IF 217 may transfer data to be written to the memory device 220 or receive data read from the memory device 220, under the control of the processor 211.

[0061] The active die manager 30 may determine the optimum number of active dies on the basis of the number of dies associated with an open zone.

[0062] Specifically, the active die manager 30 may calculate the number of dies mapped to the open zone as the number of associated dies by referring to configuration information of each zone, and determine the optimum number of active dies by adjusting the maximum number of active dies according to the number of associated dies mapped to the zone.

[0063] FIG. 6 is a configuration diagram of the active die manager 30 in accordance with an embodiment of the present disclosure.

[0064] Referring to FIG. 6, the active die manager 30 in accordance with an embodiment may include a ZNS information storage memory 301, a mapping die checking circuit 302, and an active die determination circuit 303.

[0065] The ZNS information storage memory 300 may store configuration information of each zone generated according to a request of the external device 100. The configuration information of the zone may include a zone identifier ZID and the number of dies associated with or mapped to a corresponding zone.

[0066] The mapping die checking circuit 302 may detect the number of dies associated with a zone to be opened as “the number of to-be-opened zone-dies” as a zone open command including a zone identifier ZID is transmitted from the external device 100. Furthermore, on the basis of identifiers OZID of already-opened zones, the mapping die checking circuit 302 may detect the number of dies associated with an already-opened zone as “the number of already-opened zone-dies”. The mapping die checking circuit 302 may output “the number of associated dies N_OPENDIE” by summing the number of to-be-opened zone-dies and the number of already-opened zone-dies.

[0067] The active die determination circuit 303 may determine the optimum number of active dies N_OPTDIE by adjusting the maximum number of allowed active dies N_ALLOWDIE on the basis of the number of associated dies N_OPENDIE.

[0068] In an embodiment, the active die determination circuit 303 may determine the optimum number of active dies N_OPTDIE mapped to the to-be-opened zone by adjusting the maximum number of allowed active dies N_ALLOWDIE mapped to the to-be-opened zone by the ratio of the number of associated dies N_OPENDIE mapped to the to-be-opened zone to the total number of dies N_TOTALDIE included in the memory device 220. For example, the active die determination circuit 303 may determine the optimum number of active dies N_OPTDIE mapped to the to-be-opened zone on the basis of Equation 2 below, but is not limited thereto.
N_OPTDIE=N_ALLOWDIE*(N_OPENDIE/N_TOTALDIE)  [Equation 2]

[0069] FIG. 7 is a flowchart for describing a method for operating the memory system 200 in accordance with an embodiment of the present disclosure, and specifically, a diagram for describing a method for determining the optimum number of active dies.

[0070] The memory controller 210 of the memory system 200 may generate zones according to a request of the external device 100, and store configuration information of each of the generated zones. The configuration information of a zone may include a zone identifier and the number of dies associated with or mapped to the zone.

[0071] In such a state, as a zone open command including a zone identifier is transmitted from the external device 100 (S101), the memory controller 210 may detect the number of dies associated with a zone to be opened as “the number of to-be-opened zone-dies” (S103).

[0072] On the basis of identifiers OZID of already-opened zones, the memory controller 210 may detect the number of dies associated with the already-opened zones as “the number of already-opened zone-dies”, and calculate “the number of associated dies N_OPENDIE” by adding the number of to-be-opened zone-dies and the number of already-opened zone-dies (S105).

[0073] On the basis of the number of associated dies N_OPENDIE, the memory controller 210 may determine the number of active target dies, that is, the optimum number of active dies N_OPTDIE by adjusting the maximum number of allowed active dies N_ALLOWDIE (S107).

[0074] When an open zone does not use all dies in the memory system 200 operating based on the ZNS, that is, when all dies in the memory device 220 are not mapped to the open zone, even though the number of active dies is adaptively reduced according to the number of dies associated with the opened zone, performance of the memory system 200 required by the external device 100 may be satisfied.

[0075] For example, in relation to Equation 2 above, the maximum number of associated dies capable of satisfying the performance of the memory system 200 required by the external device 100 when the total number of dies N_TOTALDIE is 100 and the maximum number of allowed active dies N_ALLOWDIE is 20.

[0076] When the actual number of associated dies for an open zone is 50, even though the optimum number of active dies is limited to 10 (=20*(50/100)), the performance of the memory system 200 required by the external device 100 may be satisfied.

[0077] When the optimum number of active dies N_OPTDIE is determined to be 20 that is the maximum number of allowed active dies N_ALLOWDIE, ⅕ (=20/100) of the total number 100 of accessible dies is active. This is because, even when the optimum number of active dies N_OPTDIE is reduced to 10 (=20*(50/100)) according to the number 50 of associated dies N_OPENDIE, ⅕ (=10/50) of 50 open dies are active.

[0078] Accordingly, when the maximum number of allowed active dies N_ALLOWDIE is fixed in the ZNS environment, performance exceeding the required performance is exhibited depending on how many dies are associated with an open zone, which may cause unnecessary power consumption.

[0079] However, according to the present technology, the optimum number of active dies N_OPTDIE is dynamically determined according to the number of dies associated with an open zone, which makes it possible to optimize power consumption while providing required performance.

[0080] FIG. 8 is a diagram illustrating a data storage system 1000, in accordance with an embodiment of the present disclosure.

[0081] Referring to FIG. 8, the data storage 1000 may include a host device 1100 and the data storage device 1200. In an embodiment, the data storage device 1200 may be configured as a solid state drive (SSD).

[0082] The data storage device 1200 may include a controller 1210, a plurality of nonvolatile memory devices 1220-0 to 1220-n, a buffer memory device 1230, a power supply 1240, a signal connector 1101, and a power connector 1103.

[0083] The controller 1210 may control general operations of the data storage device 1200. The controller 1210 may include a host interface unit, a control unit, a random access memory used as a working memory, an error correction code (ECC) unit, and a memory interface unit. In an embodiment, the controller 1210 may be configured as controller 110 shown in FIGS. 5 and 6.

[0084] The host device 1100 may exchange a signal with the data storage device 1200 through the signal connector 1101. The signal may include a command, an address, data, and so forth.

[0085] The controller 1210 may analyze and process the signal received from the host device 1100. The controller 1210 may control operations of internal function blocks according to firmware or software for driving the data storage device 1200.

[0086] The buffer memory device 1230 may temporarily store data to be stored in at least one of the nonvolatile memory devices 1220-0 to 1220-n. Further, the buffer memory device 1230 may temporarily store the data read from at least one of the nonvolatile memory devices 1220-0 to 1220-n. The data temporarily stored in the buffer memory device 1230 may be transmitted to the host device 1100 or at least one of the nonvolatile memory devices 1220-0 to 1220-n according to control of the controller 1210.

[0087] The nonvolatile memory devices 1220-0 to 1220-n may be used as storage media of the data storage device 1200. The nonvolatile memory devices 1220-0 to 1220-n may be coupled with the controller 1210 through a plurality of channels CH0 to CHn, respectively. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to each channel may be coupled to the same signal bus and data bus.

[0088] The power supply 1240 may provide power inputted through the power connector 1103 to the controller 1210, the nonvolatile memory devices 1220-0 to 1220-n and the buffer memory device 1230 of the data storage device 1200. The power supply 1240 may include an auxiliary power supply. The auxiliary power supply may supply power to allow the data storage device 1200 to be normally terminated when a sudden power interruption occurs. The auxiliary power supply may include bulk-capacity capacitors sufficient to store the needed charge.

[0089] The signal connector 1101 may be configured as one or more of various types of connectors depending on an interface scheme between the host device 1100 and the data storage device 1200.

[0090] The power connector 1103 may be configured as one or more of various types of connectors depending on a power supply scheme of the host device 1100.

[0091] FIG. 9 is a diagram illustrating a data processing system 3000, in accordance with an embodiment of the present disclosure. Referring to FIG. 9, the data processing system 3000 may include a host device 3100 and a memory system 3200.

[0092] The host device 3100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the function of a host device.

[0093] The host device 3100 may include a connection terminal 3110, such as a socket, a slot, or a connector. The memory system 3200 may be mated to the connection terminal 3110.

[0094] The memory system 3200 may be configured in the form of a board, such as a printed circuit board. The memory system 3200 may be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory device 3220, nonvolatile memory devices 3231 and 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0095] The controller 3210 may control general operations of the memory system 3200. The controller 3210 may be configured in the same manner as the controller 110 shown in FIGS. 5 and 6.

[0096] The buffer memory device 3220 may temporarily store data to be stored in the nonvolatile memory devices 3231 and 3232. Further, the buffer memory device 3220 may temporarily store data read from the nonvolatile memory devices 3231 and 3232. The data temporarily stored in the buffer memory device 3220 may be transmitted to the host device 3100 or the nonvolatile memory devices 3231 and 3232 according to control of the controller 3210.

[0097] The nonvolatile memory devices 3231 and 3232 may be used as storage media of the memory system 3200.

[0098] The PMIC 3240 may provide the power inputted through the connection terminal 3250 to the inside of the memory system 3200. The PMIC 3240 may manage the power of the memory system 3200 according to control of the controller 3210.

[0099] The connection terminal 3250 may be coupled to the connection terminal 3110 of the host device 3100. Through the connection terminal 3250, signals such as commands, addresses, data, and so forth, and power may be transferred between the host device 3100 and the memory system 3200. The connection terminal 3250 may be configured as one or more of various types depending on an interface scheme between the host device 3100 and the memory system 3200. The connection terminal 3250 may be disposed on a side of the memory system 3200, as shown.

[0100] FIG. 10 is a diagram illustrating a data processing system 4000 in accordance with an embodiment of the present disclosure. Referring to FIG. 10, the data processing system 4000 may include a host device 4100 and a memory system 4200.

[0101] The host device 4100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal function blocks for performing the function of a host device.

[0102] The memory system 4200 may be configured in the form of a surface-mounted type package. The memory system 4200 may be mounted to the host device 4100 through solder balls 4250. The memory system 4200 may include a controller 4210, a buffer memory device 4220, and a nonvolatile memory device 4230.

[0103] The controller 4210 may control general operations of the memory system 4200. The controller 4210 may be configured in the same manner as the controller 110 shown in FIGS. 5 and 6.

[0104] The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230. Further, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory device 4230. The data temporarily stored in the buffer memory device 4220 may be transmitted to the host device 4100 or the nonvolatile memory device 4230 according to control of the controller 4210.

[0105] The nonvolatile memory device 4230 may be used as the storage medium of the memory system 4200.

[0106] FIG. 11 is a diagram illustrating a network system 5000 including a data storage device, in accordance with an embodiment of the present disclosure. Referring to FIG. 11, the network system 5000 may include a server system 5300 and a plurality of client systems 5410, 5420, and 5430, which are coupled through a network 5500.

[0107] The server system 5300 may service data in response to requests from the plurality of client systems 5410 to 5430. For example, the server system 5300 may store the data provided by the plurality of client systems 5410 to 5430. For another example, the server system 5300 may provide data to the plurality of client systems 5410 to 5430.

[0108] The server system 5300 may include a host device 5100 and

[0109] a memory system 5200. The memory system 5200 may be include the memory controller 210 and memory device 220 shown in FIGS. 1 to 6.

[0110] FIG. 12 is a block diagram illustrating a nonvolatile memory device 300 included in a data storage device, such as the data storage device 10, in accordance with an embodiment of the present disclosure. Referring to FIG. 12, the nonvolatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read/write block 330, a column decoder 340, a voltage generator 350, and a control logic 360.

[0111] The memory cell array 310 may include memory cells MC which are arranged at areas where word lines WL1 to WLm and bit lines BL1 to BLn intersect with each other.

[0112] The memory cell array 310 may comprise a three-dimensional memory array. The three-dimensional memory array, for example, has a stacked structure in a perpendicular direction to the flat surface of a semiconductor substrate. Moreover, the three-dimensional memory array means a structure including NAND strings which memory cells comprised in NAND strings are stacked perpendicular to the flat surface of a semiconductor substrate.

[0113] The structure of the three-dimensional memory array is not limited to the embodiment indicated above. The memory array structure can be formed in a highly integrated manner with horizontal directionality as well as vertical directionality. In an embodiment, in the NAND strings of the three-dimensional memory array memory cells are arranged in the horizontal and vertical directions with respect to the surface of the semiconductor substrate. The memory cells may be variously spaced to provide different degrees of integration

[0114] The row decoder 320 may be coupled with the memory cell array 310 through the word lines WL1 to WLm. The row decoder 320 may operate according to control of the control logic 360. The row decoder 320 may decode an address provided by an external device (not shown). The row decoder 320 may select and drive the word lines WL1 to WLm, based on a decoding result. For instance, the row decoder 320 may provide a word line voltage, provided by the voltage generator 350, to the word lines WL1 to WLm.

[0115] The data read/write block 330 may be coupled with the memory cell array 310 through the bit lines BL1 to BLn. The data read/write block 330 may include read/write circuits RW1 to RWn, respectively, corresponding to the bit lines BL1 to BLn. The data read/write block 330 may operate according to control of the control logic 360. The data read/write block 330 may operate as a write driver or a sense amplifier, according to an operation mode. For example, the data read/write block 330 may operate as a write driver, which stores data provided by the external device in the memory cell array 310 in a write operation. For another example, the data read/write block 330 may operate as a sense amplifier, which reads out data from the memory cell array 310 in a read operation.

[0116] The column decoder 340 may operate according to control of the control logic 360. The column decoder 340 may decode an address provided by the external device. The column decoder 340 may couple the read/write circuits RW1 to RWn of the data read/write block 330, respectively corresponding to the bit lines BL1 to BLn, with data input/output lines or data input/output buffers, based on a decoding result.

[0117] The voltage generator 350 may generate voltages to be used in internal operations of the nonvolatile memory device 300. The voltages generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. For example, a program voltage generated in a program operation may be applied to a word line of memory cells for which the program operation is to be performed. For another example, an erase voltage generated in an erase operation may be applied to a well area of memory cells for which the erase operation is to be performed. For still another example, a read voltage generated in a read operation may be applied to a word line of memory cells for which the read operation is to be performed.

[0118] The control logic 360 may control general operations of the nonvolatile memory device 300, based on control signals provided by the external device. For example, the control logic 360 may control operations of the nonvolatile memory device 300 such as read, write, and erase operations of the nonvolatile memory device 300.

[0119] The above-described embodiments of the present disclosure are intended to illustrate and not to limit embodiments of the present disclosure. Various alternatives and equivalents are possible. The invention is not limited by the embodiments described herein. Nor is the invention limited to any specific type of semiconductor device. Other additions, subtractions, or modifications are apparent in view of the present disclosure and are intended to fall within the scope of the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.