US 12,667,022 B1Grant
Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
Issue Date:2026-06-23
•23 Claims
•12 Drawing Sheets
Abstract
A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.
Metadata
Assignee
- Eliyan Corp.
Inventors
- Ramin Farjadrad
- Syrus Ziai
Application Information
Application Number:US 18/396,311
Filing Date:2023-12-26
Priority Date:2021-05-06
Art Unit:2899
Classifications
IPC:
H10W90/00H10W72/00
Field of Search:
H01L 25/16H01L 25/165H10W 90/10H10W 70/611-618H10W 70/6528
Patent Drawings (12 sheets)
Description
INCORPORATED DISCLOSURES
[0001] Priority Claim. This Application describes technologies that can be used with embodiments, and other technologies, described in one or more of the following documents. This Application is a Continuation of U.S. patent application Ser. No. 17/994,205, titled “Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates”, filed Nov. 25, 2022, which is a Continuation-In-Part of U.S. patent application Ser. No. 17/737,966, titled “Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates”, filed May 5, 2022, which claims priority to U.S. Provisional Patent Application Ser. No. 63/184,842, titled “Implementing complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over MCM package substrates”, filed May 6, 2021, and U.S. Provisional Patent Application Ser. No. 63/283,265, filed Nov. 25, 2021, entitled ENABLING ADVANCE SYSTEM-IN-PACKAGE ARCHITECTURES AT LOW-COST USING HIGH-BANDWIDTH ULTRA-SHORT-REACH (USR) CONNECTIVITY IN MCM PACKAGES, all of which are incorporated herein by reference in their entirety.
[0002] This application claims priority of the following documents, and all documents which those documents incorporate by reference.
-
- [0003] U.S. Provisional Appl. 63/184,842, filed May 6, 2021, in the name of first inventor Syrus Ziai, titled “Implementing complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over MCM package substrates”.
- [0004] U.S. Provisional Appl. 63/190,170, filed May 18, 2021, in the name of first inventor Ramin Farjadrad, titled “Novel architecture for DRAM control optimization using simultaneous bidirectional memory interfaces”.
- [0005] U.S. Provisional Appl. 63/283,265, filed Nov. 25, 2021, in the name of first inventor Ramin Farjadrad, titled “Enabling advance system-in-package architectures at low-cost using high-bandwidth ultra-short-reach (USR) connectivity in MCM packages”.
- [0006] U.S. Provisional Appl. 63/295,524, filed Dec. 31, 2021, in the name of first inventor Ramin Farjadrad, titled “Innovative low-cost packaging solutions for system in package and the HBM crossover PHY architecture”.
- [0007] U.S. application Ser. No. 16/812,234, filed Mar. 6, 2020, in the name of first inventor Mohsen F. Rad, titled “Low cost solution for 2.5D and 3D packaging using USR chiplets”.
[0008] This Application also claims priority of the following documents, and all documents which those documents incorporate by reference.
-
- [0009] U.S. Pat. No. 10,572,416, issued Feb. 25, 2020, titled “Efficient signaling scheme for high-speed ultra short reach interfaces”.
- [0010] U.S. Pat. No. 10,642,767, issued May 5, 2020, titled “Efficient signaling scheme for high-speed ultra short reach interfaces”.
- [0011] U.S. Pat. No. 10,552,353, issued Feb. 4, 2020, titled “Simultaneous bidirectional serial link interface with optimized hybrid circuit”.
- [0012] U.S. Pat. No. 10,855,498, issued Dec. 1, 2020, titled “Efficient signaling scheme for high-speed ultra short reach interfaces”.
- [0013] U.S. application Ser. No. 16/365,510, filed Mar. 26, 2019, titled “Multi-chip module with configurable multi-mode serial link”.
- [0014] U.S. application Ser. No. 16/867,442, filed May 5, 2020, titled “Efficient signaling scheme for high-speed ultra short reach interfaces”.
- [0015] U.S. application Ser. No. 17/108,519, filed Dec. 1, 2020, titled “Efficient signaling scheme for high-speed ultra short reach interfaces”.
- [0016] U.S. application Ser. No. 17/521,612, filed Oct. 8, 2021, titled “Efficient signaling scheme for high-speed ultra short reach interfaces”.
[0017] These documents are hereby incorporated by reference as if fully set forth herein. Techniques described in this Application can be elaborated with detail found therein. These documents are sometimes referred to herein as the “Incorporated Disclosure,” the “Incorporated Document,” or variants thereof.
COPYRIGHT NOTICE
[0018] A portion of the disclosure of this patent document contains material subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND
[0019] This background is provided as a convenience to the reader and does not admit to any prior art or restrict the scope of the disclosure or the invention. This background is intended as an introduction to the general nature of technology to which the disclosure or the invention can be applied.
[0020] Systems of circuits that are integrated onto a single chip, sometimes called “systems on a chip”, and related terms, often involve a very large number of circuit elements being constructed on a single silicon die. As systems on a chip become more complex, it is often desirable to integrate more circuit elements on a silicon die. One way to increase the number of circuit elements on a silicon die is to make those circuit elements smaller.
[0021] A desire to make circuit elements smaller prompts the development of process technology that allows construction of circuit elements that have smaller dimensions, such as side lengths and widths. However, one problem that has arisen in the art is that smaller circuit elements involve more careful control of construction and placement of those circuit elements. Moreover, process technology has not been able to keep up with market desires to reduce the size of circuit elements. This has led to a desire for other solutions that are not subject to such drawbacks.
[0022] One proposed solution has been to make individual chips that each do not involve so many individual circuit elements, sometimes called “chiplets”, and to combine those chiplets into a system having multiple such chiplets. While this proposed solution can provide the ability to create systems that have a sufficient number of circuit elements, it poses the problem that communication between those circuit elements can be limited by a number of connecting wires between chiplets.
[0023] Accordingly, one proposed method for coupling multiple such chiplets has been to provide a silicon “interposer”, which is a silicon chip used as a substrate that is coupled to more than one distinct chiplet. While this proposed solution can provide communication between circuit elements on distinct chiplets, silicon interposers can involve a very large number of communication wires to be coupled between distinct chiplets. These communication wires might involve complex routing and/or dense layout within the silicon interposer. Silicon interposers might also need to be limited with respect to power consumption, which can limit the amount of communication bandwidth they can provide between distinct chiplets. This has led to a desire for other solutions that are not subject to such drawbacks.
[0024] One problem that has arisen in the art is that the silicon interposer being a silicon chip itself has a limited size, defined by the size of semiconductor mask reticle. Maximum manufacturable size of a silicon interposer is still significantly smaller than a conventional organic substrate. This size limitation limits the number of chiplets that can be integrated together in a package, and therefore limits the complexity and performance of the system in package.
[0025] Another proposed solution is EMDIB, an embedded interconnected communication link (sometimes called a “bus”) proposed by Intel Corporation. While this proposed solution can provide a different technique for communication between circuit elements on distinct chiplets, it is very complex to manufacture and also proprietary to Intel. This has led to a desire for other solutions that are not subject to such drawbacks.
[0026] Each of these issues, as well as other possible considerations, might relate to aspects of coupling distinct chips and distinct chiplets that is not subject to the drawbacks described herein, not subject to other drawbacks not otherwise described herein, and related matters.
BRIEF DESCRIPTION OF THE FIGURES
[0027] In the figures, like references generally indicate similar elements, although this is not strictly required.
[0028] FIG. 1 shows a conceptual drawing of a system including an interface between a first and a second chiplet using a package substrate.
[0029] FIG. 2 (collectively including FIGS. 2A-2E ) shows a conceptual drawing of a system including an interface between a computing device and a memory device using circuit logic and a package substrate. The circuit logic can include (FIG. 2A ) a separate chiplet to interface with the physical interconnect, (FIG. 2B ) a combination logic die and physical interconnect interface, or other alternative embodiments as shown in FIGS. 2C-2E .
[0030] FIG. 3 (collectively including FIGS. 3A-3F ) shows a conceptual drawing of a system including multiple computing devices coupled to each other and to one or more of: (FIG. 3A ) a relatively larger number of staggered memory devices using a set of physical interconnects with longer reach; (FIG. 3B ) an expandable set of additional memory devices and/or other circuit elements; (FIG. 3C ) a set of hybrid interfaces between one or more of the computing devices and an external pool of other devices; (FIG. 3D ) a relatively large number of staggered photonic (optical) devices using a set of physical interconnects with longer reach; (FIG. 3E ) a generic set of chiplets disposed in a staggered relationship to an IC chip; or (FIG. 3F ) a large number of photonic devices disposed in a fanout topology with staggered length interconnects.
[0031] After reading this Application, those skilled in the art would recognize that the figures are not necessarily drawn to scale for construction, nor do they necessarily specify any particular location or order of construction.
DETAILED DESCRIPTION
General Discussion
[0032] Among other disclosures, this Application describes a system, and techniques for use, capable of a physical layer interconnect between distinct chips and distinct chiplets that can provide relatively high bandwidth communication with relatively low power requirements.
[0033] In one embodiment, the described physical layer interconnect can be disposed to interface with known physical interconnects and with interfaces already used by known chips and chiplets. Alternatively, the described physical layer interconnect can be disposed in a system including an interface between a first and a second chiplet using a separate chiplet to interface with the physical interconnect or using a logic die (sometimes referred to herein as a “chiplet”) with an embedded physical interconnect interface; in either case, a computing device can be disposed to interface with a memory device using the described physical layer interconnect, whether or not the two devices were originally designed to use the described physical layer interconnect.
[0034] In one embodiment, the described physical layer interconnect can be disposed to couple to multiple computing devices to each other, and to couple each of the computing devices to a set of external devices. Thus, each of the multiple computing devices can be coupled to a substantially larger number of memory devices; to an expandable set of additional circuit elements, such as possibly memory devices or slots for coupling external devices; or to one or more hybrid interfaces between one or more of the computing devices and an external pool of other devices.
[0035] In one embodiment, the described physical layer interconnect can be disposed to couple a set of possibly different computing devices and a set of possibly different memory devices in a rack configuration, such as coupling one or more central processing units (CPUs) or otherwise general processing devices or one or more graphics processing units (GPUs) or otherwise specialized processing devices. For example, the specialized processing devices can include one or more tensor processing units (TPUs), video processing units (VPUs), or other devices disposed for specialized processing techniques. The set of possibly different computing devices can be disposed to be coupled to generalized memory devices or to memory devices specialized for operation with one or more specialized processing devices.
[0036] In one embodiment, the computing devices described herein can include an application-specific integrated circuit (ASIC), a processor, a system-on-a-chip, a floating-point gate array (FPGA), another type of computing device that can interface with one or more memory devices, or a combination or conjunction of multiple ones or multiple types of such devices.
[0037] In one embodiment, the memory devices described herein can include a high-bandwidth memory (HBM), a dynamic RAM (DRAM), static RAM (SRAM), a memory cache, a multi-level memory such as including one or more levels of cache and a memory device, a database, another type of memory device that can interface with one or more devices, or a combination or conjunction of multiple ones or multiple types of such devices.
Terms and Phrases
[0038] The following terms and phrases are exemplary only, and not limiting.
[0039] The phrases “this application”, “this description”, and variants thereof, generally refer to any material shown or suggested by any portions of this Application, individually or collectively, and including all inferences that might be drawn by anyone skilled in the art after reviewing this Application, even if that material would not have been apparent without reviewing this Application at the time it was filed.
[0040] The phrases “computing device”, and variants thereof, generally refer to any device (or portion thereof) that might be disposed to issue read and/or write commands to a “memory device”, such as described herein, or multiple ones or multiple types of such memory devices, whether in parallel or series, whether to one or more separate or banks thereof, whether to a distributed or singular such device, whether to a logically local or remote such device, or otherwise as described herein. For example, the computing device can include an application-specific integrated circuit (ASIC), a processor, a system-on-a-chip, a floating-point gate array (FPGA), another type of computing device that can interface with one or more memory devices, or a combination or conjunction of multiple ones or multiple types of such devices.
[0041] The phrases “memory device”, and variants thereof, generally refer to any device (or portion thereof) that might be disposed to receive read and/or write commands from a “computing device”, such as described herein, or multiple ones or multiple types of such computing devices, whether in parallel or series, whether to one or more separate or banks thereof, whether to a distributed or singular such device, whether from a logically local or remote such device, or otherwise as described herein. For example, the memory device can include a dynamic RAM (DRAM), static RAM (SRAM), a memory cache, a multi-level memory such as including one or more levels of cache and a memory device, a database, another type of memory device that can interface with one or more devices, or a combination or conjunction of multiple ones or multiple types of such devices.
[0042] The phrases “communication link”, “communication bus” and variants thereof, generally refer to any device (or portion thereof) that might be disposed to send information from a first device to a second device, whether or not that information is retained at the first device, whether or not that information is acknowledged or assured to be received by the second device, whether or not that information undergoes substantial delay or is transmitted by intermediate devices, or otherwise as described herein. For example, a communication link can include an electrical, optical, or electro-optical coupling between the first and second devices, a circuit-switched or packet-switched network including the first and second devices, a redundant modular or otherwise reliable distributed communication system, or otherwise as described herein.
[0043] After reviewing this Application, those skilled in the art would recognize that these terms and phrases should be interpreted in light of their context in the specification.
FIGURES AND TEXT
[0044] FIG. 1 shows a conceptual drawing of a system including an interface between a first and a second chiplet using a package substrate.
[0045] In one embodiment, a physical interconnect 100 can be disposed between a first interface 110 disposed on a first chiplet 111, through a package substrate 120 or other support structure, and a second interface 130 disposed on a second chiplet 131.
[0046] As described in the Incorporated Disclosures, the physical interconnect 100 can be disposed to communicate using an organic substrate such as a printed circuit board (PCB) between first circuit elements 112 on the first chiplet 111, using first physical interconnect circuit elements 113, and second circuit elements 132 on the second chiplet 131, using a second set of physical interconnect circuit elements 133. Whenever the first circuit elements 112 communicate with the second circuit elements 132, communication can occur using the physical interconnect 100, thus between the first circuit elements 112, the first physical interconnect circuit elements 113, the actual physical interconnect 100, the second physical interconnect circuit elements 133, and the second circuit elements 132.
[0047] Accordingly, the first circuit elements 112 and the second circuit elements 132 need not know they are not located on the same chiplet. Communication using the physical interconnect 100 might be somewhat less closely tied than direct connection on the same chiplet. However, otherwise communication between the first circuit elements 112 and the second circuit elements 132, so long as they use a protocol specified for using the physical interconnect 100, should have no substantial difference from communication on the same chiplet.
[0048] This can have the effect that the first circuit elements 112 and the second circuit elements 132 can collectively operate substantially as if they were disposed on the same chiplet, without substantial difference except for the possibly of communication that is somewhat less closely tied. Thus, communication might have slightly less bandwidth or slightly greater latency, but otherwise communication should be substantially identical, so long as the first circuit elements 112 and the second circuit elements 132 use a protocol specified for using the physical interconnect 100.
[0049] In one embodiment, communication using the physical interconnect 100 can include a communication bandwidth of about 10 gigabits/second (Gbps) per trace, with relatively low power involved for using the physical interconnect 100. This can have the effect that communication between the multiple chiplets need not involve a silicon interposer that is either (A) as large as both chiplets collectively, or (B) specially designed for communication between the multiple chiplets. Moreover, a system using the multiple chiplets can have relatively complete test coverage and need not be substantially limited by cooling or routing requirements.
[0050] FIG. 2 (collectively including FIGS. 2A-2E ) shows a conceptual drawing of a system including an interface between a computing device and a memory device using an organic package substrate such as a printed circuit board (PCB). The interface can include (FIG. 2A ) a logic die having a physical interface coupled to the memory device and a separate “gearbox” chiplet disposed to couple that physical interface with the physical interconnect or (FIG. 2B ) a logic die and physical interconnect interface. Further embodiments are shown in FIGS. 2C, 2D and 2E .
[0051] The description with respect to this figure is to be regarded as supplemented with the Incorporated Disclosures, including at least, but not limited to, one or more of the following:
-
- [0052] U.S. Provisional Appl. 63/184,842, filed May 6, 2021, in the name of inventors Syrus Ziai and Ramin Farjadrad, titled “Implementing complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over MCM package substrates”.
- [0053] U.S. Provisional Appl. 63/295,524, filed Dec. 31, 2021, in the name of first inventor Ramin Farjadrad, titled “Innovative low-cost packaging solutions for system in package and the HBM crossover PHY architecture”.
Separate Chiplet to Interface with Physical Interconnect
[0054] FIG. 2A shows a conceptual drawing of a system including a logic die having a physical interface coupled to the memory device and a separate “gearbox” chiplet disposed to couple that physical interface with the physical interconnect.
[0055] In one embodiment, a computing device disposed on a first chiplet 210 can include first computing elements disposed to perform the functions of the computing device. The circuit elements disposed on the first chiplet 210 can include first physical interconnect circuit elements 211 (such as physical interconnect circuit elements) coupled to a physical interconnect 200. The physical interconnect 200 can be disposed to couple chiplets using an organic package substrate 201, such as a printed circuit board (PCB).
[0056] In one embodiment, a memory device 220, such as a high-bandwidth memory (HBM) stack including one or more memory chiplets 221, can include an interface logic die 222 disposed with the HBM stack and including an HBM interface circuit 222 disposed to couple the HBM stack to the computing device (as described, disposed on a first chiplet 210).
[0057] The HBM interface circuit 222 can be coupled to a “gearbox chipset” 223 disposed to couple to the HBM interface circuit 222 and to translate the interface implemented by the HBM interface circuit 222 to the protocol specified for using the physical interconnect 200.
[0058] The gearbox chipset 223 can include second physical interconnect circuit elements 224, disposed to implement the protocol specified for using the physical interconnect 200. The first physical interconnect circuit elements 211 and the second physical interconnect circuit elements 224 can be coupled using the physical interconnect 200 and can collectively implement a physical interconnect protocol.
[0059] Accordingly, the memory device 220 can be disposed to interface with the computing device (as described, disposed on a first chiplet 210) using the physical interconnect 200. Therefore, the memory device 220 can connect with the computing device (as described, disposed on a first chiplet 210) over a conventional organic substrate, as opposed to advanced-packaging substrates such as silicon interposer that have many negatives, such as limited size, limited physical interface reach, and very fine trace and pad pitch. For example, the largest silicon today is approximately 2000 mm2 in size, its physical interface reach is less than 4 mm, and its pad and trace pitch is less than 50 um, while an organic substrate can be 10,000 mm2 in size, its physical interface reach to be greater than 20 mm or more, and its pad and trace pitch is greater than 100 um. Thus, the memory device 220 can couple to the computing device (as described, disposed on a first chiplet 210) using the physical interconnect 200 over the organic substrate, without requiring a silicon interposer.
Combination Logic Die and Physical Interconnect Interface
[0060] FIG. 2B shows a conceptual drawing of a system including a combination logic die and physical interconnect interface.
[0061] In one embodiment, a computing device similarly disposed on a first chiplet 210 can include first computing elements disposed to perform the functions of the computing device. The circuit elements disposed on the first chiplet 210 can similarly include first physical interconnect circuit elements 211 coupled to a physical interconnect 200.
[0062] In one embodiment, a memory device 220, such as a high-bandwidth memory (HBM) stack including one or more memory chiplets 221 can include a logic die 222 disposed with the HBM stack and including physical interconnect circuit elements 224 disposed to couple the memory device 220 to the computing device. The physical interconnect circuit elements 224 can be disposed to be coupled to corresponding physical interconnect circuit elements 211 disposed at the computing device, using a physical interconnect 200 coupling chiplets using an organic package substrate 201, such as a printed circuit board (PCB).
[0063] Accordingly, the computing device can be disposed to communicate with the memory device 220 using the first physical interconnect circuit elements 211, the physical interconnect 200, and the second physical interconnect circuit elements 224. Thus, the memory device 220 can couple to the computing device (as described, disposed on a first chiplet 210) using the physical interconnect 200 over the organic substrate, without requiring a silicon interposer.
[0064] In one embodiment, the logic die 222 can include a network interface and (optionally) a computing device.
[0065] For example, the logic die 222 can include an additional computing device and a network interface device disposed thereon. The additional computing device (disposed on the logic die 222) can be disposed to interface with the memory device 220 by receiving and responding to computing commands/controls from the computing device (as described, disposed on a first chiplet 210), using the memory device 220 as its memory device. For one example, the additional computing device (disposed on the logic die 222) can receive database commands/controls from the computing device (as described, disposed on a first chiplet 210), translate those database commands/controls into memory device read/write commands, issue those memory device read/write commands to the memory device 220, translate responses from the memory device 220 into memory device read/write responses, and respond to the computing device (as described, disposed on a first chiplet 210) with those memory device read/write responses. In such cases, the logic die 222 can provide a database interface to the memory device 220 even when the memory device 220 is not so disposed to perform those functions by itself.
[0066] The logic die 222 can also include a network interface disposed to route computing and/or memory commands/responses, such as for example read/write commands, between the memory device 220 and other devices. For example, as described herein, the logic die 222 can be disposed to route read/write commands between multiple memory devices 220, to allow those memory devices 220 to be coupled to one or more computing devices (such as described, disposed on a first chiplet 210) without being directly connected thereto. In such cases, one or more computing devices (as described, disposed on a first chiplet 210) can be coupled to multiple such memory devices 220, with one or more such logic dice 222 disposed to route read/write commands (and associated read/write data) between those computing devices (as described, disposed on a first chiplet 210) and the memory devices 220 maintaining the target memory associated with those read/write commands.
[0067] In one embodiment, the D2D physical interconnects 100 coupling the computing devices and the memory devices 220 can be disposed to route memory commands/requests to selected memory devices 220 as indicated by the computing devices (as described, disposed on a first chiplet 210). Thus, one or more of the computing devices (as described, disposed on a first chiplet 210) can issue a read/write command to one or more of the memory devices 220, even if the memory device 220 which is a target of the read/write command is not directly coupled to the issuing computing device (as described, disposed on a first chiplet 210). This can have the effect that the computing devices (as described, disposed on a first chiplet 210) can access selected memory devices 220 even when those selected memory devices 220 are not directly coupled to those computing devices (as described, disposed on a first chiplet 210).
Multi-Chip Module (MCM) with Photonic Chiplet Coupled to ASIC
[0068] FIG. 2C shows a conceptual drawing of a multi-chip module (MCM) 230 including a package substrate 232 that mounts a first semiconductor device 234 that communicates with a second semiconductor device 236 via a long-reach interconnect that has a relatively large cross section 238. The large cross section helps reduce the resistance of the interconnect, and thus allow for its long reach. For one embodiment, the first semiconductor device 234 takes the form of a single integrated circuit (IC) die, or chiplet, and includes photonic circuitry 240 coupled to a first interface adapter circuit 242 such as a Universal Chiplet Interconnect Express (UCIe) physical interconnect interface. While not shown, the photonic circuitry 240 includes an optical interface for coupling to one or more optical fibers. For one embodiment, the first semiconductor device 234 is packaged with a relatively low-density external interface of mechanical bumps, at 244, that allows for the use of high-speed and relatively long-reach links as the interconnects 238 for coupling to the UCIe interface 242. For one specific embodiment, a bump-to-bump pitch of the connection interface 244 is on the order of 130 micrometers. As more fully explained below, the ability to employ the long-reach links 238 allows for multiple semiconductor devices, such as photonic chiplets, to be staggered in a high-density topology on the MCM 230 with respect to the second semiconductor device 236.
[0069] With continued reference to FIG. 2C , in some embodiments, the photonic circuitry 240 incorporates an electronic interface circuit (EIC) that includes advanced logic for performing optical-to-electrical signal conversions and vice-versa. In such embodiments, the EIC circuitry couples to the first interface adapter circuit 242, which carries out interface conversions between the two circuits such that the first semiconductor device 234 is able to communicate with the second semiconductor device 236.
[0070] Further referring to FIG. 2C , for one embodiment, the second semiconductor device 236 includes application specific integrated circuit (ASIC) core logic 248 coupled to a second interface adapter circuit 250 that is compatible with the first interface adapter circuit 242 of the first semiconductor device 234. The high-speed and relatively long-reach links 238 provide high-bandwidth connectivity per bump of the packaged semiconductor devices 234 and 236. As a result, the package substrate 232 for mounting the semiconductor devices 234 and 236 and for routing the links 238 may take the form of a relatively inexpensive package substrate, such as an organic or non-silicon substrate. This, in-turn, allows the MCM 230 to provide chip-to-chip communications without the need for an expensive silicon-based substrate, such as a silicon interposer.
Multi-Chip Module (MCM) with Photonic Chiplet Assembly Coupled to ASIC
[0071] FIG. 2D shows a conceptual drawing of a multi-chip module (MCM) 250 that is similar to the MCM 230, employing a similar second semiconductor device 236 and package substrate 232. The MCM 250 includes a first semiconductor assembly 252 that disaggregates the Universal Chiplet Interconnect Express (UCIe) physical interconnect interface of FIG. 2C as a separate gearbox adapter chiplet 254 that is separate from a photonic chiplet 256 in a 2.5D physical layout. For one embodiment, the photonic chiplet 256 includes EIC circuitry and a high-bandwidth interconnect (HBI) interface 257, where the HBI interface is a wide interface operating at a relatively low-baud rate over many wires that are spaced at a relatively high density. The gearbox adapter chiplet 254 employs a primary interface that couples to the HBI interface, and a secondary interface that, for one embodiment, takes the form of the UCIe interface. Conversion circuitry within the gearbox adapter chiplet 254 performs interface conversions between the interfaces.
[0072] Further referring to FIG. 2D , for one embodiment, the photonic chiplet 256 and the interface adapter chiplet 254 are both mounted in a horizontal relationship with each other on a secondary substrate 256. The secondary substrate 256 includes an array of contacts or bumps 258 that connect the secondary substrate 256 to the main package substrate 232. For some embodiments, the secondary substrate 256 may be formed as a silicon interposer, or as a non-silicon substrate formed, for example, as an epoxy-based mold material in a high-density fan-out (HDFO) process or a wafer-level fan-out (WLFO) process. The secondary substrate 256 provides for high-pitch and high-density signaling paths or traces, at 258, formed, for example, in an oxide layer of the mold material between the first chip interface 257 and the interface adapter chiplet 254. For some embodiments, through-vias may be formed through the mold material, at 262, to provide low-density and high-bandwidth connections between the interface adapter chiplet 254 and the main package substrate 232.
Multi-Chip Module (MCM) with a Disaggregated EIC Circuit
[0073] FIG. 2E shows a conceptual drawing of an MCM 270 that is similar to the MCM 250, employing a similar second semiconductor device 236 and package substrate 232. The MCM 270 includes a first semiconductor assembly 272 that not only disaggregates the adapter interface as a separate adapter chiplet 274, but also includes EIC circuitry within the adapter chiplet 274 that is separate from a photonic chiplet 276 in a 2.5D physical layout. As noted above, the EIC circuitry generally includes advanced logic that is more suitable for an advanced logic manufacturing process, similar to the gearbox logic. The photonic logic, on the other hand, is more suitable to a less-advanced manufacturing process. By disaggregating the different forms of logic, the photonic chip may be less costly since it may avoid the more advanced manufacturing steps associated with the advanced logic process. Additionally, in many cases, implementing the very high-speed EIC circuits on the photonic chiplet 276 is either impractical or if practical, leads to very high-power implementations. Adding the EIC circuitry to the gearbox logic with the advanced logic process not only minimally impacts the cost of the gearbox chiplet, but delivers a very lower-power combined solution. As a result, manufacturing costs associated with the first semiconductor assembly may be reduced. In some proposed prior art, the EIC is implemented in the second semiconductor device 236, which also include advanced logic process, however, the very high-speed signals between the EIC and PIC can be attenuated if the coupling traces are long. In the latter configuration, the photonic chip 279 either needs to be placed close to the ASIC chip 236, which limits the routability and placement of the chiplets in the MCM, or the PIC chiplet needs to have high-speed equalization circuits that lead to high power and complexity.
[0074] FIG. 3 (collectively including FIGS. 3A-3F ) shows a conceptual drawing of a system including one or more computing devices coupled to one or more of: (FIG. 3A ) a relatively larger number of memory devices using a set of physical interconnects; (FIG. 3B ) an expandable set of additional memory devices and/or other circuit elements; (FIG. 3C ) a set of hybrid interfaces between one or more of the computing devices and an external pool of other devices; (FIG. 3D ) a relatively larger number of photonic devices disposed in a staggered topology using a set of physical interconnects; (FIG. 3E ) a larger number of generic chiplets disposed in a staggered topology; or (FIG. 3F ) a relatively larger number of photonic devices disposed in a fanout topology using a set of physical interconnects.
Coupling to Relatively Larger Set of Physical Interconnects
[0075] FIG. 3A shows a conceptual drawing of a system including multiple computing devices coupled to each other and to a relatively larger of memory devices using a set of physical interconnects.
[0076] In one embodiment, a package 300 includes one or more of the following:
-
- [0077] A first ASIC 301 and a second ASIC 302. The first ASIC 301 and the second ASIC 302 can be coupled using an example physical interconnect 100, or an equivalent thereof. The example physical interconnect 100 can be disposed using a package substrate 300a.
- [0078] A first set of memory devices 301a, such as a first set of high-bandwidth memory devices (HBM), coupled to the first ASIC 301, and a second set of memory devices 302a, also such as HBM devices, coupled to the second ASIC 302. (It is also possible for at least one or more of the HBM devices to be coupled to both the first ASIC 301 and to the second ASIC 302, such as possibly using multiple physical interconnects 100.)
- [0079] The first ASIC 301 can be coupled to each of the first set of memory devices 301a using an example physical interconnect 200, or an equivalent thereof and the physical interfaces 211 and 224 respectively. Similarly, the second ASIC 302 can be coupled to each of the second set of memory devices 302a using an example physical interconnect 200, or an equivalent thereof and the physical interfaces 211 and 224 respectively. Each physical interconnect 200 can be disposed using the package substrate 300a.
[0080] In one embodiment, the package 300 can be disposed so that the first ASIC 301 and the second ASIC 302 each are coupled to an external connection. For example, the external connection can include a relatively long-range coupling to outside of the substrate. Alternatively, the external connection can include a relatively long-range coupling to a device disposed to couple to outside the substrate.
[0081] In one embodiment, the package 300 can be disposed so that the first ASIC 301 and the second ASIC 302 are relatively close to one another within the package 300, using the package substrate 300a.
[0082] In one embodiment, the package 300 can also be disposed so that the first ASIC 301 is relatively separated from its associated HBMs 301a, and the second ASIC 302 is relatively separated from its associated HBMs 302a. This is possible because the physical interconnect (described with respect to FIGS. 2A-2B ) using an organic substrate can cover a substantially longer distance than a physical interconnect using a silicon interposer.
[0083] For example, an ASIC chiplet might be approximately 33 mm on a side, an HBM chiplet might be approximately 11 mm on a side, and a physical interconnect using a silicon interposer might be 4 mm at most in length. This would allow only about three HBMs to be coupled to the ASIC on a side. With a substantially longer physical interconnect provided using the organic substrate, each HBM can be disposed substantially farther from the ASIC. This can allow a larger number of HBMs to be coupled to the ASIC using the physical interconnect. For example, as shown in the figure, the ASIC can be coupled to twice as many HBMs as it could be when using a silicon interposer.
[0084] In one embodiment, the HBM chiplets can be disposed in a staggered manner. Thus, the HBM chiplets can be disposed in an arrangement other than strictly linear, so that some HBM chiplets are closer and some are farther from the ASIC chiplet. This can have the effect that more HBM chiplets can be disposed on a substrate such as an organic substrate or a printed circuit board (PCB). Because each trace in the D2D physical interconnect can have a lower loss, the traces can be disposed to have a longer reach. The longer reach of the D2D physical interconnect can be used to allow more HBM chiplets to be coupled to the ASIC chiplet.
[0085] Moreover, the longer reach of the D2D physical interconnect can be used to coupled larger ASIC chiplets or to couple the ASIC chiplets at a greater distance. This can have the effect that each ASIC chiplet can dissipate more heat without affecting other HBM chiplets that are heat sensitive. This can have the effect that more chiplets can be disposed on a single PCB without providing excessive heat or otherwise requiring extensive cooling means.
Expandable Set of Additional Memory Devices
[0086] FIG. 3B shows a conceptual drawing of a system including multiple computing devices coupled to each other and to an expandable set of additional memory devices and/or other circuit elements.
[0087] In one embodiment, an alternative package 300 can include one or more of the following:
-
- [0088] A first ASIC 301 and a second ASIC 302, similar to those described herein.
- [0089] A first set of memory devices 301a and a second set of memory devices 302a, similar to those described herein.
- [0090] A first set of expansion slots 301b, such as coupled to an elastomeric package, such as the package substrate 300a, or such as to a printed circuit board (PCB) 300b, coupled to the first ASIC 301, and a second set of expansion slots 302b, such as similarly coupled. The expansion slots 301b or 302b can be disposed to allow coupling of additional, new, or replacement circuits to the first ASIC 301 and/or the second ASIC 302. For example, the expansion slots 301b or 302b can be disposed to allow additional HBM devices 301a and/or 302a to be coupled to the ASICs 301 and/or 302. For another example, the expansion slots 301b or 302b can be disposed to allow other types of devices to be coupled to the ASICs 301 and/or 302.
[0091] As described above with respect to FIG. 3A , the package 300 can be disposed so that a bump pitch on the organic substrate is greater than 100 μm. This can provide that the first ASIC 301 can be coupled to its associated expansion slots 301b, and the second ASIC 302 can be coupled to its associated expansion slots 302b. Such associated expansion slots 301b are not generally possible with silicon interposers having micro bumps sized less than 100 um.
[0092] In one embodiment, the expansion slots 301b or 302b can each be coupled to an optical, electrical, or other external connection. For example, one or more of the expansion slots 301b or 302b can be coupled to an optical, electrical, or another type of connection to an external chiplet. Similarly, one or more of the expansion slots 301b or 302b can be coupled to an optical, electrical, or another type of connection to a device other than a chiplet, such as a device external to the substrate.
Hybrid Interfaces with External Pool of Other Devices
[0093] FIG. 3C shows a conceptual drawing of a system including multiple computing devices coupled to each other and to a set of hybrid interfaces between one or more of the computing devices and an external pool of other devices.
[0094] In one embodiment, an alternative package 300 can include one or more of the following:
-
- [0095] A first ASIC 301 and a second ASIC 302, similar to those described herein.
- [0096] A first set of memory devices 301a and a second set of memory devices 301a, similar to those described herein.
- [0097] A first set of external coupling devices 301b, coupled to the first ASIC 301, such as each disposed to be coupled to a communication link such as a terabits/second (Tbps) fiber link, couplable to an external memory or any other external device disposed to exchange information using such a link, and a second set of external coupling devices 302b, coupled to the second ASIC 302, such as similarly coupled. As shown in the figure, the external coupling devices 301b or 302b are disposed close to the edge of the MCM package, so the coupling of fiber and/or other external links are mechanically easier.
[0098] As described above with respect to FIG. 3A , the package 300 can be disposed so that the first ASIC 301 is relatively separated from its associated external coupling devices 301b, and the second ASIC 302 is relatively separated from its associated external coupling devices 302b. Similar to FIG. 3A , this is possible because the physical interconnect (described with respect to FIGS. 2A-2B ) using an organic substrate can cover a substantially longer distance than a physical interconnect using a silicon interposer.
Coupling to Relatively Larger Set of Photonic Devices in a Staggered Topology
[0099] FIG. 3D shows a conceptual drawing of a multi-chip module (MCM) 310 including a computing device 320 coupled to a set of photonic devices 322 that are disposed in a staggered relationship to the computing device 320.
[0100] Further referring to FIG. 3D , for one embodiment, the computing device 320 takes the form of an ASIC that is mounted to a package substrate 324. The ASIC 320 includes “north” and “south” edge areas 326 and 328 that are formed with respective sets of interface circuits 330. For one embodiment, each interface circuit 330 takes the form of a UCIe interface circuit and supports communications between the ASIC and a given photonic device 322 along an associated long-reach link 332.
[0101] With continued reference to FIG. 3D , for one embodiment, each photonic device or chiplet 322 may take the form of any of the semiconductor device embodiments described with respect to FIGS. 2C-2E and includes an interface circuit 334 that is compatible with the interface circuit 330 of the ASIC. In an effort to increase an overall bandwidth of the MCM 310 while still minimizing the size of the MCM footprint, the photonic chiplets 322 are positioned such that adjacent chiplets 322 are staggered longitudinally from the ASIC 320. For one embodiment, a lateral center-to-center spacing of a first chiplet relative to an adjacent second chiplet is less than half a total width of the first chiplet and the second chiplet. In some embodiments, a combination of different chiplets in addition to or other than photonic chiplets may be included on the MCM 320. Such chiplets may include SerDes chiplets, gearbox chiplets, memory chiplets, or the like.
Generic Coupling to Relatively Larger Set of Chiplets in a Staggered Topology
[0102] FIG. 3E shows a conceptual drawing of an integrated circuit (IC) chip 340 coupled to a set of chiplets 342 that are disposed in a staggered relationship to the IC chip 340.
[0103] Further referring to FIG. 3E , for one embodiment, the IC chip 340 includes an input/output (I/O) edge area 344 that includes a set of interface circuits 346. For one embodiment, each interface circuit 346 takes the form of a UCIe interface circuit and supports communications between the IC chip 340 and a given chiplet 342 along an associated long-reach link 348. The IC chip 340, the chiplets 342 and the links 348 are all disposed on a package substrate (not shown) to form a multi-chip module (MCM).
[0104] With continued reference to FIG. 3E , for one embodiment, each chiplet 342 may take the form of any of the semiconductor device embodiments described with respect to FIGS. 2C-2E and includes an interface circuit 350 that is compatible with the interface circuit 346 of the IC chip 340. In an effort to increase an overall bandwidth of the MCM while still minimizing the size of the MCM footprint, the chiplets 342 are positioned such that adjacent chiplets, such as at 352 and 354, are staggered longitudinally from the IC chip 340. Thus, the chiplet 342, at 352, is disposed a first longitudinal distance 356 that is different than a second longitudinal distance, at 358, associated with the chiplet 342 at 354. Additionally, the chiplets are disposed laterally with respect to one another such that the first chiplet, at 352, and the second chiplet, at 354, are disposed in an at least partially laterally overlapping configuration with respect to each other. For one embodiment where the chiplets 342 are identical, the lateral overlapping results in a lateral center-to-center spacing of the chiplets that is less than half a total width of the first chiplet WCHIP1 and the second chiplet WCHIP2.
Coupling to Relatively Larger Set of Photonic Devices in a Fanout Topology
[0105] FIG. 3F shows a conceptual drawing of a multi-chip module (MCM) 360 that is similar to the MCM 310 of FIG. 3D , including a computing device 320 coupled to a set of photonic devices 322 via a set of long-reach links 362 along a package substrate 324.
[0106] Further referring to FIG. 3F , for one embodiment, the photonic devices 322 are positioned in an “east” to “west” linear arrangement, with each photonic device being coupled to the ASIC 320 via a corresponding link 362. Due to the long-reach nature of the links 362, the photonic devices 322 may be positioned, if desired, further from the ASIC 320 than in the previously-described embodiments. Fanning out the photonic devices in this manner may allow for better coupling of fiber interconnects to the photonic devices 322. Additionally, by positioning the photonic devices 322 further from the ASIC 320, mechanical interference from vertically-oriented fiber interconnects may be avoided when installing a heat sink on the ASIC 320.
ALTERNATIVE EMBODIMENTS
[0107] While this Application primarily describes systems and techniques that primarily relate to physical layer interconnects between chips and/or chiplets, there is no requirement for any such limitation. After reading this Application, those skilled in the art will recognize that the techniques described herein are applicable to a wide variety of devices disposed to interconnect electronic circuitry or portions thereof. For example, the techniques described herein are applicable to a wide variety of different types of devices disposed to interconnect electronic circuitry or portions thereof, and to provide high-bandwidth and/or relatively low-power interconnects therebetween; or otherwise as described herein.
[0108] Moreover, after reading this Application, those skilled in the art will recognize that the techniques described herein are applicable to a wide variety of different types of devices which can computing devices, memory devices, specialized hardware/software devices such as tensor processing devices (TPUs), video processing devices (VPUs), and a wide variety of different types of electronic circuitry coupling.
[0109] This Application describes a preferred embodiment with preferred process steps and, where applicable, preferred data structures. After reading this Application, those skilled in the art would recognize that, where any calculation or computation is appropriate, embodiments of the description can be implemented using general purpose computing devices or switching processors, special purpose computing devices or switching processors, other circuits adapted to particular process steps and data structures described herein, or combinations or conjunctions thereof, and that implementation of the process steps and data structures described herein would not require undue experimentation or further invention.
[0110] The claims are incorporated into the specification as if fully set forth herein.
Claims
The invention claimed is:
1. A chiplet-based multi-chip module (MCM) to mount to a main substrate, comprising:
a package substrate without an interposer, the package substrate separate from the main substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first interface beachfront of a first longitudinal length, the first interface beachfront formed along a first edge of the first IC chiplet and comprising a first set of die-to-die (D2D) interface circuits; and
a first set of peripheral chiplets coupled to the package substrate in a first collinear fanout arrangement with respect to the first interface beachfront of the first IC chiplet, the first collinear fanout arrangement comprising a second longitudinal length that is longer than the first longitudinal length, the first set of peripheral chiplets coupled to the first set of D2D interfaces in a one-to-one relationship via a first set of long-reach links.
2. The chiplet-based MCM of claim 1, wherein:
the first collinear fanout arrangement of the first set of peripheral chiplets defines a parallel spaced-apart relationship of the first set of peripheral chiplets with respect to the first set of D2D interfaces.
3. The chiplet-based MCM of claim 1, wherein:
the first IC chiplet comprises a processing IC chiplet.
4. The chiplet-based MCM of claim 1, wherein:
the first set of peripheral chiplets comprises multiple photonic IC chiplets.
5. The chiplet-based MCM of claim 1, wherein:
the first set of peripheral chiplets comprises multiple memory chiplets.
6. The chiplet-based MCM of claim 5, wherein:
each of the multiple memory chiplets comprises
a base die; and
a memory stack disposed on the base die.
7. The chiplet-based MCM of claim 6, wherein:
the memory stack comprises a high-bandwidth memory (HBM) stack of dynamic random access memory (DRAM).
8. The chiplet-based MCM of claim 1, wherein:
the first set of long-reach links are free to be different lengths.
9. The chiplet-based MCM of claim 8, wherein:
the first set of long-reach links are of staggered lengths.
10. The chiplet-based MCM of claim 2, wherein:
the first set of D2D interfaces comprises a first set of Universal Chiplet Interconnect Express (UCIe) D2D interfaces.
11. The chiplet-based MCM of claim 1, wherein:
the first integrated circuit (IC) chiplet comprises a second interface beachfront of a third longitudinal length, the second interface beachfront formed along a second edge of the first IC chiplet and comprising a second set of die-to-die (D2D) interface circuits; and
wherein the chiplet-based MCM further comprises a second set of peripheral chiplets coupled to the package substrate in a second collinear fanout arrangement with respect to the second interface beachfront of the first IC chiplet, the second collinear fanout arrangement comprising a fourth longitudinal length that is longer than the third longitudinal length, the second set of peripheral chiplets coupled to the second set of D2D interfaces in a one-to-one relationship via a second set of long-reach links.
12. A chiplet-based multi-chip module (MCM) to mount to a main substrate, comprising:
a package substrate without an interposer, the package substrate separate from the main substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first set of die-to-die (D2D) interface circuits disposed proximate a first edge of the first IC chiplet and a second set of D2D interface circuits disposed proximate a second edge of the first IC chiplet;
a first set of peripheral chiplets coupled to the first set of D2D interface circuits via a first set of links, the first set of links routed along a first set of traces of the package substrate;
a second set of peripheral chiplets coupled to the second set of D2D interface circuits via a second set of links, the second set of links routed along a second set of traces of the package substrate; and
wherein adjacent peripheral chiplets of the first set of peripheral chiplets are positioned in a first collinear fanout arrangement with respect to the first IC chiplet, and wherein adjacent peripheral chiplets of the second set of peripheral chiplets are positioned in a second collinear fanout arrangement with respect to the first IC chiplet.
13. The chiplet-based MCM of claim 12, wherein:
the first collinear fanout arrangement of the first set of peripheral chiplets defines a first parallel spaced-apart relationship of the first set of peripheral chiplets with respect to the first set of D2D interfaces; and
the second collinear fanout arrangement of the second set of peripheral chiplets defines a second parallel spaced-apart relationship of the second set of peripheral chiplets with respect to the second set of D2D interfaces.
14. The chiplet-based MCM of claim 12, wherein:
the first IC chiplet comprises a processing IC chiplet.
15. The chiplet-based MCM of claim 12, wherein:
the first set of peripheral chiplets comprises multiple photonic IC chiplets.
16. The chiplet-based MCM of claim 12, wherein:
the first set of peripheral chiplets comprises multiple memory chiplets.
17. The chiplet-based MCM of claim 16, wherein:
each of the multiple memory chiplets comprises
a base die; and
a memory stack disposed on the base die.
18. The chiplet-based MCM of claim 17, wherein:
the memory stack comprises a high-bandwidth memory (HBM) stack of dynamic random access memory (DRAM).
19. The chiplet-based MCM of claim 12, wherein:
the first set of links and the second set of links are free to be different lengths.
20. The chiplet-based MCM of claim 19, wherein:
the first set of links and the second set of links are of staggered lengths.
21. The chiplet-based MCM of claim 12, wherein:
the first set of D2D interfaces and the second set of D2D interfaces comprise respective first and second sets of Universal Chiplet Interconnect Express (UCIe) D2D interfaces.
22. A method of operation in a chiplet-based multi-chip module (MCM), comprising:
interfacing, on a package substrate without an interposer, a first set of D2D interfaces of a first integrated circuit (IC) chiplet to a first set of peripheral chiplets via a first set of long-reach links, the interfacing of the first IC chiplet to the first set of peripheral chiplets comprising positioning adjacent peripheral chiplets of the first set of peripheral chiplets in a first collinear fanout arrangement with respect to the first IC chiplet;
interfacing, on the package substrate, a second set of D2D interfaces of the first IC chiplet to a second set of peripheral chiplets via a second set of long-reach links, wherein the interfacing of the first IC chiplet to the second set of peripheral chiplets comprises positioning adjacent peripheral chiplets of the second set of peripheral chiplets in a second collinear fanout arrangement with respect to the first IC chiplet.
23. The method of claim 22, wherein:
the first collinear fanout arrangement of the first set of peripheral chiplets defines a first parallel spaced-apart relationship of the first set of peripheral chiplets with respect to the first set of D2D interfaces; and
the second collinear fanout arrangement of the second set of peripheral chiplets defines a second parallel spaced-apart relationship of the second set of peripheral chiplets with respect to the second set of D2D interfaces.
Patent Citations (176)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4334305(A) | 1982-06-01 | Girardi | Applicant |
| US5396581(A) | 1995-03-01 | Mashiko | Applicant |
| US5677569(A) | 1997-10-01 | Choi | Applicant |
| US5892287(A) | 1999-04-01 | Hoffman | Applicant |
| US5910010(A) | 1999-06-01 | Nishizawa | Applicant |
| US6031729(A) | 2000-02-01 | Berkely | Applicant |
| US6055235(A) | 2000-04-01 | Blanc | Applicant |
| US6417737(B1) | 2002-07-01 | Moloudi | Applicant |
| US6690742(B2) | 2004-02-01 | Chan | Applicant |
| US6721313(B1) | 2004-04-01 | Van Duyne | Applicant |
| US6932618(B1) | 2005-08-01 | Nelson | Applicant |
| US7027529(B1) | 2006-04-01 | Ohishi | Applicant |
| US7248890(B1) | 2007-07-01 | Raghavan | Applicant |
| US7269212(B1) | 2007-09-01 | Chau | Applicant |
| US7477615(B2) | 2009-01-01 | Oshita | Applicant |
| US7535958(B2) | 2009-05-01 | Best | Applicant |
| US7701957(B1) | 2010-04-01 | Bicknell | Applicant |
| US7907469(B2) | 2011-03-01 | Sohn et al. | Applicant |
| US7978754(B2) | 2011-07-01 | Yeung | Applicant |
| US8004330(B1) | 2011-08-01 | Acimovic | Applicant |
| US8024142(B1) | 2011-09-01 | Gagnon | Applicant |
| US8121541(B2) | 2012-02-01 | Rofougaran | Applicant |
| US8176238(B2) | 2012-05-01 | Yu et al. | Applicant |
| US8483579(B2) | 2013-07-01 | Fukuda | Applicant |
| US8546955(B1) | 2013-10-01 | Wu | Applicant |
| US8704364(B2) | 2014-04-01 | Banijamali et al. | Applicant |
| US8861573(B2) | 2014-10-01 | Chu | Applicant |
| US8948203(B1) | 2015-02-01 | Nolan | Applicant |
| US8982905(B2) | 2015-03-01 | Kamble | Applicant |
| US9088334(B2) | 2015-07-01 | Chakraborty | Applicant |
| US9106229(B1) | 2015-08-01 | Hutton | Applicant |
| US9129935(B1) | 2015-09-01 | Chandrasekar | Applicant |
| US9294313(B2) | 2016-03-01 | Prokop | Applicant |
| US9349707(B1) | 2016-05-01 | Sun | Applicant |
| US9379878(B1) | 2016-06-01 | Lugthart | Applicant |
| US9432298(B1) | 2016-08-01 | Smith | Applicant |
| US9832006(B1) | 2017-11-01 | Bandi | Applicant |
| US9843538(B2) | 2017-12-01 | Woodruff | Applicant |
| US9886275(B1) | 2018-02-01 | Carlson | Applicant |
| US9934842(B2) | 2018-04-01 | Mozak | Applicant |
| US9961812(B2) | 2018-05-01 | Suorsa | Applicant |
| US10171115(B1) | 2019-01-01 | Shirinfar | Applicant |
| US10402363(B2) | 2019-09-01 | Long et al. | Applicant |
| US10410694(B1) | 2019-09-01 | Arbel | Applicant |
| US10439661(B1) | 2019-10-01 | Heydari | Applicant |
| US10642767(B1) | 2020-05-01 | Farjadrad | Applicant |
| US10678738(B2) | 2020-06-01 | Dai | Applicant |
| US10735176(B1) | 2020-08-01 | Heydari | Applicant |
| US10748852(B1) | 2020-08-01 | Sauter | Applicant |
| US10769073(B2) | 2020-09-01 | Desai | Applicant |
| US10803548(B2) | 2020-10-01 | Matam et al. | Applicant |
| US10804204(B2) | 2020-10-01 | Rubin et al. | Applicant |
| US10826536(B1) | 2020-11-01 | Beukema | Applicant |
| US10855498(B1) | 2020-12-01 | Farjadrad | Applicant |
| US10935593(B2) | 2021-03-01 | Goyal | Applicant |
| US11088876(B1) | 2021-08-01 | Farjadrad | Applicant |
| US11100028(B1) | 2021-08-01 | Subramaniam | Applicant |
| US11164817(B2) | 2021-11-01 | Rubin et al. | Applicant |
| US11204863(B2) | 2021-12-01 | Sheffler | Applicant |
| US11789649(B2) | 2023-10-01 | Chatterjee et al. | Applicant |
| US11841815(B1) | 2023-12-01 | Farjadrad | Applicant |
| US11842986(B1) | 2023-12-01 | Ramin | Applicant |
| US11855043(B1) | 2023-12-01 | Farjadrad | Applicant |
| US11855056(B1) | 2023-12-01 | Rad | Applicant |
| US11892242(B2) | 2024-02-01 | Mao | Applicant |
| US11893242(B1) | 2024-02-01 | Farjadrad | Applicant |
| US11983125(B2) | 2024-05-01 | Soni | Applicant |
| US12001355(B1) | 2024-06-01 | Dreier | Applicant |
| US2002/0122479(A1) | 2002-09-01 | Agazzi | Applicant |
| US2002/0136315(A1) | 2002-09-01 | Chan | Applicant |
| US2004/0088444(A1) | 2004-05-01 | Baumer | Applicant |
| US2004/0113239(A1) | 2004-06-01 | Prokofiev | Applicant |
| US2004/0130347(A1) | 2004-07-01 | Moll | Applicant |
| US2004/0156461(A1) | 2004-08-01 | Agazzi | Applicant |
| US2005/0041683(A1) | 2005-02-01 | Kizer | Applicant |
| US2005/0134306(A1) | 2005-06-01 | Stojanovic | Applicant |
| US2005/0157781(A1) | 2005-07-01 | Ho | Applicant |
| US2005/0205983(A1) | 2005-09-01 | Origasa | Applicant |
| US2006/0060376(A1) | 2006-03-01 | Yoon | Applicant |
| US2006/0103011(A1) | 2006-05-01 | Andry | Applicant |
| US2006/0158229(A1) | 2006-07-01 | Hsu | Applicant |
| US2006/0181283(A1) | 2006-08-01 | Wajcer | Applicant |
| US2006/0188043(A1) | 2006-08-01 | Zerbe | Applicant |
| US2006/0250985(A1) | 2006-11-01 | Baumer | Applicant |
| US2006/0251194(A1) | 2006-11-01 | Bublil | Applicant |
| US2007/0281643(A1) | 2007-12-01 | Kawai | Applicant |
| US2008/0063395(A1) | 2008-03-01 | Royle | Applicant |
| US2008/0086282(A1) | 2008-04-01 | Artman | Applicant |
| US2008/0143422(A1) | 2008-06-01 | Lalithambika | Applicant |
| US2008/0186987(A1) | 2008-08-01 | Baumer | Applicant |
| US2008/0222407(A1) | 2008-09-01 | Carpenter | Applicant |
| US2009/0113158(A1) | 2009-04-01 | Schnell | Applicant |
| US2009/0154365(A1) | 2009-06-01 | Diab | Applicant |
| US2009/0174448(A1) | 2009-07-01 | Zabinski | Applicant |
| US2009/0220240(A1) | 2009-09-01 | Abhari | Applicant |
| US2009/0225900(A1) | 2009-09-01 | Yamaguchi | Applicant |
| US2009/0304054(A1) | 2009-12-01 | Tonietto | Applicant |
| US2010/0177841(A1) | 2010-07-01 | Yoon | Applicant |
| US2010/0197231(A1) | 2010-08-01 | Kenington | Applicant |
| US2010/0294547(A1) | 2010-11-01 | Hatanaka | Applicant |
| US2011/0029803(A1) | 2011-02-01 | Redman-White | Applicant |
| US2011/0038286(A1) | 2011-02-01 | Ta | Applicant |
| US2011/0167297(A1) | 2011-07-01 | Su | Applicant |
| US2011/0187430(A1) | 2011-08-01 | Tang | Applicant |
| US2011/0204428(A1) | 2011-08-01 | Erickson | Applicant |
| US2011/0267073(A1) | 2011-11-01 | Chengson | Applicant |
| US2011/0293041(A1) | 2011-12-01 | Luo | Applicant |
| US2012/0082194(A1) | 2012-04-01 | Tam | Applicant |
| US2012/0182776(A1) | 2012-07-01 | Best | Applicant |
| US2012/0192023(A1) | 2012-07-01 | Lee | Applicant |
| US2012/0216084(A1) | 2012-08-01 | Chun | Applicant |
| US2012/0327818(A1) | 2012-12-01 | Takatori | Applicant |
| US2013/0181257(A1) | 2013-07-01 | Ngai | Applicant |
| US2013/0222026(A1) | 2013-08-01 | Havens | Applicant |
| US2013/0249290(A1) | 2013-09-01 | Buonpane | Applicant |
| US2013/0285584(A1) | 2013-10-01 | Kim | Applicant |
| US2014/0016524(A1) | 2014-01-01 | Choi | Applicant |
| US2014/0048947(A1) | 2014-02-01 | Lee | Applicant |
| US2014/0126613(A1) | 2014-05-01 | Zhang | Applicant |
| US2014/0192583(A1) | 2014-07-01 | Rajan | Applicant |
| US2014/0269860(A1) | 2014-09-01 | Brown | Applicant |
| US2014/0269983(A1) | 2014-09-01 | Baeckler | Applicant |
| US2015/0012677(A1) | 2015-01-01 | Nagarajan | Applicant |
| US2015/0046612(A1) | 2015-02-01 | Gupta | Applicant |
| US2015/0172040(A1) | 2015-06-01 | Pelekhaty | Applicant |
| US2015/0180760(A1) | 2015-06-01 | Rickard | Applicant |
| US2015/0206867(A1) | 2015-07-01 | Lim | Applicant |
| US2015/0271074(A1) | 2015-09-01 | Hirth | Applicant |
| US2015/0326348(A1) | 2015-11-01 | Shen | Applicant |
| US2015/0358005(A1) | 2015-12-01 | Chen | Applicant |
| US2016/0056125(A1) | 2016-02-01 | Pan | Applicant |
| US2016/0071818(A1) | 2016-03-01 | Wang | Applicant |
| US2016/0111406(A1) | 2016-04-01 | Mak | Applicant |
| US2016/0217872(A1) | 2016-07-01 | Hossain | Applicant |
| US2016/0294585(A1) | 2016-10-01 | Rahman | Applicant |
| US2017/0255575(A1) | 2017-09-01 | Niu | Applicant |
| US2017/0317859(A1) | 2017-11-01 | Hormati | Applicant |
| US2017/0331651(A1) | 2017-11-01 | Suzuki | Applicant |
| US2018/0010329(A1) | 2018-01-01 | Golding, Jr. | Applicant |
| US2018/0082981(A1) | 2018-03-01 | Gowda | Applicant |
| US2018/0137005(A1) | 2018-05-01 | Wu | Applicant |
| US2018/0175001(A1) | 2018-06-01 | Pyo | Applicant |
| US2018/0190635(A1) | 2018-07-01 | Choi | Applicant |
| US2018/0210830(A1) | 2018-07-01 | Malladi et al. | Applicant |
| US2018/0315735(A1) | 2018-11-01 | Delacruz | Examiner |
| US2019/0044764(A1) | 2019-02-01 | Hollis | Applicant |
| US2019/0058457(A1) | 2019-02-01 | Ran | Applicant |
| US2019/0108111(A1) | 2019-04-01 | Levin | Applicant |
| US2019/0198489(A1) | 2019-06-01 | Kim | Applicant |
| US2019/0319626(A1) | 2019-10-01 | Dabral | Applicant |
| US2020/0051961(A1) | 2020-02-01 | Rickard | Applicant |
| US2020/0105718(A1) | 2020-04-01 | Collins et al. | Applicant |
| US2020/0257619(A1) | 2020-08-01 | Sheffler | Applicant |
| US2020/0373286(A1) | 2020-11-01 | Dennis | Applicant |
| US2021/0056058(A1) | 2021-02-01 | Lee | Applicant |
| US2021/0082875(A1) | 2021-03-01 | Nelson | Applicant |
| US2021/0117102(A1) | 2021-04-01 | Grenier | Applicant |
| US2021/0149763(A1) | 2021-05-01 | Ranganathan | Applicant |
| US2021/0181974(A1) | 2021-06-01 | Ghosh | Applicant |
| US2021/0183842(A1) | 2021-06-01 | Fay | Applicant |
| US2021/0193567(A1) | 2021-06-01 | Cheah et al. | Applicant |
| US2021/0225827(A1) | 2021-07-01 | Lanka | Applicant |
| US2021/0258078(A1) | 2021-08-01 | Meade | Applicant |
| US2021/0311900(A1) | 2021-10-01 | Malladi | Applicant |
| US2021/0365203(A1) | 2021-11-01 | O | Applicant |
| US2022/0051989(A1) | 2022-02-01 | Agarwal | Applicant |
| US2022/0159860(A1) | 2022-05-01 | Winzer | Applicant |
| US2022/0189934(A1) | 2022-06-01 | Kim | Applicant |
| US2022/0223522(A1) | 2022-07-01 | Scearce | Examiner |
| US2022/0254390(A1) | 2022-08-01 | Gans | Applicant |
| US2023/0039033(A1) | 2023-02-01 | Zarkovsky | Applicant |
| US2023/0068802(A1) | 2023-03-01 | Wang | Applicant |
| US2023/0090061(A1) | 2023-03-01 | Zarkovsky | Applicant |
| US2023/0092541(A1) | 2023-03-01 | Dugast | Applicant |
| US2023/0161599(A1) | 2023-05-01 | Erickson | Applicant |
| US2023/0181599(A1) | 2023-06-01 | Du et al. | Applicant |
Non-Patent Literature (14)
- U.S. Appl. No. 16/812,234; Mohsen F. Rad, filed Mar. 6, 2020.Applicant
- Universal Chiplet Interconnect Express (UCle) Specification, Revision 1.1, Version 1.0, Jul. 10, 2023.Applicant
- Hybrid Memory Cube Specification 2.1, Hybrid Memory Cube Consortium, HMC-30G-VSR PHY, 2014.Applicant
- Block Memory Generator v8.2 LogiCore IP Product Guide Vivado Design Suite; Xilinx; Apr. 1, 2015.Applicant
- Kurt Lender et al., “Questions from the Compute Express Link Exploring Coherent Memory and Innovative Cases Webinar”, Apr. 13, 2020, CXL consortium.Applicant
- Planet Analog, “The basics of SerDes (serializers/deserializers) for interfacing”, Dec. 1, 2020, Planet Analog.Applicant
- “Hot Chips 2017: Intel Deep Dives Into EMIB”, TomsHardware.com; Aug. 25, 2017.Applicant
- “Using Chiplet Encapsulation Technology to Achieve Processing-In-Memory Functions”; Micromachines 2022, 13, 1790; https://www.mdpi.com/journal/micromachines; Tian et al.Applicant
- “Multiport memory for high-speed interprocessor communication in MultiCom;” Scientia Iranica, vol. 8, No. 4, pp. 322-331; Sharif University of Technology, Oct. 2001; Asgari et al.Applicant
- Farjadrad et al., “A Bunch of Wires (BOW) Interface for Inter-Chiplet Communication”, 2019 IEEE Symposium on High-Performance Interconnects (HOTI), pp. 27-30, Oct. 2019.Applicant
- Universal Chiplet Interconnect Express (UCIe) Specification Rev. 1.0, Feb. 24, 2022.Applicant
- Brinda Ganesh et al., “Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling”, 2007, IEEE, 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp. 1-12 (Year: 2007).Applicant
- Anu Ramamurthy, “Chiplet Technology & Heterogeneous Integration” Jun. 2021, NASA, 2021 NEPP ETW, slides 1-17 (Year: 2021).Applicant
- Wikipedia, “Printed circuit board”, Nov. 9, 2021, Wayback Machine, as preserved by the Internet Archive on Nov. 9, 2021, pp. 1-23 (Year: 2021).Applicant