Cross-coupling connections for stacked field effect transistors

[0001] The disclosure relates generally to stacked field effect transistor (FET) devices. The disclosure relates particularly to stacked FET devices having latch cross-coupling connections.

[0002] Latch cross-coupling of transistor pairs are often present in circuit designs for information scannable D-flip-flops, storage and other uses. Scannable D-flip-flops may constitute up to 40% of the total area of a logic portion of a semiconductor device. Implementing the cross-coupling connections in planar arrays of transistors is relatively straightforward.

[0003] The following presents a summary to provide a basic understanding of one or more embodiments of the disclosure. This summary is not intended to identify key or critical elements or delineate any scope of the particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later.

[0004] In one aspect, a semiconductor device includes a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.

[0005] In one aspect, a semiconductor device includes a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a gate cut region disposed adjacent to a gate of the first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate over the gate cut region, a bonding dielectric layer disposed between the first upper transistor and the first lower transistor, and a cross-connection disposed through the bonding dielectric layer and in contact with the gate extension and a gate of the first upper transistor.

[0006] In one aspect, a method of fabricating a semiconductor device comprising cross-connected transistor includes forming a first lower transistor and a second lower transistor, forming a lower transistor gate extension from a gate of the first lower transistor toward a gate of the second lower transistor, forming a first upper transistor above the second lower transistor, and forming a cross-connection between a gate of the first upper transistor and the gate extension.

[0029] Some embodiments will be described in more detail with reference to the accompanying drawings, in which the embodiments of the present disclosure have been illustrated. However, the present disclosure can be implemented in various manners, and thus should not be construed to be limited to the embodiments disclosed herein.

[0030] It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.

[0031] It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0032] The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

[0033] Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0034] It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGel-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

[0035] Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

[0036] It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not tended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

[0038] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations and the spatially relative descriptors used herein can be interpreted accordingly. In addition, be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers cat also be present.

[0039] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

[0040] Deposition processes for the metal liner and sacrificial material include, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use PVD, a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In alternative embodiments that use GCIB deposition, a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters. The clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.

[0041] One of the processing complexities of stacked CMOS devices that needs to be addressed at nodes beyond 5 nm is providing final devices having cross-connections enabling the formation of latch circuits, such as scannable D flip-flop circuits. Though such cross-connections may be easily formed for planar arrays of transistors, forming comparable cross-connections for stacked CMOS structure presents a challenge. Disclosed embodiments enable latch circuit designs which incorporate stacked CMOS transistor pairs through integrated device cross-connections between upper and lower transistors of adjacent stacked CMOS pairs.

[0042] Reference is now made to the figures. The figures provide schematic cross-sectional illustration of semiconductor devices at intermediate stages of fabrication, according to one or more embodiments of the invention. The figures provide a front cross-section (X) parallel to the nanosheet fins of the device, and side cross-sections (Y1), (Y2), parallel to the gate structures of the device. The figures provide schematic representations of the devices of the invention and are not to be considered accurate or limiting with regards to device element scale.

[0043] FIG. 1A provides a schematic plan view of a device, according to an embodiment of the invention. As shown in the Figure, gate structures 12, are disposed perpendicular to nanosheet stack fins 14. Section lines X, Y1 and Y2, indicate the viewpoints of the respective views of FIGS. 1B-19.

[0044] FIG. 1B provides a schematic view of the device according to an embodiment of the invention following the deposition, patterning, selective removal of material leaving a stack of layers for the formation of lower device nanosheets. In an embodiment, the stack includes alternating layers of epitaxially grown silicon germanium (SiGe) 140, and silicon 130, disposed upon underlying substrate 110. Other materials having similar properties may be used in place of the SiGe and Si.

[0045] The terms “epitaxially growing and/or depositing” and “epitaxially grown and/or deposited” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed.

[0046] The nanosheet stack includes a bottom-most layer of a first semiconductor material, such as SiGe and a top-most layer of a second semiconductor material, such as SiGe having a different (lower) Ge concentration. The nanosheet stack is depicted with four layers (two SiGe layers 140 and two Si layers 130 forming a lower device), however any number and combinations of layers can be used so long as the layers alternate between SiGe and Si to form lower devices. The nanosheet stack is depicted with the layers being in the form of nanosheets, however the width of any given nanosheet layer can be varied so as to result in the form of a nanowire, a nanoellipse, a nanorod, etc. SiGe layers 140, can be composed of, for instance, SiGe_20-60, examples thereof including, but not limited to SiGe₂₀, SiGe₂₅, SiGe₃₀ . . . SiGe₆₅.

[0047] Substrate 110 can be composed of any currently known or later developed semiconductor material, which may include without limitation, silicon, germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula Al_X1Ga_X2In_X3As_Y1P_Y2N_Y3Sb_Y4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include II-VI compound semiconductors having a composition Zn_A1Cd_A2Se_B1Te_B2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Insulating layer 120 may be present on substrate 110 and, if present, is located between substrate 110 and the nanosheet stack. Insulating layer 120 can be, for example, a buried oxide layer (typically SiO₂) or a bottom dielectric isolation layer formed early in the process (typically SiN, SiBCN, SiOCN, SiOC, or any combination of low-k materials).

[0048] In an embodiment, each sacrificial semiconductor material layer 140, is composed of a first semiconductor material which differs in composition from at least an upper portion of the semiconductor substrate 110. In one embodiment, the upper portion of the semiconductor substrate 110 is composed of silicon, while each sacrificial semiconductor material layers 140 is composed of a silicon germanium alloy. In an embodiment, the SiGe alloy that provides each sacrificial semiconductor material layer 140 has a germanium content that is less than 50 atomic percent germanium. In one example, the SiGe alloy that provides each sacrificial semiconductor material layer 140 has a germanium content from 20 atomic percent germanium to 40 atomic percent germanium. The first semiconductor material that provides each sacrificial semiconductor material layers 140 can be formed utilizing an epitaxial growth (or deposition process).

[0049] Each semiconductor channel material layer 130, is composed of a second semiconductor material that has a different etch rate than the first semiconductor material of the sacrificial semiconductor material layers 140 and is also resistant to Ge condensation. The second semiconductor material of each semiconductor channel material layer 130, may be the same as, or different from, the semiconductor material of at least the upper portion of the semiconductor substrate 110. The second semiconductor material can be a SiGe alloy provided that the SiGe alloy has a germanium content that is less than 50 atomic percent germanium, and that the first semiconductor material is different from the second semiconductor material.

[0050] In one example, at least the upper portion of the semiconductor substrate 110 and each semiconductor channel material layer 130 is composed of Si or a III-V compound semiconductor, while each sacrificial semiconductor material layer 140, is composed of a silicon germanium alloy. The second semiconductor material of each semiconductor channel material layer 130, can be formed utilizing an epitaxial growth (or deposition process).

[0051] Following deposition of the stack of layers 130, and 140, across the surface of the device die, the layers are patterned using a process such as lithographic masking, and selectively etched, yielding a pattern of device fins. Such fin stacks define the active regions of the lower devices.

[0052] In an embodiment, the etching proceeds into substrate 110. Deposition of a shallow trench isolation (STI) material 120, such as silicon dioxide, or any suitable combination of multiple dielectric materials (e.g., silicon nitride and silicon oxide), occurs after the formation of shallow trench isolation (STI) regions between nanosheet stack circuit elements of the device. Following such deposition, chemical mechanical planarization (CMP) processes smooth the upper surface of the deposited oxide in preparation for the subsequent fabrication steps. An oxide recess process trims the upper surface of STI regions to the level of the bottom sacrificial semiconductor layer 140. STI regions 120 provide electrical isolation between adjacent nanosheet devices.

[0053] FIG. 1B further illustrates the device 100 following the forming at least one dummy gate structure 150, on the nanosheet stack. Two dummy gates 150 are shown in the Figure, however any number of gates can be formed. Dummy gate structures can be formed by depositing a dummy gate material 150 over the nanosheet stack. The dummy gate material can be, for example, a thin layer of oxide, followed by polycrystalline silicon, amorphous silicon or microcrystal silicon. After that, a hardmask layer (not shown) is deposited over the dummy gate, followed by lithographic patterning, masking, and etching processes yielding the dummy gate structures of the Figure.

[0054] In an embodiment, the hardmask includes a nitride, oxide, an oxide-nitride bilayer, or another suitable material. In some embodiments, the hardmask may include an oxide such as silicon oxide (SiO), a nitride such as silicon nitride (SiN), an oxynitride such as silicon oxynitride (SiON), combinations thereof, etc. In some embodiments, the hardmask is a silicon nitride such as Si₃N₄.

[0055] FIG. 1B further illustrates the device following conformal deposition of low-k dielectric spacer materials 160, to form sidewall spacers along the sidewalls of dummy gate structures 150. In an embodiment, spacer material 160 may be the same material as hardmask or may be different materials and may be comprised of any one or more of a variety of different insulative materials, such as Si₃N₄, SiBCN, SiNC, SiN, SiCO, SiO₂, SiNOC, etc.

[0056] FIG. 1B further illustrates the device after selective removal of spacer sidewall materials 160 from the horizontal surfaces of the dummy gate hard mask. In an embodiment, anisotropic etching is used to selectively remove the horizontal surfaces of the dummy gate hard mask. FIG. 1B further illustrates the device following recessing the nanosheet stack layers 130, 140, and spacer layer 160, to form the source-drain (S/D) cavities for lower devices.

[0057] Etching generally refers to the removal of material from a substrate (or structures formed on the substrate) and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate.

[0058] There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching.

[0059] FIG. 1B further illustrates device 100 following SiGe indentation and inner spacer formation (not shown) and epitaxial growth of source/drain regions 170, for the lower FET device of the stacked CMOS. In an embodiment, pairs of lower epitaxial source/drain regions are formed on opposing sides of nanosheet stacks and dummy gate structures. In an embodiment, boron doped SiGe (SiGe:B) is epitaxially grown from exposed semiconductor surfaces (layer 130) for the formation of p-type FET device on the bottom. In this embodiment, the bottom device S/D regions comprise p-type materials. As an alternative, the bottom S/D regions may instead comprise n-type materials.

[0060] In the present embodiments, the source/drain regions 170 may be doped in situ by adding one or more dopant species to the epitaxial material. The dopant used will depend on the type of FET being formed, whether p-type or n-type. As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon-containing semiconductor, examples of p-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium and indium. As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous. In an embodiment, the lower regions comprise p-type materials. In an embodiment, the lower regions comprise n-type materials.

[0061] FIG. 1B further illustrates the device following deposition, and planarization of a interlayer dielectric (ILD) 180, composed of any suitable dielectric material, for example Si₃N₄, SiBCN, SiNC, SiN, SiCO, SiO₂, SiNOC, etc. This can be achieved by a conformal deposition of ILD 180 to pinch-off the gate-to-gate space or just overfill the sacrificial spacer material then followed by a chemical mechanical planarization (CMP) to a desired upper surface height for the ILD 180.

[0062] FIG. 2 illustrates device 100 following the formation of a number of gate extension cuts 210 through the dummy gate structure, sidewalls and ILD materials using lithographic patterning and selective etching.

[0063] FIG. 3 illustrates device 100 following filling the gate extension cuts with a material similar to that of the dummy gate structure 150. The filled gate extensions cuts serve as placeholders for future device cross-connection contacts.

[0064] FIG. 4 illustrates device 100 following bonding a top device layer over the bottom device. The top device can be nanosheet device comprising alternative semiconductor channel layers 430 and sacrificial layers 420. The top device can also be FINFET device, and in that case a Si layer is bonded. The bonding process can be conventional dielectric-to-dielectric bonding, such as oxide-to-oxide bonding. Here layer 410 represents the bonding oxide in case oxide-to-oxide bonding is used.

[0065] FIG. 5 illustrates device 100 following the formation of active regions for top device by patterning the top nanosheet stack into Fins, and formation of dummy gate structures 510, and sidewalls 520, similar to the fabrication of such lower device structures as described with respect to FIG. 1B above. FIG. 5 further illustrates the device following the formation of inner spacer (not shown) and epitaxial growth of upper FET source/drain regions 530 in a manner similar to that used for the formation of lower FET source/drain regions 170. In an embodiment, the lower device FETs comprise n-type devices and the upper FETs comprise p-type devices. This should not be construed as limiting the invention as the lower devices may comprise n-type devices and the upper FETs may comprise p-type devices. In an embodiment, each set of upper or lower devices comprise a single polarity (n-type or p-type) with the other set comprising the opposite polarity. FIG. 5 further illustrates device 100 following deposition and CMP of an ILD material 540, similar to ILD material 180 referenced with regard to FIG. 1 above.

[0066] FIG. 6 illustrates device 100 following the formation of gate openings 610 through inter-stack bonding oxide layer 410, enabling replacement gate formation and future cross-connections between upper and lower devices of adjacent CMOS stacks.

[0067] FIG. 7 illustrates device 100 following selective release and removal of lower and upper dummy gate materials 150 and 510, and gate extension 310 using a selective etch of the materials.

[0068] FIG. 8 illustrates device 100 following the formation of the high-k metal gate (HKMG) stack. As shown in the Figure, a replacement metal gate structure 810, has been formed in the void space created by removal of the spacer material 210, 610. Gate structure 810 includes gate dielectric and gate metal layers. The gate dielectric is generally a thin film and can be silicon oxide, high-k materials, or any combination of these materials. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials may further include dopants such as lanthanum, aluminum, magnesium. Gate dielectric can be deposited by CVD, ALD, or any other suitable technique. Metal gates can include any known metal gate material known to one skilled in the art, e.g., TiN, TiAl, TiC, TiAlC, tantalum (Ta) and tantalum nitride (TaN), W, Ru, Co, Al. Metal gates may be formed via known deposition techniques, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. It should be appreciated that a CMP process can be applied to the top surface. In an embodiment, the replacement metal gate includes work-function metal (WFM) layers, (e.g., titanium nitride, titanium aluminum nitride, titanium aluminum carbide, titanium aluminum carbon nitride, and tantalum nitride) and other appropriate metals and conducting metal layers (e.g., tungsten, cobalt, tantalum, aluminum, ruthenium, copper, metal carbides, and metal nitrides). The term work function metal includes a single metal layer as well as a stack of metal layers, or surface dipoles combined with a single or stack of metal layers. After formation and CMP of the HKMG, the HKMG can be optionally recessed followed by a deposition and CMP of a gate cap dielectric material (not shown), such as SiN, or similar materials, completing the replacement metal gate fabrication stage for the device.

[0069] FIG. 9 illustrates device 100 following the formation and backfilling of additional lower gate cuts 920 and upper gate cuts 910, isolating the gate of the upper FET device from the gate of the lower FET, as well as gates between neighboring cells.

[0070] FIG. 10 illustrates device 100 following formation of device contacts 1010, connecting upper device S/D regions 530, and lower device S/D regions 170, through ILD layer 1020, as well as formation of the back-end-of-line structure 1030 (V0 and M1). The Figure illustrates the cross connection 1040 between the gate of an upper FET of device stack and the gate extension of a lower FET of an adjacent gate. A similar cross-connection (not shown) connects the other upper-lower device pairing of the combined adjacent stacked devices.

[0071] FIG. 11 illustrates device 200 at an intermediate stage of device fabrication, similar to that illustrated in FIG. 1B as described above. As shown in the Figure, the device includes substrate 1110, STI regions 1120, sacrificial nanosheets 1140, channel nanosheets 1130, dummy gates 1150, sidewall spacers 1160, ILD layer 1180, and lower S/D regions 1170.

[0072] FIG. 12 illustrates device 200 following formation of gate cuts 1210 through portions of each dummy gate structure 1150. These gate cuts serve to isolate the dummy gates in preparation for forming gate cross-connection regions between upper and lower devices of adjacent stacked device pairs.

[0073] FIG. 13 illustrates device 200 following the formation of gate extensions 1310 between dummy gates 1150, and gate cuts 1210, as well as the filling of the extensions through the deposition of dummy gate material.

[0074] FIG. 14 illustrates device 200 following bonding the top channel materials. FIG. 14 further illustrates formation Fin stacks of sacrificial layer 1420, similar to sacrificial layers 140, and crystalline semiconductor layers 1430, similar to the semiconductor materials of semiconductor nanosheets 130.

[0075] FIG. 14 further illustrates device 200 following the formation of dummy gate structures 1450, and sidewalls 1460, similar to the fabrication of such lower device structures as described with respect to FIG. 11 above. FIG. 14 further illustrates the device following epitaxial growth of upper FET source/drain regions 1470 in a manner similar to that used for the formation of lower FET source/drain regions 1170. In an embodiment, the lower device FETs comprise n-type devices and the upper FETs comprise p-type devices. This should not be construed as limiting the invention as the lower devices may comprise n-type devices and the upper FETs may comprise p-type devices. In an embodiment, each set of upper or lower devices comprise a single polarity (n-type or p-type) with the other set comprising the opposite polarity. FIG. 14 further illustrates device 200 following deposition and CMP of an ILD material 1480, similar to ILD material 180 referenced with regard to FIG. 11 above.

[0076] FIG. 15 illustrates device 200 following the formation of gate openings 1510 through dummy gates 1150 and inter-stack bonding oxide layer 1410, enabling formation of replacement gate and future cross-connections between upper and gate extensions 310, of the lower devices of adjacent CMOS stacks.

[0077] FIG. 16 illustrates device 200 following selective release and removal of lower and upper dummy gate materials 150 and 1450, and gate extension using a selective etch of the materials. This removal exposes upper and lower device channels, 130, 1130, and lower gate extension structures.

[0078] FIG. 17 illustrates device 1200 following the formation of the high-k metal gate (HKMG) stack. As shown in the Figure, a replacement metal gate structure 1710, has been formed in the void space created by removal of the dummy gate materials 150, 1150. Gate structure 1710 includes gate dielectric and gate metal layers. The gate dielectric is generally a thin film and can be silicon oxide, high-k materials, or any combination of these materials. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials may further include dopants such as lanthanum, aluminum, magnesium. Gate dielectric can be deposited by CVD, ALD, or any other suitable technique. Metal gates can include any known metal gate material known to one skilled in the art, e.g., TiN, TiAl, TiC, TiAlC, tantalum (Ta) and tantalum nitride (TaN), W, Ru, Co, Al. Metal gates may be formed via known deposition techniques, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. It should be appreciated that a CMP process can be applied to the top surface. In an embodiment, the replacement metal gate includes work-function metal (WFM) layers, (e.g., titanium nitride, titanium aluminum nitride, titanium aluminum carbide, titanium aluminum carbon nitride, and tantalum nitride) and other appropriate metals and conducting metal layers (e.g., tungsten, cobalt, tantalum, aluminum, ruthenium, copper, metal carbides, and metal nitrides). The term work function metal includes a single metal layer as well as a stack of metal layers, or surface dipoles combined with a single or stack of metal layers. After formation and CMP of the HKMG, the HKMG can be optionally recessed followed by a deposition and CMP of a gate cap dielectric material (not shown), such as SiN, or similar materials, completing the replacement metal gate fabrication stage for the device. The Figure illustrates the cross connection 1720 between the gate of an upper FET and the gate of a lower FET of an adjacent device. A similar cross-connection (not shown) connects the other upper-lower device pairing of the combined adjacent stacked devices.

[0079] FIG. 18 illustrates device 200 following the formation and backfilling of additional gate cuts 1810, isolating upper FET devices from the lower FET devices, as well as devices between neighboring cells.

[0080] FIG. 19 illustrates device 200 following formation of device contacts 1910, connecting upper device S/D regions 1470, and lower device S/D regions 1170, through ILD layer 1480, as well as formation of the back-end-of-line structure 1930 (V0 and M1). As shown in FIG. 19, the cross-connections between adjacent upper and lower devices are contained within the bonding oxide, gate cut and ILD layers of the device. This clears the way for additional options in configuring the MOL and BEOL contacts for the upper and lower device S/D regions.

[0081] FIG. 20 depicts a fabrication process flowchart 2000, according to an embodiment of the invention. As shown in flowchart 2000, at block 2010, the method forms first and second lower FET gate structures. Stacks of alternating nanosheet layers of differing semiconductor materials are epitaxially grown upon an underlying substrate, or upon an insulating layer disposed upon a substrate. The stacks include sacrificial layers and channel layers. The channel layers form the nanosheet channels of the lower FETs of the stacked CMOS. The layers are patterned and etched to form fins upon the underlying substrate as well as shallow trench isolation regions between otherwise adjacent stacks of nanosheets. Dummy gate structures including gate sidewall spacers are added atop and along the fins. The nanosheet layers are recessed to align with the dummy gate spacers and inner spacers between nanosheet channel layers are formed to isolate the gates from the S/D regions of the devices. The method grows S/D regions for the lower FET devices.

[0082] At block 2020, the method forms isolating regions in gate cuts made in each of the dummy gates of the first and second lower FETs. The method further forms gate extensions between adjacent gate structures extending from one dummy gate region into an adjacent dummy gate region across a gap separating the otherwise adjacent dummy gate structures.

[0083] At block 2030, the method forms an upper FET dummy gate structures including gate sidewall spacers and grows upper FET S/D regions for at least one upper FET stacked above the second lower FET. In an embodiment, the method forms a third FET above the second lower FET and a fourth FET above the first lower FET.

[0084] At block 2040, the method forms connections between upper and lower devices using the gate extensions connecting the upper device gate and an adjacent lower device gate. In an embodiment, the method forms cross-connections between a third upper device and a first lower device as well as a cross-connection between a fourth upper device and a second lower device.

[0085] At block 2050, the method forms metal gates, replacing the upper and lower dummy gate structures.

[0086] At block 2060, the method forms S/D and gate contacts for the upper and lower FETs of the stacked CMOS device. Metal contacts fill vias formed in interlayer dielectric layers encapsulating the bottom FET devices.

[0087] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and device fabrication steps according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more fabrication steps for manufacturing the specified device(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

[0088] References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0089] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.