Page buffers and operation methods thereof, memory devices, and memory systems

[0001] This application claims priority to and the benefit of Chinese Patent Application 202311607431.X, filed on Nov. 27, 2023, which is hereby incorporated by reference in its entirety.

[0002] Examples of the present disclosure relate to semiconductor technology, and relate to but not limited to page buffers and operation methods thereof, memory devices, and memory systems.

[0003] Semiconductor memories may be roughly divided into two categories, depending on whether they retain stored data in the case of loss of power. Such two categories of semiconductor memories are: volatile memories and non-volatile memories. The volatile memories lose the stored data in the case of the loss of power, and the non-volatile memories retain the stored data in the case of loss of power. Memory cells in the non-volatile memories are connected to bit lines and word lines respectively, and thus have good random access time characteristics.

[0028] In order to facilitate the understanding of the present application, the present application will be described below more comprehensively with reference to the relevant drawings. Preferable examples of the present application are given in the drawings. However, the present application may be implemented in many different forms, and is not limited to the examples described herein. Instead, the purpose of providing these examples is to make the disclosure of the present application more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the technical field of the present application. The terms used in the specification of the present application are only for the purpose of describing examples, and are not intended to limit the present application. The term “and/or” used herein include any and all combinations of one or more listed associated items.

[0030] The terms “first”, “second” and the like used in the present application do not indicate any order, quantity, or significance, but are used only to distinguish different constituent parts. Similarly, the term such as “one”, “a” or “the” does not indicate a quantitative limitation, but refers to “at least one”. The term such as “including” or “containing” means that a component or object appearing in front of the term covers a component or object listed following the term and its equivalents, without excluding other components or objects. The term such as “connecting”, “connected” or “coupling” is not defined as physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0031] In order to understand the present application thoroughly, detailed operations and detailed structures will be proposed in the following description to set forth the technical solution of the present application. The detailed descriptions of the preferable examples of the present application are as follows. However, the present application may also have other implementations in addition to these detailed descriptions.

[0032] With the increase of an integration level of the memory, an area occupied by a page buffer in a peripheral circuit of the memory device is limited and tends to decrease as required, and thus a reduction in the number of elements constituting the page buffer is also required.

[0033] As shown in FIG. 1, examples of the present application illustrate an electronic system 10. In an example, the electronic system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning apparatus, a wearable electronic apparatus, a smart sensor, a Virtual Reality (VR) apparatus, an Augmented Reality (AR) apparatus or any other suitable electronic apparatuses having memory devices 32 therein.

[0034] With continued reference to FIG. 1, the electronic system 10 may comprise a host 20 and a memory system 30.

[0035] The host 20 may be a processor (for example, a Central Processing Unit (CPU), or a System on a Chip (SoC) (e.g., an Application Processor (AP)) of an electronic apparatus. The host 20 may be configured to send or receive data to or from the memory system 30.

[0036] The memory system 30 comprises a memory controller 31 and one or more memory devices 32, as well as other integrated circuit structures used for signal transmission. The memory controller 31 and the one or more memory devices 32 may be integrated and packaged in the same memory apparatus. As such, it is favorable to the application of the memory system 30 in different types of end electronic products.

[0037] In an example, types of the memory apparatus that integrates the memory controller 31 and the one or more memory devices 32 include: Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC), among other types of memory apparatuses.

[0038] There are various patterns of integrated circuits of the memory apparatus, e.g., a memory card 40 (as shown in FIG. 2) formed by integrating a single memory device 32 and the memory controller 31 together, or an SSD 50 (as shown in FIG. 3) formed by integrating a plurality of memory devices 32 and the memory controller 31 together.

[0039] In an example, the memory card 40 may include one or more types of memory apparatuses among a Personal Computer Memory Card International Association (PC) card, a CF card, a Smart Media (SM) card, a memory stick, a Multi-Media Card (MMC, Reduced-Size MMC (RS-MMC), and MMCmicro), an SD card (SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), and a UFS, etc.

[0040] With continued reference to FIG. 2, the memory card 40 further comprises a memory card connector 41. The memory card connector 41 is configured to couple the memory card 40 with a host (e.g., the host 20 in FIG. 1). For example, the memory card connector 41 includes a golden finger.

[0041] Alternatively, with continued reference to FIG. 3, the SSD 50 further comprises an SSD connector 51. The SSD connector 51 is configured to couple the SSD 50 with a host (e.g., the host 20 in FIG. 1). For example, the SSD connector 51 includes a golden finger.

[0042] It may be understood that a storage capacity and/or operation speed of the SSD 50 are greater than a storage capacity and/or operation speed of the memory card 40.

[0043] The memory controller 31 integrated in the same memory apparatus is coupled with the memory device 32 (and the host 20), and the memory controller 31 is configured to control the memory device 32.

[0044] In an example, the memory controller 31 may be designed to operate in a low duty-cycle environment. For example, the memory controller is configured to operate in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic apparatuses, such as a personal computer, a digital camera, and a mobile phone, etc. In another example, the memory controller 31 may be designed to operate in a high duty-cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC). The SSD or eMMC may be used as a data storage for mobile apparatuses, such as a smartphone, a tablet computer, and a laptop computer, etc., and an enterprise memory array.

[0045] Further, the memory controller 31 can manage data in the memory device 32 and communicate with the host 20. The memory controller 31 may be configured to control read, erase and program operations of the memory device 32, may be further configured to manage various functions with respect to data stored or to be stored in the memory device 32, including, but not limited to, bad-block management, garbage collection, logical-to-physical address translation, and wear leveling, etc., and may be further configured to process Error Checking and Correction (ECC) code with respect to data read from or written to the memory device 32.

[0046] Furthermore, the memory controller 31 may further perform any other suitable functions, e.g., formatting the memory device 32 or communicating with an external apparatus (e.g., the host 20 in FIG. 1) according to an example communication protocol. For example, the memory controller 31 may communicate with the host 20 through at least one of various interface protocols. The interface protocols include one or more of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol, etc.

[0047] The above memory device 32 may include, but is not limited to, one or more of a NAND Flash Memory, a Vertical NAND Flash Memory, a NOR Flash Memory, a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM), a Nano Random Access Memory (NRAM), etc.

[0048] Based on the above description, the present application uses the memory device 32 being a semiconductor memory, e.g., a solid state electronic device (such as a NAND memory) fabricated using a semiconductor integrated circuit process for storing data information, as an example for subsequent description of the implementations. The subsequent examples of the present application do not limit an interior structure of the memory device 32.

[0049] It may be understood that, in order to facilitate distinguishing between cases of adaptive adjustments made to the memory device 32 for applications to different scenarios, e.g., various example structures of the memory device 32 based on the above content, the memory device (e.g., NAND memory) provided in the subsequent examples of the present application is illustrated using a memory device 60.

[0050] As shown in FIG. 4, in some examples, the memory device 60 may comprise a memory cell array 61 and a circuit structure such as a peripheral circuit 62 coupled to the memory cell array 61, etc.

[0051] The memory cell array 61 is coupled with the plurality of bit lines (BLs). In an example, the memory cell array 61 may be a NAND flash memory cell array. For example, the memory cell array 61 is a circuit structure disposed in the form of an array arrangement of NAND memory strings 611. Each NAND memory string 611 extends vertically on a substrate. In an example, each NAND memory string 611 may comprise a plurality of memory cells that are coupled in series and stacked vertically. Each memory cell performs signal transmission in a state of holding a continuous analog value (such as a voltage or charge), and the analog value of the memory cell depends on a number of electrons trapped within a region of the memory cell.

[0052] In an example, each memory cell in the memory cell array 61 may be either a floating gate memory cell that includes a floating gate transistor, or a charge trap memory cell that includes a charge trap transistor. The present application does not impose limitations thereto.

[0053] In some examples, memory types of the above memory cells include any one of a Single Level Cell (SLC), a Multi Level Cell (MLC), a Triple Level Cell (TLC), and a Quad Level Cell (QLC), etc.

[0054] In an example, each SLC memory cell can store one bit of data and has two possible memory states: a first memory state and a second memory state. The first memory state (e.g., “0”) corresponds to a first threshold voltage range, and the second memory state (e.g., “1”) corresponds to a second threshold voltage range. As such, the second memory state (e.g., “1”) serves as an erased state, and the first memory state (e.g., “0”) serves as a programmed state.

[0055] In another example, each MLC memory cell can store two bits of data and has four possible memory states: a first memory state, a second memory state, a third memory state, and a fourth memory state. The first memory state (e.g., “11”) corresponds to a first threshold voltage range, the second memory state (e.g., “01”) corresponds to a second threshold voltage range, the third memory state (e.g., “10”) corresponds to a third threshold voltage range, and the fourth memory state (e.g., “00”) corresponds to a fourth threshold voltage range. As such, the fourth memory state (e.g., “00”) serves as an erased state, the first memory state (e.g., “11”), the second memory state (e.g., “01”), and the third memory state (e.g., “10”) serve as programmed states.

[0056] Similarly, each TLC memory cell can store three bits of data and has eight possible memory states. The eight memory states correspond to eight threshold voltage ranges respectively, and the memory states are no longer repeated here. One of the eight threshold voltage ranges serves as an erased state (e.g., “111”), and the other seven threshold voltage ranges serve as programmed states. Furthermore, each QLC memory cell can store four bits of data and has sixteen possible memory states. The sixteen memory states correspond to sixteen threshold voltage ranges respectively, and the memory states are no longer repeated here. One of the sixteen threshold voltage ranges serves as an erased state (e.g., “1111”), and the other fifteen threshold voltage ranges serve as programmed states.

[0057] With continued reference to FIG. 4, the above peripheral circuit 62 may be coupled to the memory cell array 61 via a Bit Line (BL), a Word Line (WL), a Source Line (SL), a Source Select Gate (SSG), and a Drain Select Gate (DSG). The peripheral circuit 62 is configured to implement a logic operation (e.g., a program, read, or write operation) on the memory cell array 61 by applying voltage signals and/or current signals to each target memory cell and sensing voltage signals and/or current signals from each target memory cell via the bit line BL, the word line WL, the source line SL, the source select gate SSG, or the drain select gate DSG, etc.

[0058] In an example, the peripheral circuit 62 comprises various types of circuit structures formed using Metal-Oxide-Semiconductor (MOS) transistors. For example, as shown in FIG. 5, the peripheral circuit 62 may comprise various circuit structures such as a row decoder/word line driver 620, a page buffer (PB)/sense amplifier 621, a column decoder/bit line driver 623, a voltage generator 624, a control logic unit 625, a latch circuit 626, an interface 627, and a data bus 628, etc.

[0059] Further, as shown in FIG. 6, the peripheral circuit 62 may comprise a page buffer group consisting of a plurality of page buffers 621. The page buffer group may be coupled with the memory cell array 61 via a plurality of bit lines (BL1 to BLk). One page buffer 621 is coupled with the memory cell array 61 via one bit line. For example, as shown in FIG. 6, the plurality of page buffers 621 may be coupled with the memory cell array 61 via the respective bit lines BL1 to BLk, respectively.

[0060] Based on the above content, in some examples, the page buffer 621 of the peripheral circuit 62 comprises a plurality of latches 6211. In an example, as shown in FIG. 7, the page buffer 621 of the peripheral circuit 62 comprises at least five latches 6211.

[0061] A latch 6211 comprises two phase inverters 6212 connected end-to-end, a data transmission circuit 6213, and other electronic elements. The two phase inverters 6212 comprise at least four transistors. In such case where the page buffer 621 comprises a plurality of latches 6211, especially for TLC and QLC memory cells, the page buffer 621 is required to be provided with more latches 6211 to realize data read or program, and thus there are more transistors in each page buffer 621. Accordingly, in the case where the peripheral circuit 62 implements the logic (e.g., program, read, or write) operation through the page buffer group (see FIG. 6), the number of the electronic elements of the plurality of page buffers 621 are accumulated, resulting in a sudden increase of a space occupied by the peripheral circuit 62 in the memory device 60 (e.g., occupying nearly ⅓ of an interior space of the memory device 60), thereby reducing an energy efficiency ratio of the memory device 60.

[0062] In order to solve the above problem, as shown in FIG. 8 to FIG. 20, the present application provides a structure of the page buffer 622, so as to simplify the circuit structure and reduce a space in the memory device 60 occupied by and fabrication costs of the page buffer 622.

[0063] In some examples, as shown in FIG. 8, the page buffer 622 comprises a bit line control circuit 6221, a bit line discharge circuit 6222, and a plurality of latch circuits 6223.

[0064] The bit line control circuit 6221 is coupled with a first supply voltage node N1, the bit line BL, and a sense node SO, and is configured to control a potential level of the sense node SO during a sense operation based on a current level of the bit line BL. For example, whether to charge the bit line may be determined according to a program verify result latched in the latch circuits 6223. For example, when the program verify result indicates that a memory cell reaches a target threshold voltage, the bit line BL coupled to the memory cell may be charged to a program inhibit bit line voltage (e.g., VDD) through the bit line control circuit 6221, so as to inhibit program; and when the program verify result indicates that the memory cell does not reach the target threshold voltage, the bit line BL coupled to the memory cell may be regulated to a normal program bit line voltage (e.g., VSS) or a bit line BL force voltage (greater than VSS and less than VDD) through the bit line control circuit 6221, so as to continue the programming.

[0065] The bit line discharge circuit 6222 is coupled between the bit line BL and a second supply voltage node N2 and is configured to discharge a potential level of the bit line BL in response to a discharge control signal (e.g., VDD).

[0066] It may be understood that a level of the first supply voltage node N1 is VDD, and a level of the second supply voltage node N2 is VSS. An identifier of a “node” adopted in an example of the present application only characterizes a transmission signal level feature of the node in an example, but does not limit a magnitude of an actual level signal transmitted by the node.

[0067] The plurality of latch circuits 6223 are all coupled with the sense node SO, and charge and discharge the level of the sense node SO under driving of the bit line control circuit 6221 and the bit line discharge circuit 6222. For example, there are six latch circuits 6223 in the page buffer 622 as shown in FIG. 9. The six latch circuits 6223 may comprise a Sense Latch (S Latch), a Low Voltage Latch (LVT Latch), three Data Latches (D Latch), and a Cache Latch (C Latch).

[0068] The sense latch S Latch may be configured to store inhibition information and verification information from a verify operation.

[0069] The cache latch C Latch is configured to perform data exchange with the outside, for example, external data is first transmitted to the cache latch C Latch, and then transmitted to the sense latch S Latch through the cache latch C Latch. For another example, the data in the sense latch S Latch is transmitted to the cache latch C Latch, and then transmitted to the outside through the cache latch C Latch. The outside may be the memory controller 31 or the host 20, etc. For still another example, the cache latch C Latch may also be used for other functions, e.g., for temporarily storing the verification information.

[0070] The data latch D Latch may be configured to latch data of a designated page of the memory cell.

[0071] The low voltage latch LVT Latch may be configured to store the inhibition information and adjusted verification information from a verify operation.

[0072] In some examples, memory cell-based memory types include memory types such as an SLC, an MLC, a TLC, and a QLC.

[0073] If the memory cell is an SLC, the latch circuits 6223 in the page buffer 622 may include the cache latch. The cache latch is configured to latch data of the memory cell.

[0074] If the memory cell is an MLC, in addition to the cache latch C Latch, the page buffer 622 may further comprise one data latch D Latch. The data latch D Latch may be configured to latch data of a lower page of the memory cell, and the cache latch C Latch may be configured to latch data of an upper page of the memory cell.

[0075] If the memory cell is a TLC, in addition to the cache latch C Latch, the page buffer 622 may further comprise two data latches D Latch. One data latch D Latch may be configured to latch the data of the lower page of the memory cell, the other data latch D Latch may be configured to latch data of a middle page of the memory cell, and the cache latch C Latch may be configured to latch the data of the upper page of the memory cell.

[0076] By analogy, if the memory cell is an nLC, the number of data latches D Latch in the page buffer 622 may be n−1, wherein the n−1 data latches D Latch respectively latch data of designated pages of the memory cell, and n is a positive integer greater than 0.

[0077] It may be understood that the sense latch S Latch, the low voltage latch LVT Latch, the data latch D Latch, and the cache latch C Latch contain subcircuits of partially identical structures, and the subcircuits of the partially identical structures can implement complete data transmission. The sense latch S Latch and the cache latch C Latch further comprise additional electronic elements to assist in the implementation of the data transmission, and the present application imposes no limitations on structures of the additional electronic elements. In subsequent examples, the partially identical circuit structures of different types of latch circuits 6223 are illustrated, and thus the reference to the latch circuits 6223 in the subsequent examples does not limit the types of the latch circuits 6223.

[0078] In some examples, as shown in FIG. 10, each latch circuit 6223 comprises a resetting control circuit 6201, a setting control circuit 6202, a data transmission circuit 6203, and a latch transmission circuit 6204.

[0079] The resetting control circuit 6201 is coupled to a first data node Data and is configured to receive a first supply voltage V1, so as to determine a potential of the first data node Data.

[0080] The setting control circuit 6202 is coupled to a second data node Data_bar and is configured to receive the first supply voltage V1, so as to determine a potential of the second data node Data_bar.

[0081] The data transmission circuit 6203 is coupled to the first data node Data and the second data node Data_bar and is configured to receive a second supply voltage V2.

[0082] The latch transmission circuit 6204 is coupled to the first data node Data, the second data node Data_bar, and the sense node SO.

[0083] The first supply voltage V1 is higher than the second supply voltage V2. In an example, a level of the first supply voltage V1 is VDD, a level of the second supply voltage V2 is VSS, and VDD is greater than VSS.

[0084] By coupling the latch transmission circuit 6204 in the page buffer 622 with the first data node Data and the second data node Data_bar, the present application controls the latch transmission circuit 6204 to be connected with or disconnected from the sense node SO based only on logic levels of the first data node Data and the second data node Data_bar.

[0085] As such, in the case where the latch transmission circuit 6204 need not be coupled with the second supply voltage node N2 (as shown in FIG. 7, the phase inverters 6212 and the data transmission circuit 6213 are grounded), the latch transmission circuit is controlled to be connected with or disconnected from the sense node based on the logic levels of the first data node Data and the second data node Data_bar that are obtained under a joint action of the data transmission circuit 6203, the setting control circuit 6202, and the resetting control circuit 6201, thus reducing grounding line structures. Moreover, the number of electronic elements (e.g., transistors) is also reduced due to not using the phase inverters 6212, thereby reducing the fabrication costs of and the space in the memory device 60 occupied by the page buffer 622. In the case where the memory device 60 comprises a page buffer group or comprises page buffers 622 for driving a multi level cell type, the fabrication costs of and the space occupied by the page buffer 622 can be reduced significantly.

[0086] Moreover, due to the simplified circuit structure, the complexity of a signal transmission path between the page buffer 622 and the sense node SO is reduced, a loss during transmission of the level signal is reduced, and thus the overall performance of the memory device 60 is improved.

[0087] Furthermore, under the condition that an area occupied by the page buffer 622 is unchanged, more latch circuits 6223 may be disposed (e.g., data latch circuits 6223 are added), so as to meet demands of the memory device 60 of more bits of data, such that more bits of data information may be stored, which is favorable to increase a bit density of the memory device 60.

[0088] In some examples, the setting control circuit 6202 is configured to set the second data node Data_bar and the first data node Data to a first logic level and a second logic level respectively in response to a setting signal set being in an enabled state. The first logic level is higher than the second logic level.

[0089] In an example, the first logic level is a high level, and the second logic level is a low level. It may be understood that the “high level” and “low level” are two signal levels indicative of relative magnitudes of level signals. For example, the first logic level is VDD, the second logic level is VSS, and VDD is greater than VSS. As such, the level of the second data node Data_bar is VDD, and the level of the first data node Data is VSS.

[0090] The resetting control circuit 6201 is configured to set the first data node Data and the second data node Data_bar to the first logic level and the second logic level respectively in response to a reset signal rst being in an enabled state. For example, the level of the second data node Data_bar is VSS, and the level of the first data node Data is VDD.

[0091] The latch transmission circuit 6204 is configured to couple the second data node Data_bar with the sense node SO in response to a transmission signal rd being in an enabled state and the first data node Data and the second data node Data_bar being at the first logic level and the second logic level respectively, wherein the sense node SO is at the second logic level (e.g., VSS).

[0092] The above transmission signal rd is a signal transmitted by an Rd end (referring to FIG. 10). For ease of understanding, an identity of a signal end provided in the example of the present application is distinguished from an identifier of a signal transmitted by the signal end through capitalization of the first letter. It is similar for identities of signals such as the setting signal set, the reset signal rst, a prech_sel_en signal, a prech_all_en signal, and a data setting signal rst_sa_latch mentioned in subsequent examples (corresponding to various signal ends as shown in FIG. 15 and FIG. 19).

[0093] In some examples, the latch transmission circuit 6204 is further configured to, when the sense node SO is at the first logic level, maintain the sense node SO at the first logic level in response to the transmission signal rd being in the enabled state and the first data node Data and the second data node Data_bar being at the second logic level and the first logic level respectively.

[0094] In an example, the sense node SO is at the first logic level. When the level of the second data node Data_bar is VDD and the level of the first data node Data is VSS, the latch transmission circuit 6204 disconnects the second data node Data_bar from the sense node SO, so that the sense node SO is maintained at the first logic level.

[0095] In some examples, as shown in FIG. 11, the data transmission circuit 6203 comprises a first transistor T1 and a second transistor T2.

[0096] A control electrode of the first transistor T1 is coupled with the first data node Data, a first electrode of the first transistor T1 is coupled with the second supply voltage node N2, and a second electrode of the first transistor T1 is coupled with the second data node Data_bar. A control electrode of the second transistor T2 is coupled with the second data node Data_bar, a first electrode of the second transistor T2 is coupled with the second supply voltage node N2, and a second electrode of the second transistor T2 is coupled with the first data node Data.

[0097] In an example, with continued reference to FIG. 11, the first transistor T1 and the second transistor T2 are N-type transistors.

[0098] In some examples, as shown in FIG. 12, the resetting control circuit 6201 comprises a third transistor T3. A control electrode of the third transistor T3 receives the reset signal rst, a first electrode of the third transistor T3 is coupled with the first supply voltage node N1, and a second electrode of the third transistor T3 is coupled with the first data node Data.

[0099] In an example, as shown in FIG. 12, the third transistor T3 is a P-type transistor.

[0100] In some examples, as shown in FIG. 13, the setting control circuit 6202 comprises a fourth transistor T4. A control electrode of the fourth transistor T4 receives the setting signal set, a first electrode of the fourth transistor T4 is coupled with the first supply voltage node N1, and a second electrode of the fourth transistor T4 is coupled with the second data node Data_bar.

[0101] In an example, as shown in FIG. 13, the fourth transistor T4 is a P-type transistor.

[0102] In some examples, as shown in FIG. 14, the latch transmission circuit 6204 comprises a fifth transistor T5 and a sixth transistor T6 in a serial cascade relationship.

[0103] A control electrode of the fifth transistor T5 is coupled with the first data node Data, a first electrode of the fifth transistor T5 data is coupled with the second data node Data_bar, and a second electrode of the fifth transistor T5 is coupled with a first electrode of the sixth transistor T6. A control electrode of the sixth transistor T6 receives the transmission signal rd, and a second electrode of the sixth transistor T6 is coupled with the sense node SO.

[0104] In an example, with continued reference to FIG. 14, the fifth transistor T5 and the sixth transistor T6 are N-type transistors. Considering that a leakage current of an N-type transistor is small, the latch transmission circuit 6204 using an electronic element having an N-type transistor can reduce the risk of a sensitive level change of the sense node SO caused by the leakage current, thus improving data accuracy of the sense latch circuit 6223.

[0105] It may be understood that when the fifth transistor T5 and the sixth transistor T6 are N-type transistors, the effect on actual level magnitudes of the first data node Data and the second data node Data_bar is determined in conjunction with a process of transmitting a level signal of an entire circuit structure of the latch circuit 6223 in the resetting control circuit 6201 and the setting control circuit 6202. For example, as shown in FIG. 12, the third transistor T3 is a P-type transistor. The P-type transistor is turned on under control of a low level (i.e., a control electrode of the P-type transistor is more sensitive to a magnitude of the sensed level signal), and can transfer charges of the first supply node N1 to the first data node Data as much as possible. Similarly, as shown in FIG. 13, the fourth transistor T4 is set to a P-type transistor, which may transfer charges of the first supply node N1 to the second data node Data_bar as much as possible.

[0106] Moreover, in a subsequent read phase of the page buffer 622, a large charge amount of the first data node Data ensures that an on-degree (i.e., a magnitude relationship of a voltage difference between the control electrode and the first electrode and a threshold voltage is characterized as the on-degree of the transistor) of the fifth transistor T5 reaches a target degree (a maximum on-degree based on the threshold voltage of the fifth transistor T5). As such, the fifth transistor T5 transmits the level of the second data node Data_bar to the sense node SO as much as possible when implementing an on-state in response to the level of the first data node Data, which is favorable to improving the sensitivity and accuracy of acquiring a data change of the latch circuit 6223 by the sense node SO.

[0107] In some examples, at least two latch circuits 6223 in the page buffer 622 may share one latch transmission circuit 6204. For example, two latch circuits 6223 share one latch transmission circuit 6204. In this way, the structure of the page buffer 622 occupies less area, further reducing the area of the memory device 60, which is favorable to realizing a high degree of integration and a small size of the memory device 60.

[0108] Based on the structure of the latch circuit 6223 provided in the above examples, as shown in FIG. 15, the latch circuit 6223 comprises six transistors. In conjunction with the structure of the latch 6211 shown in FIG. 7, the number of the transistors in the latch circuit 6223 of the present application is reduced by two, thus reducing the costs of and the space in the memory device 60 occupied by the page buffer 622. A reduction in the number of the transistors of the two phase inverters 6211 reduces a peak current generated when the two phase inverters transmit a signal through a plurality of transistors, thus improving the stability of the signal transmission of the page buffer 622.

[0109] Moreover, while realizing functions of charge and discharge operations on the sense node SO, the stability of the level signal transmission through a line between the latch circuit 6223 and the sense node SO is improved, improving the accuracy of sensing the signal by the sense node SO and thereby improving the performance of the page buffer 622.

[0110] In some examples, as shown in FIG. 16 to FIG. 18, the latch circuit 6223 further comprises a voltage stabilizing circuit 6205. As shown in FIG. 16, the voltage stabilizing circuit 6205 is coupled with the first data node Data and the second data node Data_bar and configured to stabilize a voltage difference between the first data node Data and the second data node Data_bar.

[0111] In an example, as shown in FIG. 17, the voltage stabilizing circuit 6205 comprises a capacitor C1. A first plate of the capacitor C1 is coupled with the first data node Data, and a second plate of the capacitor C2 is coupled with the second data node Data_bar. As such, the capacitor C1 maintains a voltage difference between the first plate and the second plate as being stable under a bootstrap effect thereof, thereby stabilizing the voltage difference between the first data node Data and the second data node Data_bar, so that a voltage difference between the control electrode and the first electrode of the fifth transistor T5 is stable, i.e., ensuring that the signal flowing through the fifth transistor T5 is stable.

[0112] In a further example, as shown in FIG. 18, the voltage stabilizing circuit 6206 comprises a seventh transistor T7. A control electrode of the seventh transistor T7 is coupled with the second data node Data_bar, and a first electrode and a second electrode of the seventh transistor T7 are both coupled with the first data node Data. As such, the first electrode and the second electrode of the seventh transistor T7 are coupled with the same node (i.e., the first data node Data), so that the level of the first data node Data may be maintained as being stable regardless of whether the seventh transistor T7 is turned on or off under control of a level signal of the second data node Data_bar. Accordingly, an on-degree of the first transistor T1 controlled by the level of the first data node Data is stable, and the level of the second data node Data_bar is stable. Therefore, the voltage difference between the control electrode and the first electrode of the fifth transistor T5 is stable, i.e., ensuring that the signal flowing through the fifth transistor T5 is stable.

[0113] For example, the seventh transistor T7 is a P-type transistor. As such, a property of the P-type transistor being turned on under control of a low level signal is taken into consideration. In order to reduce the loss generated by the transmission of the level signal in a circuit signal line, which causes the problem that the level signal received by the control electrode of the transistor fails to turn on the transistor or the on-degree of the transistor is poor (i.e., the magnitude relationship of the voltage difference between the control electrode and the first electrode and the threshold voltage is characterized as the on-degree of the transistor), the P-type transistor is disposed between the first data node Data and the second data node Data_bar, so as to improve the sensitivity of sensing level changes of the first data node Data and the second data node Data_bar and improve a voltage stabilizing effect.

[0114] Furthermore, the voltage stabilizing circuit 6205 may also be a circuit comprising other electronic elements that have a voltage stabilizing effect. In an example, the voltage stabilizing circuit 6205 comprises electronic elements such as a voltage stabilizing diode or a linear regulator (e.g., a low dropout regulator (LDO)). The examples of the present application do not impose limitations thereto.

[0115] For ease of understanding, based on the page buffer 622 having the latch circuit 6223 provided in the above examples, a process of implementing data latch for one latch circuit 6223 and adjusting the potential of the sense node SO are illustrated in an example. It is to be noted that other latch circuits 6223 in the page buffer 622 may perform similar methods for a data setting operation.

[0116] As shown in FIG. 20, the page buffer 622 comprises the bit line control circuit 6221, the bit line discharge circuit 6222, and five latch circuits 6223. The five latch circuits 6223 include a sense latch circuit 6223-1, three data latch circuits 6223-2, 6223-3, and 6223-4, and a cache latch circuit 6223-5.

[0117] The sense node SO is charged via the bit line control circuit 6221, so that the sense node SO has a high level (e.g., a supply voltage VDD). Meanwhile, (an eighth transistor T8 and) the third transistor T3 in FIG. 15 is turned on, so that the supply voltage VDD from a supply voltage end may be provided to the first data node Data of the sense latch circuit 6223-1, that is, data latched by the sense latch circuit 6223-1 is “1”. Alternatively, the fourth transistor T4 in FIG. 15 is turned on, so that a ground voltage VSS may be provided to the first data node Data of the sense latch circuit 6223-1, that is, data latched by the sense latch circuit 6223-1 is “0”.

[0118] It is to be noted that the data “1” may represent a high level or a low level, and the data “0” may represent a low level or a high level. In the examples of the present application, the illustration is performed by taking the data “1” representing the high level and the data “0” representing the low level as an example.

[0119] The sense latch circuit 6223-1 receives the enabled transmission signal rd (for example, the rd signal is a low level signal), and the latch transmission circuit 6204 in the sense latch circuit 6223-1 is turned on. If data stored in the sense latch circuit 6223-1 is “1”, a high voltage on the sense node SO may be discharged to a low voltage through the latch transmission circuit 6204. If the data stored in the sense latch circuit 6223-1 is “0”, the latch transmission circuit 6204 in the sense latch circuit 6223-1 is cut off, the high voltage on the sense node SO cannot be discharged through the latch transmission circuit 6204, and the voltage on the sense node SO is still the high voltage.

[0120] Therefore, data information stored in the sense latch circuit 6223-1 may be obtained by sensing the voltage at the sense node SO at this time. Similarly, data information stored in the respective latch circuits 6223 may be sensed using the various latch circuits 6223.

[0121] Furthermore, with continued reference to FIG. 20, the page buffer 622 further comprises a data setting circuit 6224. The data setting circuit 6224 is a force setting circuit, that is, when the data setting signal rst_sa_latch is enabled (for example, the rst_sa_latch signal is a low level signal), regardless of a magnitude of the voltage of the sense node SO at this time, data setting may be performed on the designated latch circuit 6223.

[0122] In an example, as shown in FIG. 20, the data setting circuit 6224 comprises the eighth transistor T8. A control electrode of the eighth transistor T8 is configured to receive the data setting signal rst_sa_latch; a first electrode of the eighth transistor T8 is coupled with the latch circuit 6223; and a second electrode of the eighth transistor T8 is coupled with the supply voltage VDD.

[0123] The eighth transistor T8 includes, but is not limited to, a P-type transistor or an N-type transistor. In the examples of the present application, the illustration is performed by taking the eighth transistor T8 being the P-type transistor as an example.

[0124] In the examples of the present application, prior to enabling the page buffer 622, a data set or reset operation may be performed on one or more of the latch circuits 6223 in the page buffer 622 using the data setting circuit 6224. For example, the binary data “0” may be used to represent a reset operation, and “1” may represent a set operation.

[0125] In some examples, the peripheral circuit 62 further comprises a control logic circuit (not shown in FIG. 20). The control logic circuit is coupled with the data setting circuit 6224 of the page buffer 622 and configured to generate the data setting signal rst_sa_latch. For example, the control logic unit 625 shown in FIG. 5 comprises the control logic circuit.

[0126] The control logic circuit may be further configured to generate various control signals required by the page buffer 100, including, but not limited to, the data setting signal rst_sa_latch.

[0127] On the other hand, based on the page buffer 622 provided in any of the above examples (referring to FIG. 8 to FIG. 20), as shown in FIG. 22 and FIG. 23, the examples of the present application further provide an operation method of the page buffer 622. In conjunction with FIG. 19, FIG. 20, FIG. 21A, and FIG. 21B, the operation method of the page buffer 622 is illustrated in an example. The circuit structure shown in FIG. 15 is taken as an example of the latch circuit 6223 of the page buffer 622. The operation method of the page buffer 622 of the present application does not limit all of the latch circuits 6223 as being the circuit structure shown in FIG. 15, for example, the latch circuits 6223 may also include a circuit structure of the voltage stabilizing circuit 6205 as shown in FIG. 16 to FIG. 18.

[0128] As shown in FIG. 19, the page buffer 622 comprises the bit line control circuit 6221, the bit line discharge circuit 6222, and the plurality of latch circuits 6223.

[0129] The bit line control circuit 6221 is coupled with the first supply voltage node N1 (e.g. the transmission supply voltage VDD), the bit line BL, and the sense node SO, and is configured to control the potential level of the sense node SO during the sense operation based on the current level of the bit line BL.

[0130] In an example, the bit line control circuit 6221 may set the voltage at the sense node SO through the data latched in the sense latch circuit 6223, and may also set the voltage at the sense node SO directly in response to level signals of a Prech_all_en end and a Prech_sel_en end based on the supply voltage VDD provided by the first supply voltage node N1. For example, when the signals transmitted at the Prech_all_en end and the Prech_sel_en end are enabled at the same time, the supply voltage (e.g., VDD) may be applied to the sense node SO through the bit line control circuit 6221.

[0131] During a process of programming the memory cell, a program inhibit bit line voltage (e.g., VDD) or a normal program bit line voltage (e.g., VSS) may be applied to the bit line BL coupled with the memory cell via the bit line control circuit 6221. In an example, a high level is applied to the bit line through a charge function of the bit line control circuit 6221 to achieve an effect of inhibiting the program, or the bit line is discharged through a discharge function of the bit line control circuit 6221, so that the voltage of the bit line is pulled down to the ground voltage to achieve an effect of allowing the program. The normal program bit line voltage<the program inhibit bit line voltage.

[0132] The bit line discharge circuit 6222 is coupled between the bit line BL and the second supply voltage node N2 (e.g., the transmission ground voltage GND) and is configured to discharge the potential level of the bit line BL in response to the discharge control signal prech_all_en.

[0133] In an example, the bit line discharge circuit 6222 may be a combination of a plurality of N-type transistors and/or P-type transistors. Alternatively, the bit line discharge circuit 6222 comprises components that may be used for clamping or regulating voltages, e.g., one or more components among a Zener diode, a transient voltage suppressor, and a piezoresistor, etc. In an example, the bit line discharge circuit 6222 may generate different bit line force voltages based on different electronic components. For example, a first bit line force voltage and a second bit line force voltage. The normal program bit line voltage<the first bit line force voltage<the second bit line force voltage<the program inhibit bit line voltage.

[0134] As such, fine program of the memory cell can be achieved by applying the different bit line force voltages to the bit line BL using the bit line discharge circuit 6222, such that a target threshold voltage distribution is narrower, increasing a read window between the memory cells in different programmed states and thus ensuring accurate data read.

[0135] The plurality of latch circuits 6223 are coupled with the sense node SO, and charge and discharge the level of the sense node SO under driving of the bit line control circuit 6221 and the bit line discharge circuit 6222. As shown in FIG. 10, each latch circuit 6223 comprises the resetting control circuit 6201 coupled with the first data node Data, the setting control circuit 6202 coupled with the second data node Data_bar, the data transmission circuit 6203 coupled with both the first data node Data and the second data node Data_bar, and the latch transmission circuit 6204 coupled with the first data node Data, the second data node Data_bar, and the sense node SO.

[0136] In some examples, as shown in FIG. 19, in the bit line control circuit 6221, when the signal prech_sel_en and the signal prech_all_en are enabled at the same time, the supply voltage (e.g., VDD) may be applied to the sense node SO directly.

[0137] At this time, as shown in FIG. 15, the level of the second data node Data_bar is the high level, and the level of the first data node Data is the low level. As such, under a joint action of the first transistor T1 and the second transistor T2 in the latch circuit 6223 (that is, the fifth transistor T5 is turned off), the latch circuit 6223 does not discharge the level of the sense node SO. The level of the sense node SO is the supply voltage VDD applied by the bit line control circuit 6221.

[0138] Accordingly, as shown in FIG. 19, when the bit line control circuit 6221 couples the bit line BL and the sense node SO in response to a signal vbias and a signal vsoblk being both enabled, the bit line BL acquires the data stored in the latch circuit 6223 by reading the level of the sense node SO. For example, the level of the sense node SO is unchanged. Data read by the bit line BL is “1”, and then it may be deduced that the data latched by the latch circuit 6223 is “1”.

[0139] Alternatively, with continued reference to FIG. 19, when the signal prech_sel_en is in the enabled state and the signal prech_all_en is not in the enabled state, the bit line control circuit 6221 applies the supply voltage (VDD) to the sense node SO in response to the signal transmitted by the latch circuit 6223.

[0140] At this time, as shown in FIG. 15, the level of the second data node Data_bar is the low level, and the level of the first data node Data is the high level. Under a joint action of the first transistor T1 and the second transistor T2 in the latch circuit 6223 (that is, the fifth transistor T5 is turned on), in response to the signal rd being enabled, the latch circuit 6223 is coupled with the sense node SO to discharge the level of the sense node SO. That is, the level of sense node SO is discharged from the supply voltage VDD. In this way, when the signal vbias and the signal vsoblk are enabled at the same time, the level signal of the sense node SO is fed back to the bit line BL. The bit line BL acquires the data stored in the latch circuit 6223 by reading the level of the sense node SO. For example, the level of the sense node SO is changed. Data read by the bit line BL is “0”, and then it may be deduced that the data latched by the latch circuit 6223 is “1”.

[0141] In order to reflect a driving process of the latch circuit 6223 of the page buffer 622 more clearly, the above operations are described in detail below in conjunction with timing diagrams shown in FIG. 21A and FIG. 21B, taking the latch circuit 6223 shown in FIG. 15 as an example.

[0142] As shown in FIG. 15, the latch circuit 6223 comprises the resetting control circuit 6201, the setting control circuit 6202, the data transmission circuit 6203, and the latch transmission circuit 6204.

[0143] The resetting control circuit 6201 comprises the third transistor T3. The third transistor T3 is a P-type transistor.

[0144] The setting control circuit 6202 comprises the fourth transistor T4. The fourth transistor T4 is a P-type transistor.

[0145] The data transmission circuit 6203 comprises the first transistor T1 and the second transistor T2. The first transistor T1 and the second transistor T2 are both N-type transistors.

[0146] The latch transmission circuit 6204 comprises the fifth transistor T5 and the sixth transistor T6 connected in series. The fifth transistor T5 and the sixth transistor T6 are both N-type transistors.

[0147] On that basis, as shown in FIG. 22 and FIG. 23, the operation method comprises at least S100, S200, S300, and S400. As shown in FIG. 21A and FIG. 21B, an operation process of the page buffer 622 comprises three phases: a setting phase P-SET, a reset phase P-RST, and a read phase P-RD. Moreover, the timing diagrams provided by FIG. 21A and FIG. 21B only represent example signals employed during the driving process of the latch circuit 6223. The different phases may be spaced apart by a certain time interval or may be adjacent to each other, and the present application do not impose limitations in this respect.

[0148] Meanwhile, the latch circuit 6223 has a characteristic, that is, in different phases, the latch circuit 6223 causes logic levels of the first data node Data and the second data node Data_bar coupled with the latch transmission circuit 6204 to be opposite, in response to configuration signals of the opposite logic levels (for example, the setting signal set and the reset signal rst have opposite logic levels in the same phase).

[0149] For example, as shown in FIG. 21A, a phase prior to the read phase P-RD may be the reset phase P-RST, and the logic levels of the first data node Data and the second data node Data_bar obtained in the reset phase P-RST are a group of target levels. Based on the characteristic of the latch circuit 6223, a process that causes the logic levels of the first data node Data and the second data node Data_bar to be opposite to the group of target levels is necessarily present prior to the reset phase P-RST (e.g., the setting phase P-SET).

[0150] Alternatively, as shown in FIG. 21B, a phase prior to the read phase P-RD may be the setting phase P-SET, and the logic levels of the first data node Data and the second data node Data_bar obtained in the setting phase P-SET are a group of target levels. Based on the characteristic of the latch circuit 6223, a process that causes the logic levels of the first data node Data and the second data node Data_bar to be opposite to the group of target levels is necessarily present prior to the setting phase P-SET (e.g., the reset phase P-RST).

[0151] Moreover, states of the plurality of latch circuits 6223 in different page buffers 622 may be the same or different, for example, part of the latch circuits 6223 perform data write operations, and the other part of the latch circuits 6223 perform active data transmission operations. That is, data latched in a phase (the setting phase P-SET or the reset phase P-RST) prior to a current state of the latch circuit 6223 is read in the read phase P-RD. In this way, if the different latch circuits 6223 transmit different signals in the same time period, different pieces of data are read in the read phase P-RD.

[0152] Thus, as shown in FIG. 21A and FIG. 21B, two sequential orders of the setting phase P-SET and the reset phase P-RST are reflected in the same timing process.

[0153] In order to clearly distinguish different operation methods of acquiring data in read phases P-RD of the different latch circuits 6223, the illustration is performed by taking the two operation methods shown in FIG. 21A and FIG. 22 as well as FIG. 21B and FIG. 23 as an example.

[0154] In some examples, as shown in FIG. 21A and FIG. 22, the operation process of the page buffer 622 comprises the setting phase P-SET, the reset phase P-RST following the setting phase P-SET, and the read phase P-RD following the reset phase P-RST.

[0155] In an example, as shown in FIG. 15, FIG. 21A, and FIG. 22, the operation method comprises S300, S100, and S200.

[0156] S300: In the setting phase P-SET, the setting control circuit 6202 sets the first data node Data and the second data node Data_bar to the second logic level and the first logic level respectively in response to the enabled state of the setting signal set. The first logic level is higher than the second logic level.

[0157] In an example, with continued reference to FIG. 15 and FIG. 21A, a precharge operation is performed on the sense node SO such that the sense node SO has the first logic level. For example, the first logic level is VDD.

[0158] The fourth transistor T4 of the setting control circuit 6202 is turned on in response to the signal set being in the enabled state, so as to couple the first supply voltage node N1 with the second data node Data_bar, so that the first logic level is transmitted to the control electrode of the second transistor T2 in the data transmission circuit 6203. The second transistor T2 is turned on to transmit the second logic level (e.g., VSS) of the second supply voltage node N2 to the first data node Data. The first logic level VDD is higher than the second logic level VSS.

[0159] At this time, the third transistor T3 of the resetting control circuit 6201 is turned off in response to the reset signal rst being in a disabled state, and the level of the first data node Data is maintained at the second logic level.

[0160] Meanwhile, the first transistor T1 in the data transmission circuit 6203 is turned off in response to the second logic level of the first data node Data, and the level of the second data node Data_bar is maintained at the first logic level.

[0161] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned off in response to the second logic level signal of the first data node Data. The latch circuit 6223 is disconnected from the sense node SO, and the sense node SO is maintained at the first logic level.

[0162] S100: In the reset phase P-RST, the resetting control circuit 6201 initializes the first data node Data and the second data node Data_bar to the first logic level and the second logic level respectively in response to the enabled state of the reset signal rst.

[0163] In an example, with continued reference to FIG. 15 and FIG. 21A, in the resetting control circuit 6201, in response to the enabled state of the reset signal rst (for example, the reset signal rst is a low level signal), the third transistor T3 of the resetting control circuit 6201 is turned on to transmit the level of the first supply voltage node N1 to the first data node Data, so that the level of the first data node Data is set to the first logic level.

[0164] The first transistor T1 of the data transmission circuit 6203 is turned on in response to the first logic level (e.g., VDD) of the first data node Data, so as to transmit the level of the second supply voltage node N2 to the second data node Data_bar, so that the level of the second data node Data_bar is set to the second logic level (e.g., VSS). The first logic level is higher than the second logic level.

[0165] Meanwhile, the fourth transistor T4 of the setting control circuit 6202 is turned off in response to the setting signal set being in a disabled state (the setting signal set is at the high level), and the level of the second data node Data_bar is maintained at the second logic level.

[0166] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned on in response to the first logic level of the first data node Data. However, since the sixth transistor T6 is turned off in response to the transmission signal rd being in a disabled state (e.g., the transmission signal rd is at the low level), the latch circuit 6223 is disconnected from the sense node SO, and the sense node SO is maintained at the first logic level.

[0167] Based on the above operation process, the level of the sense node SO is the first logic level. A program operation is performed on the latch circuit 6223 via the bit line BL, and the latch circuit 6223 latches target data. Data set in the reset phase P-RST is read in the subsequent read phase P-RD.

[0168] S200: In the read phase P-RD following the reset phase P-RST where the sense node SO is at the first logic level, the latch transmission circuit 6204 couples the second data node Data_bar with the sense node SO in response to the transmission signal rd being in the enabled state, so as to transmit the second logic level of the second data node Data_bar to the sense node SO. The sense node SO changes from the first logic level to the second logic level.

[0169] In an example, with continued reference to FIG. 15 and FIG. 21A, after S100, the first data node Data has the second logic level, and the second data node Data_bar has the first logic level. The fifth transistor T5 of the latch transmission circuit 6204 is turned on in response to the first logic level of the first data node Data, and the sixth transistor T6 is turned on in response to the transmission signal rd, so as to couple the second data node Data_bar with the sense node SO. Therefore, the second logic level of the second data node Data_bar is transmitted to the sense node SO.

[0170] As such, the sense node SO changes from the first logic level to the second logic level. That is, the bit line BL reads the data of the latch circuit 6223 through a level change of the sense node SO. Accordingly, the read data can be latched to other latch circuits 6223 via the bit line BL.

[0171] In some other examples, as shown in FIG. 21B and FIG. 23, the operation process of the page buffer 622 comprises the reset phase P-RST, the setting phase P-SET following the reset phase P-RST, and the read phase P-RD following the setting phase P-SET.

[0172] In an example, as shown in FIG. 15, FIG. 21B, and FIG. 23, the operation method comprises S100, S300, and S400.

[0173] S100: In the reset phase P-RST, the resetting control circuit 6201 initializes the first data node Data and the second data node Data_bar to the first logic level and the second logic level respectively in response to the enabled state of the reset signal rst.

[0174] In an example, first, the precharge operation is performed on the sense node SO such that the sense node SO has the first logic level. For example, the first logic level is VDD.

[0175] With continued reference to FIG. 15 and FIG. 21B, in the resetting control circuit 6201, in response to the enabled state of the reset signal rst, the third transistor T3 of the resetting control circuit 6201 is turned on to transmit the level of the first supply voltage node N1 to the first data node Data, so that the level of the first data node Data is set to the first logic level.

[0176] The first transistor T1 of the data transmission circuit 6203 is turned on in response to the first logic level of the first data node Data, so as to transmit the level of the second supply voltage node N2 to the second data node Data_bar, so that the level of the second data node Data_bar is set to the second logic level. The first logic level is higher than the second logic level. For example, the first logic level is VDD, and the second logic level is VSS.

[0177] Meanwhile, the fourth transistor T4 of the setting control circuit 6202 is turned off in response to the setting signal set being in the disabled state, and the level of the second data node Data_bar is maintained at the second logic level.

[0178] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned on in response to the first logic level of the first data node Data. However, since the sixth transistor T6 is turned off in response to the transmission signal rd being in the disabled state, the latch circuit 6223 is disconnected from the sense node SO, the level of the sense node SO is not pulled down, and the sense node SO is maintained at the first logic level.

[0179] S300: In the setting phase P-SET, the setting control circuit 6202 sets the first data node Data and the second data node Data_bar to the second logic level and the first logic level respectively in response to the enabled state of the setting signal set.

[0180] In an example, with continued reference to FIG. 15 and FIG. 21B, the fourth transistor T4 of the setting control circuit 6202 is turned on in response to the signal set being in the enabled state, so as to couple the first supply voltage node N1 with the second data node Data_bar, so that the first logic level is transmitted to the control electrode of the second transistor T2 in the data transmission circuit 6203. The second transistor T2 is turned on to transmit the second logic level of the second supply voltage node N2 to the first data node Data. For example, the second logic level is VSS. The first logic level VDD is higher than the second logic level VSS.

[0181] At this time, the third transistor T3 of the resetting control circuit 6201 is turned off in response to the reset signal rst being in the disabled state, and the level of the first data node Data is maintained at the second logic level. Meanwhile, the first transistor T1 in the data transmission circuit 6203 is turned off in response to the second logic level of the first data node Data, and the level of the second data node Data_bar is maintained at the first logic level.

[0182] In this way, the fifth transistor T5 of the latch transmission circuit 6204 is turned off in response to the second logic level signal of the first data node Data. The latch circuit 6223 is disconnected from the sense node SO, and the sense node SO is maintained at the first logic level.

[0183] Based on the above operation process, the level of the sense node SO is the first logic level. A program operation is performed on the latch circuit 6223 via the bit line BL, and the latch circuit 6223 latches target data. Data set in the setting phase P-SET is read in the subsequent read phase P-RD.

[0184] S400: In the read phase P-RD following the setting phase P-SET where the sense node SO is at the first logic level, the latch transmission circuit 6204 disconnects the second data node Data_bar from the sense node SO, so that the level of the sense node SO is maintained at the first logic level.

[0185] In an example, with continued reference to FIG. 15 and FIG. 21B, after S300, the first data node Data has the second logic level, and the second data node Data_bar has the first logic level. The fifth transistor T5 of the latch transmission circuit 6204 is turned off in response to the second logic level signal of the first data node Data.

[0186] On that basis, regardless of whether the transmission signal rd is in the enabled state (that is, if the signal rd is a high level signal, the sixth transistor T6 is turned off; or if the signal rd is a low level signal, the sixth transistor T6 is in an on state), the second data node Data_bar is disconnected from the sense node SO, so that the level of the sense node SO is maintained at the first logic level. As such, the bit line BL reads the data of the latch circuit 6223 continuously through the sense node SO.

[0187] The operation method of the page buffer 622 provided by the present application comprises two flows as shown in FIG. 22 and FIG. 23. One is based on the level signals stored at the first data node Data and the second data node Data_bar in the reset phase P-RST, wherein the latch transmission circuit 6204 is connected with the sense node SO in the read phase P-RD via the enabled state of the transmission signal rd, so that the level of the sense node SO is changed. The other one is based on the level signals stored at the first data node Data and the second data node Data_bar in the setting phase P-SET, wherein the latch transmission circuit 6202 is disconnected from the sense node SO in the read phase P-RD even in the case of a response to the enabled state of the transmission signal rd, so that the level of the sense node SO is maintained. The two flows are based on a plurality of latch circuits of different page buffers, and different latch circuits may be in different states in the same time period, which is characterized in that the operation process of the page buffer 622 may be, during the read phase P-RD, reading data stored in the setting phase P-SET or reading data stored in the reset phase P-RST. In this way, during the read phase P-RD, the latch circuits 6223 of the different page buffers 622 affect the level of the sense node SO differently, thereby acquiring different pieces of data of the different page buffers 622 through the sense node SO. The circuit structure of the page buffer 622 provided by the present application can achieve data read of the memory cells in different states.

[0188] In view of above, examples of the present application provide a page buffer and an operation method thereof, a memory device, and a memory system.

[0189] In a first aspect, examples of the present application provide a page buffer. The page buffer comprises a plurality of latch circuits. Each of the latch circuits comprises a resetting control circuit, a setting control circuit, a data transmission circuit, and a latch transmission circuit. The resetting control circuit is coupled to a first data node and configured to receive a first supply voltage, so as to determine a potential of the first data node. The setting control circuit is coupled to a second data node and configured to receive the first supply voltage, so as to determine a potential of the second data node. The data transmission circuit is coupled to the first data node and the second data node and configured to receive a second supply voltage. The latch transmission circuit is coupled to the first data node, the second data node, and a sense node. The first supply voltage is higher than the second supply voltage.

[0190] In some examples, the setting control circuit is configured to set the second data node and the first data node to a first logic level and a second logic level respectively in response to a setting signal being in an enabled state, wherein the first logic level is higher than the second logic level.

[0191] The resetting control circuit is configured to set the first data node and the second data node to the first logic level and the second logic level respectively in response to a reset signal being in an enabled state.

[0192] The latch transmission circuit is configured to couple the second data node with the sense node in response to a transmission signal being in an enabled state and the first data node and the second data node being at the first logic level and the second logic level respectively, wherein the sense node is at the second logic level.

[0193] In some examples, the latch transmission circuit is further configured to, when the sense node is at the first logic level, maintain the sense node at the first logic level in response to the transmission signal being in the enabled state and the first data node and the second data node being at the second logic level and the first logic level respectively.

[0194] In some examples, the data transmission circuit comprises a first transistor and a second transistor. A control electrode of the first transistor is coupled with the first data node, a first electrode of the first transistor is coupled with a second supply voltage node, and a second electrode of the first transistor is coupled with the second data node. A control electrode of the second transistor is coupled with the second data node, a first electrode of the second transistor is coupled with a second supply voltage node, and a second electrode of the second transistor is coupled with the first data node.

[0195] In some examples, the resetting control circuit comprises a third transistor, a control electrode of the third transistor receives the reset signal, a first electrode of the third transistor is coupled with a first supply voltage node, and a second electrode of the third transistor is coupled with the first data node.

[0196] The setting control circuit comprises a fourth transistor, a control electrode of the fourth transistor receives the setting signal, a first electrode of the fourth transistor is coupled with the first supply voltage node, and a second electrode of the fourth transistor is coupled with the second data node.

[0197] In some examples, the latch transmission circuit comprises a fifth transistor and a sixth transistor in a serial cascade relationship; and the fifth transistor and the sixth transistor are N-type transistors.

[0198] In some examples, a control electrode of the fifth transistor is coupled with the first data node, a first electrode of the fifth transistor is coupled with the second data node, and a second electrode of the fifth transistor is coupled with a first electrode of the sixth transistor. A control electrode of the sixth transistor receives the transmission signal, and a second electrode of the sixth transistor is coupled with the sense node.

[0199] In some examples, the latch circuit further comprises a voltage stabilizing circuit. The voltage stabilizing circuit is coupled with the first data node and the second data node and configured to stabilize a voltage difference between the first data node and the second data node.

[0200] In some examples, the voltage stabilizing circuit comprises a capacitor. A first plate of the capacitor is coupled with the first data node, and a second plate of the capacitor is coupled with the second data node.

[0201] In some example, the voltage stabilizing circuit comprises a seventh transistor. A control electrode of the seventh transistor is coupled with the second data node, and a first electrode and a second electrode of the seventh transistor are both coupled with the first data node.

[0202] In some examples, the page buffer further comprises a bit line control circuit and a bit line discharge circuit. The bit line control circuit is coupled with a first supply voltage node, a bit line, and the sense node and configured to control a potential level of the sense node during a sense operation based on a current level of the bit line. The bit line discharge circuit is coupled between the bit line and a second supply voltage node and configured to discharge a potential level of the bit line in response to a discharge control signal.

[0203] The present application couples the first data node and the second data node via the latch transmission circuit in the page buffer. As such, without coupling the latch transmission circuit with a ground voltage node, the latch transmission circuit is controlled to be connected with or disconnected from the sense node based solely on logic levels of the first data node Data and the second data node Data_bar obtained under a joint action of the data transmission circuit 6203, the setting circuit 6202, and the resetting control circuit 6201, thus reducing grounding line structures. Moreover, the number of electronic elements (e.g., transistors) is also reduced due to not directly using phase inverters, thereby reducing fabrication costs of and a space in a memory device occupied by the page buffer. In the case where the memory device comprises a page buffer group or comprises page buffers for driving a multi level cell type, the fabrication costs of and the space occupied by the page buffer may be reduced significantly.

[0204] Moreover, due to the simplified circuit structure, the complexity of a signal transmission path between the page buffer and the sense node is reduced, a loss during transmission of the level signal is reduced, and thus the overall performance of the memory device is improved.

[0205] In another aspect, the present application provides a memory device. The memory device comprises a memory cell array and a plurality of page buffers provided in any of the above examples. The memory cell array is coupled with a plurality of bit lines. Each of the page buffers is coupled with one of the bit lines and configured to perform a sense operation based on a current level of the bit line.

[0206] The memory device provided in this example achieves the same beneficial effect as the beneficial effect of the page buffer provided in any of the above examples, which is no longer repeated here.

[0207] In further another aspect, the present application provides a memory system. The memory system comprises one or more memory devices provided in any of the above examples and a memory controller. The memory controller is coupled with the memory devices and configured to control the memory devices.

[0208] The memory system provided in this example achieves the same beneficial effect as the beneficial effect of the memory device provided in any of the above examples, which is no longer repeated here.

[0209] In yet another aspect, the present application provides an operation method of a page buffer. The page buffer comprises a plurality of latch circuits, each comprising a resetting control circuit coupled with a first data node, a setting control circuit coupled with a second data node, and a data transmission circuit coupled with both the first data node and the second data node; and a latch transmission circuit coupled with the first data node, the second data node, and a sense node.

[0210] The operation method comprises:

• • [0211] in a reset phase, setting a reset signal to an enabled state, and setting, by the resetting control circuit, the first data node and the second data node to a first logic level and a second logic level respectively in response to the enabled state of the reset signal, wherein the first logic level is higher than the second logic level; and
  • [0212] in a read phase following the reset phase where the sense node is at the first logic level, setting a transmission signal to an enabled state, and coupling, by the latch transmission circuit, the second data node with the sense node in response to the transmission signal being in the enabled state, so that the sense node changes from the first logic level to the second logic level.

[0213] In some examples, the operation method further comprises:

• • [0214] in a setting phase, setting a setting signal to an enabled state, and setting, by the setting control circuit, the first data node and the second data node to the second logic level and the first logic level respectively in response to the enabled state of the setting signal; and
  • [0215] in a read phase following the setting phase where the sense node is at the first logic level, disconnecting, by the latch transmission circuit, the second data node from the sense node to maintain the level of the sense node at the first logic level.

[0216] The operation method of the page buffer provided by the present application comprises two flows. One is based on the level signals stored at the first data node and the second data node in the reset phase, wherein the second data node is coupled with the sense node in the read phase via the enabled state of the transmission signal, so that the level of the sense node is changed. The other one is based on the level signals stored at the first data node and the second data node in the setting phase, wherein the second data node is disconnected from the sense node in the read phase even in the case of a response to the enabled state of the transmission signal, so that the level of the sense node is maintained. The two flows are based on a plurality of latch circuits included in different page buffers, and different latch circuits may be in different states in the same time period, which is characterized in that the operation process of the page buffer may be, during the read phase, reading data stored in the setting phase or reading data stored in the reset phase. In this way, during the read phase, the latch circuits of the different page buffers affect the level of the sense node differently, thereby acquiring different pieces of data of the different page buffers through the sense node. The circuit structure of the page buffer provided by the present application can achieve data read of memory cells in different states.

[0217] It is to be understood that, references to “some implementations” or “some examples” throughout this specification mean that particular features, structures, or characteristics related to the examples are included in at least one example of the present application. Therefore, “in some examples” or “in an example” presented everywhere throughout this specification does not necessarily refer to the same example. Furthermore, these particular features, structures, or characteristics may be incorporated in one or more examples in any suitable manner. It is to be understood that, in various examples of the present application, sequence numbers of the above processes do not indicate an execution sequence, and an execution sequence of various processes shall be determined by functionalities and intrinsic logics thereof, and shall constitute no limitation on an implementation process of the examples of the present application. The above sequence numbers of the examples of the present application are only for description, and do not represent advantageous and disadvantageous of the examples.

[0218] It is to be noted that, the terms “comprise”, “include” or any variants thereof herein are intended to cover non-exclusive inclusion, such that a process, a method, an article or a device comprising a series of elements comprise not only those elements, but also other elements not listed explicitly, or elements inherent to this process, method, article or device. An element defined by a statement “comprising one . . . ” without more limitations do not preclude the presence of another identical element in the process, method, article or device comprising this element.

[0219] The above descriptions are merely implementations of the present application, but the protection scope of the present application is not limited to these. Any variation or replacement readily figured out by those skilled in the art within the technical scope as disclosed by the present application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.