Solar cell and preparation method therefor

[0001] This application is a U.S. National Stage of PCT International Application No. PCT/CN2023/100575 filed on Jun. 16, 2023, which claims priority to Chinese Patent Application No. 2022114796707, filed on Nov. 24, 2022, entitled “SOLAR CELL AND PREPARATION METHOD THEREFOR”, the content of each of which is hereby incorporated by reference in its entirety.

[0002] The present application relates to the technical field of solar cell production, and in particular to a solar cell and a method for preparing the same.

[0003] N-type single crystal interdigitated back contact (IBC) solar cells usually form a heavily-doped emitter and a heavily-doped back field region on a back surface of its silicon wafer using a diffusion process, thereby effectively solving the problem of light blocking by metal grid lines and thus significantly increasing short-circuit current density.

[0004] Compared with conventional crystalline silicon solar cells, the N-type single crystal IBC solar cells possess the following advantages in actual outdoor photovoltaic power stations and system applications: 1. high photoelectric conversion efficiency; 2. no light-induced degradation (LID) and high stability; 3. good weak light response and low temperature coefficient; 4. a beautiful appearance, no grid line blocking on the front surface, being more beautiful than appearance of conventional components, and can being widely used in photovoltaic building integration; and 5. long service life.

[0005] However, the process for preparing the N-type single crystal IBC solar cell is relatively complex, with high technical barrier and high preparation cost, and thus is an important factor restricting the mass production of N-type single crystal IBC solar cells. Therefore, how to simplify the process for preparing the N-type single crystal IBC solar cell and reduce the preparation cost is an important research direction in this field.

[0006] Accordingly, it is necessary to provide a solar cell and a method for preparing the same, in which the preparation method is relatively simple and has a low production cost.

[0007] According to an aspect of the present application, a method for preparing a solar cell is provided. The method includes the following steps:

• • [0008] forming a first silicon oxide layer, an intrinsic amorphous silicon layer, a phosphosilicate glass layer and a second silicon oxide layer sequentially on a back surface of an n-type silicon substrate;
  • [0009] removing the phosphosilicate glass layer and the second silicon oxide layer on a partial region of the back surface of the n-type silicon substrate;
  • [0010] performing boron diffusion on the back surface of the n-type silicon substrate, so that the intrinsic amorphous silicon layer in a region where the phosphosilicate glass layer and the second silicon oxide layer are removed is converted into a boron-doped polysilicon layer, and the intrinsic amorphous silicon layer in a region where the phosphosilicate glass layer and the second silicon oxide layer are not removed is converted into a phosphorus-doped polysilicon layer;
  • [0011] forming an isolation groove at a boundary between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer; and
  • [0012] preparing a first electrode connected to the boron-doped polysilicon layer and a second electrode connected to the phosphorus-doped polysilicon layer.

[0013] In any embodiment, performing boron diffusion on the back surface of the n-type silicon substrate includes the following step:

• • [0014] performing a diffusion treatment on the back surface of the n-type silicon substrate using a boron source at a temperature ranging from 900° C. to 1050° C. for 1 h to 3 h.

[0015] In any embodiment, the boron source is one or more selected from BCl₃ or BBr₃.

[0016] In any embodiment, a volume proportion of the boron source in an atmosphere during the boron diffusion is 5% to 30%.

[0017] In any embodiment, removing the phosphosilicate glass layer and the second silicon oxide layer in the partial region of the back surface of the n-type silicon substrate includes the following steps:

• • [0018] forming a patterned blocking layer in a partial region of a surface of the second silicon oxide layer;
  • [0019] removing the phosphorosilicate glass layer and the second silicon oxide layer with a solution containing hydrogen fluoride in a region of the back surface of the n-type silicon substrate where the patterned blocking layer is not formed; and
  • [0020] removing the patterned blocking layer.

[0021] In any embodiment, the patterned blocking layer is a waxy resin material.

[0022] In any embodiment, the patterned blocking layer is removed with an alkali solution containing hydrogen peroxide.

[0023] In any embodiment, forming the isolation groove at the boundary between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer includes the following step:

• • [0024] performing laser grooving at the boundary between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer, and etching a laser-formed groove with an alkali solution.

[0025] In any embodiment, after forming the isolation groove and prior to preparing the first electrode and the second electrode, the method further includes a step of removing a wrap-around layer on a front surface of the n-type silicon substrate.

[0026] In any embodiment, after forming the isolation groove and prior to removing the wrap-around layer on the front surface of the n-type silicon substrate, the method further includes a step of forming a third silicon oxide layer in the isolation groove.

[0027] In any embodiment, after removing the wrap-around layer on the front surface of the n-type silicon substrate and prior to preparing the first electrode and the second electrode. the method further includes a step of performing a texturing process on the front surface of the n-type silicon substrate and cleaning the n-type silicon substrate with a mixed solution of hydrofluoric acid and hydrochloric acid.

[0028] In any embodiment, after cleaning the n-type silicon substrate and prior to preparing the first electrode and the second electrode, the method further includes a step of forming aluminum oxide layers on the front surface and the back surface of the n-type silicon substrate, respectively.

[0029] In any embodiment, after forming the aluminum oxide layer and prior to preparing the first electrode and the second electrode, the method further includes a step of forming passivation and anti-reflection layers on the aluminum oxide layers on the front surface and the back surface of the n-type silicon substrate respectively.

[0030] In any embodiment, after forming the passivation and anti-reflection layer and prior to preparing the first electrode and the second electrode, the method further includes forming openings in the passivation and anti-reflection layer on the back surface of the n-type silicon substrate to form a first electrode contact hole which is communicated with the boron-doped polysilicon layer and a second electrode contact hole which is communicated with the phosphorus-doped polysilicon layer.

[0031] In any embodiment, the first electrode is prepared in the first electrode contact hole by screen printing; and the second electrode is prepared in the second electrode contact hole by screen printing.

[0032] According to another aspect of the present application, a solar cell is provided. The solar cell is prepared by the method for preparing the solar cell in the present application described above.

[0033] According to another aspect of the present application, a solar cell is provided. The solar cell includes an n-type silicon substrate, a first silicon oxide layer, a boron-doped polysilicon layer, a phosphorus-doped polysilicon layer, an aluminum oxide layer, a passivation and anti-reflection layer, a first electrode, and a second electrode. The first silicon oxide layer is disposed on a back surface of the n-type silicon substrate. The boron-doped polysilicon layer is disposed on the first silicon oxide layer. The phosphorus-doped polysilicon layer is disposed on the first silicon oxide layer and is separated from the boron-doped polysilicon layer by an isolation groove. The aluminum oxide layer is disposed on a front surface of the n-type silicon substrate, on the boron-doped polysilicon layer, on the phosphorus-doped polysilicon layer and in the isolation groove. The passivation and anti-reflection layer is disposed on the aluminum oxide layer. The first electrode extends through the passivation and anti-reflection layer and the aluminum oxide layer on the back surface of the n-type silicon substrate and is connected to the boron-doped polysilicon layer. The second electrode extends through the passivation and anti-reflection layer and the aluminum oxide layer on the back surface of the n-type silicon substrate and is connected to the phosphorus-doped polysilicon layer.

[0034] According to the preparation method of the present application, through removing the phosphosilicate glass layer and the second silicon oxide layer in the partial region of the back surface of the n-type silicon substrate and then performing the boron diffusion, the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer are formed in one step on the back surface of the n-type silicon substrate. The preparation method can simultaneously prepare the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer through only a single high-temperature process (i.e., boron diffusion), thereby greatly simplifying the preparation process for the solar cell and reducing production cost.

[0050] In order to make the present application more comprehensible, the present application is described in detail below with reference to the accompanying drawings. In the drawings, better embodiments of the present application are given. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. It should be understood that these embodiments are provided for the purpose of providing a more thorough understanding of the disclosure of the present application.

[0051] In addition, the terms “first” and “second” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity or order of the indicated technical features. Therefore, the features modified by “first” or “second” may explicitly or implicitly include at least one of the features. In the description of the present application, the “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined.

[0052] In describing positional relationships, unless otherwise specified, when an element such as a layer, a film, or a substrate is referred to as being “on” another film layer, it can be directly on the other film layer, or an intervening film layer may also be present. Further, when a layer is referred to as being ‘below’ another layer, it can be directly below the other film layer, or one or more intervening layers may be present. It will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0053] Unless mentioned to the contrary, terms in a singular form may include a plural form and should not be construed as being one in number.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present application pertains. The terms used in the specification of the present application herein are for the purpose of describing embodiments only and are not intended to limit the present application.

[0055] Referring to FIG. 1 to FIG. 13, an embodiment of the present application provides a method for preparing a solar cell 100, and the method includes the following step S1 to step S14.

[0056] Step S1: an n-type silicon substrate 1 is provided, a damage removal treatment is then performed on the n-type silicon substrate 1 using an alkaline solution, and then a cleaning treatment is performed. The structure of the n-type silicon substrate 1 is shown in FIG. 1.

[0057] In some embodiments, the n-type silicon substrate 1 is subjected to a damage removal treatment using a sodium hydroxide solution to remove a damaged layer on the surface of the n-type silicon substrate 1 after mechanical processing, and then the surface of the n-type silicon substrate 1 is cleaned by water washing.

[0058] Step S2: a first silicon oxide layer 2, an intrinsic amorphous silicon layer 3, a phosphosilicate glass layer 4, and a second silicon oxide layer 5 are sequentially formed on a back surface of the n-type silicon substrate 1 (i.e., a lower surface of the n-type silicon substrate 1 in FIG. 1). The structure after forming the first silicon oxide layer 2. the intrinsic amorphous silicon layer 3, the phosphosilicate glass layer 4, and the second silicon oxide layer 5 is shown in FIG. 2.

[0059] In some embodiments, by using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), the first silicon oxide layer 2 is firstly deposited on the back surface of the n-type silicon substrate 1, and then the intrinsic amorphous silicon layer 3 is deposited on the first silicon oxide layer 2. A thickness of the first silicon oxide layer 2 is 1 nm to 2 nm. A thickness of the intrinsic amorphous silicon layer 3 is 50 nm to 500 nm.

[0060] In some embodiments, the phosphosilicate glass layer 4 (PSG) and the second silicon oxide layer 5 are sequentially formed on the intrinsic amorphous silicon layer 3 by using atmospheric pressure chemical vapor deposition (APCVD). A thickness of the phosphosilicate glass layer 4 is 30 nm to 100 nm, and a mass percent of phosphorus (P) in the phosphosilicate glass layer 4 is less than or equal to 50%. A thickness of the second silicon oxide layer 5 is 30 nm to 100 nm.

[0061] Step S3: a patterned blocking layer 6 is formed in a partial region of a surface of the second silicon oxide layer 5. The structure after forming the patterned blocking layer 6 is shown in FIG. 3.

[0062] In some embodiments, a blocking layer slurry is pattenedly printed on the partial region of the surface of the second silicon oxide layer 5 according to a preset pattern, and then dried to form the above-mentioned patterned blocking layer 6. The blocking layer slurry has the following characteristics: the formed blocking layer can be dissolved in alkali but insoluble in acid.

[0063] In some embodiments, the patterned blocking layer 6 is a waxy resin material.

[0064] In some embodiments, the patterned blocking layer 6 formed after printing has printed lines with spacing ranging from 500 μm to 2000 μm.

[0065] Step S4: the phosphorosilicate glass layer 4 and the second silicon oxide layer 5 in a region of the back surface of the n-type silicon substrate 1 where the patterned blocking layer 6 is not formed are removed using a solution containing HF (i.e., hydrofluoric acid). The structure after removing the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the region where the blocking layer is not disposed is shown in FIG. 4.

[0066] In some embodiments, a hydrofluoric acid solution is used to remove the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the region where the patterned blocking layer 6 is not formed, and the first silicon oxide layer 2 is preserved. In the region of the back surface of the n-type silicon substrate I where the patterned blocking layer 6 is disposed, the phosphosilicate glass layer 4 and the second silicon oxide layer 5 on the inner side of the patterned blocking layer will not be removed due to the presence of the patterned blocking layer 6.

[0067] Step S5: the patterned blocking layer 6 is removed. The structure after removing the patterned blocking layer 6 is shown in FIG. 5.

[0068] In some embodiments. a mixed solution of sodium hydroxide and hydrogen peroxide (H₂O₂) is used to remove the patterned blocking layer 6. After removing the patterned blocking layer 6, a mixed solution of hydrochloric acid (HCl) and H₂O₂ is used to clean the n-type silicon substrate 1.

[0069] After the patterned blocking layer 6 is removed, the phosphosilicate glass layer 4 and the second silicon oxide layer 5 at the position corresponding to the patterned blocking layer 6 are preserved.

[0070] It should be noted that the purpose of the above steps S3, S4 and S5 is to form a stacked structure including the phosphosilicate glass layer 4 and the second silicon oxide layer 5 on a partial region of the back surface of the n-type silicon substrate 1, while other regions of the back surface of the n-type silicon substrate I only include the first silicon oxide layer 2 and the intrinsic amorphous silicon layer 3. The steps S3 to S5 provide the patterned blocking layer 6 as a mask layer to achieve the above purpose. It should be understood that other methods can be used to achieve the above purpose in some other embodiments of the present application, as long as the stacked structure including the phosphosilicate glass layer 4 and the second silicon oxide layer 5 is formed on a partial region of the back surface of the n-type silicon substrate 1.

[0071] Step S6: boron diffusion is performed on the back surface of the n-type silicon substrate 1. The structure after the boron diffusion is shown in FIG. 6.

[0072] During the high-temperature treatment process of the boron diffusion, the intrinsic amorphous silicon layer 3 in the region of the back surface of the n-type silicon substrate 1 where the phosphosilicate glass layer 4 and the second silicon oxide layer 5 are removed can be converted into a boron-doped polysilicon layer 7, and borosilicate glass 8 (BSG) is formed on its outer layer due to the diffusion. In contrast, due to the action of the high temperature, the phosphorus in the phosphosilicate glass layer 4 is diffused into the intrinsic amorphous silicon layer 3 in the region of the back surface of the n-type silicon substrate 1 where the phosphosilicate glass layer 4 and the second silicon oxide layer 5 are not removed (i.e., a corresponding region where the patterned blocking layer 6 is provided), and a phosphorus-doped polysilicon layer 9 is formed through crystallization and annealing. Due to the blocking of the second silicon oxide layer 5 on the outside, boron will not be doped into the intrinsic amorphous silicon layer 3 in this region. As such, the preparation of the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 can be achieved simultaneously through a one-step high-temperature process (i.e., boron diffusion), thereby greatly simplifying the preparation process of the solar cell 100 and reducing the production cost for the solar cell 100.

[0073] The region corresponding to the boron-doped polysilicon layer 7 is the p-region, and the region corresponding to the phosphorus-doped polysilicon layer 9 is the n-region.

[0074] In some embodiments, the n-type silicon substrate I is placed in a boron diffusion furnace. The boron diffusion is performed at a temperature ranging from 900° C. to 1050° C. for 1 h to 3 h by using a boron source such as boron trichloride (BCl₃) and/or boron tribromide (BBr₃). A volume proportion of the boron source in an atmosphere of the boron diffusion in the furnace is 5% to 30%. It should be understood that the temperature for boron diffusion can be but is not limited to 900° C. 920° C., 950° C. 980° C., 1000° C., 1020° C., 1050° C., etc. The time period of boron diffusion can be but is not limited to 1 h, 1.5 h, 2 h, 2.5 h, 3 h, etc. The volume proportion of the boron source in the atmosphere of the boron diffusion can be but is not limited to 5%, 8%, 10%, 12%, 15%, 18%, 20%, 22%, 25%, 28%, 30%, etc.

[0075] Step S7: laser grooving is formed at the boundary between the boron-doped polysilicon layer and the phosphorus-doped polysilicon layer by using a laser, and then etching is performed using an alkali solution to form an isolation groove 10. The structure after laser grooving to form the isolation groove 10 is shown in FIG. 7.

[0076] In some embodiments, a laser is utilized to perform laser grooving at the boundary between the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 to remove the polysilicon layer in the grooved region, and then an alkaline solution such as a sodium hydroxide solution is utilized to etch the grooved region, so that the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 are separated and are not directly connected to each other.

[0077] Step S8: a wrap-around layer 11 on the front surface of the n-type silicon substrate 1 is removed.

[0078] In some embodiments, the wrap-around layer 11 on the front surface of the n-type silicon substrate 1 including the silicon oxide layer, phosphosilicate glass, the polysilicon layer and borosilicate glass that are wrapped around is removed using a chain acid polishing (HF+HNO₃) device. By using the chain acid polishing (HF+HNO₃) device, the silicon oxide layer, phosphosilicate glass, the polysilicon layer and borosilicate glass that are wrapped around on the front surface all can be removed at one time, thereby avoiding electric leakage and appearance defect for the solar cell 100 caused by incomplete removal of the wrap-around layer 11. While removing the wrap-around layer 11 on the front surface, the phosphosilicate glass layer 4, the second silicon oxide layer 5 and borosilicate glass 8 on the back surface of the n-type silicon substrate 1 are also removed. The schematic view after the chain acid polishing treatment is shown in FIG. 8.

[0079] In some embodiments. prior to removing the wrap-around layer 11 on the front surface of the n-type silicon substrate 1, a silicon oxide film is deposited in the isolation groove 10 through atmospheric pressure chemical vapor deposition (APCVD). Then, the n-type silicon substrate 1 is subjected to removal of wrap-around layer 11 in the chain acid polishing device. As such, the silicon oxide film can protect the isolation groove 10 region on the back surface of the n-type silicon substrate 1 from being textured in the subsequent texturing process, which maintains the surface morphology of this region and reduces the carrier recombination in this region, thereby improving the overall passivation performance of the back surface of the n-type silicon substrate 1.

[0080] Step S9: a texturing process and then cleaning are performed on the front surface of the n-type silicon substrate. The structure after texturing and cleaning is shown in FIG. 9.

[0081] In some embodiments, the n-type silicon substrate 1 is placed in a slot cleaning machine, and a sodium hydroxide solution is utilized to texturize the front surface of the n-type silicon substrate 1. The back surface of the n-type silicon substrate 1 will not be etched by the alkaline solution (the texturing agent) due to the protection of phosphosilicate glass and borosilicate glass. When the texturing process is completed, a mixed solution of hydrofluoric acid and hydrochloric acid is utilized for cleaning.

[0082] Step S10: aluminum oxide layers 12 are formed on the front surface and the back surface of the n-type silicon substrate 1, respectively. The structure after forming the aluminum oxide layer 12 is shown in FIG. 10.

[0083] In some embodiments, the aluminum oxide layers 12 are respectively formed on the front surface and the back surface of the n-type silicon substrate 1 through atomic layer deposition (ALD). The thickness of the aluminum oxide layers 12 on the front surface and the back surface of the n-type silicon substrate I is each independently 3 nm to 10 nm.

[0084] Step S11: passivation and anti-reflection layers 13 are formed on the aluminum oxide layers 12 on the front surface and the back surface of the n-type silicon substrate 1, respectively. The structure after forming the passivation and anti-reflection layer 13 is shown in FIG. 11.

[0085] In some embodiments, a passivation and anti-reflection layer 13 with a thickness of 60 nm to 100 nm is first deposited on the aluminum oxide layer 12 on the front surface of the n-type silicon substrate 1 through PECVD, and then a passivation and anti-reflection layer 13 with a thickness of 80 nm to 150 nm is deposited on the aluminum oxide layer 12 on the back surface of the n-type silicon substrate 1 through PECVD.

[0086] Step S12: openings are formed in the passivation and anti-reflection layer 13 on the back surface of the n-type silicon substrate 1. The structure after forming openings is shown in FIG. 12.

[0087] In some embodiments, a laser is utilized to form openings in the passivation and anti-reflection layer 13 on the back surface of the n-type silicon substrate 1, so as to form a first electrode contact bole which is in communication with the boron-doped polysilicon layer 7 and a second electrode contact hole which is in communication with the phosphorus-doped polysilicon layer 9, respectively. As such, electrodes connected to the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 can be prepared in the first electrode contact hole and the second electrode contact hole, respectively.

[0088] Step S13: a first electrode 14 and a second electrode 15 are prepared in the first electrode contact hole and the second electrode contact hole, respectively. The structure of the obtained solar cell 100 is shown in FIG. 13.

[0089] In some embodiments, the first electrode 14 is prepared in the first electrode contact hole by screen printing, and the first electrode 14 is connected to the boron-doped polysilicon layer 7. The second electrode 15 is prepared in the second electrode contact hole by screen printing, and the second electrode 15 is connected to the phosphorus-doped polysilicon layer 9.

[0090] Step S14: light is injected.

[0091] The prepared solar cell 100 is subjected to light injection by using a light injection device.

[0092] In general, according to the preparation method of the solar cell 100 in the present application, through removing the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the partial region of the back surface of the n-type silicon substrate 1 and then performing the boron diffusion, the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 are formed in one step on the back surface of the n-type silicon substrate 1. The preparation method can simultaneously prepare the boron-doped polysilicon layer 7 and the phosphorus-doped polysilicon layer 9 through only a single high-temperature process (i.e., boron diffusion), thereby greatly simplifying the preparation process for the solar cell 100 and reducing production cost.

[0093] In addition, by forming a patterned blocking layer 6 in a partial region of the surface of the second silicon oxide layer 5 to pattern the back surface of the n-type silicon substrate 1, the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in other region of the back surface of the n-type silicon substrate 1 can be easily removed, and the phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the partial region are preserved. According to the preparation method of the solar cell 100 in the present application, the first silicon oxide layer 2 and the boron-doped polysilicon layer 7 are formed in the p-region of the back surface of the n-type silicon substrate 1, and the first silicon oxide layer 1 and the phosphorus-doped polysilicon layer 9 are formed in the n-region, which greatly improves the passivation performance of the solar cell 100, thereby facilitating to improve the open circuit voltage (Voc) of the solar cell 100.

[0094] Referring to FIG. 1 to FIG. 3, an embodiment of the present application provides a back-contact solar cell 100. The solar cell 100 includes an n-type silicon substrate 1, a first silicon oxide layer 2, a boron-doped polysilicon layer 7, a phosphorus-doped polysilicon layer 9, an aluminum oxide layer 12, a passivation and anti-reflection layer 13, a first electrode 14, and a second electrode 15.

[0095] The first silicon oxide layer 2 is disposed on the back surface of the n-type silicon substrate 1. The boron-doped polysilicon layer 7 is disposed on the first silicon oxide layer 2. The phosphorus-doped polysilicon layer 9 is disposed on the first silicon oxide layer 2 and is separated from the boron-doped polysilicon layer 7 by an isolation groove 10. Aluminum oxide layers 12 are disposed on the front surface of the n-type silicon substrate 1, on the boron-doped polysilicon layer 7, on the phosphorus-doped polysilicon layer 9 and in the isolation groove 10. Passivation and anti-reflection layers 13 are disposed on each of the aluminum oxide layers 12. The first electrode 14 extends through the passivation and anti-reflection layer 13 and the aluminum oxide layer 12 on the back surface of the n-type silicon substrate 1 and is connected to the boron-doped polysilicon layer 7. The second electrode 15 extends through the passivation and anti-reflection layer 13 and the aluminum oxide layer 12 on the back surface of the n-type silicon substrate 1 and is connected to the phosphorus-doped polysilicon layer 9.

[0096] In some embodiments, the passivation and anti-reflection layer 13 is a silicon nitride layer. The first electrode 14 and the second electrode 15 are metal gate electrodes.

[0097] The present application will be further described below in conjunction with specific examples and comparative examples, which should not be construed as limiting the protection scope of the present application.

[0098] A method for preparing an-type full back contact solar cell 100 includes the following steps.

[0099] An n-type silicon substrate 1 is provided, followed by performing a damage removal treatment on the n-type silicon substrate 1 with an alkaline solution of sodium hydroxide (NaOH) and then a cleaning treatment.

[0100] A first silicon oxide layer 2 with a thickness of 1 nm and an intrinsic amorphous silicon layer 3 with a thickness of 200 nm are sequentially deposited on the back surface of the n-type silicon substrate 1 through LPCVD.

[0101] A phosphosilicate glass layer 4 (PSG) and a second silicon oxide layer 5 are sequentially deposited on the intrinsic amorphous silicon layer 3 by APCVD. In which, a thickness of the phosphosilicate glass layer 4 is 50 nm, a mass percent of phosphorus (P) in the phosphosilicate glass layer 4 is 30%, and a thickness of the second silicon oxide layer 5 is 50 nm.

[0102] A corrosion-resistant slurry, which is a waxy resin material and is characterized by acid resistance and no alkali resistance, is printed in a partial region of the second silicon oxide layer 5 on the back surface of the n-type silicon substrate 1, and dried to form a patterned blocking layer 6 having printed lines with spacing of 1200 μm.

[0103] The phosphosilicate glass layer 4 and the second silicon oxide layer 5 in the region where the patterned blocking layer 6 is not formed are removed with a HF solution. The patterned blocking layer 6 is then removed with a mixed solution of NaOH and H₂O₂. Next, a mixed solution of HCl and H₂O₂ is used for cleaning.

[0104] The above n-type silicon substrate 1 is placed in a boron diffusion furnace. By using BCl₃ as a boron source (with a volume proportion of 20% in the atmosphere), the back surface of the n-type silicon substrate 1 is subjected to boron diffusion at a temperature of 980° C. for 2 h to form p-type B-doped polysilicon (i.e., boron-doped polysilicon layer 7). Due to the diffusion, borosilicate glass (BSG) is formed in the outer layer of the boron-doped polysilicon layer 7. In the region where the phosphosilicate glass layer 4 and the second silicon oxide layer 5 are retained, the phosphorus in the phosphosilicate glass layer 4 is pushed into the intrinsic amorphous silicon layer 3 due to the action of the high temperature, to form n-type P-doped polysilicon (i.e., phosphorus-doped polysilicon layer 9); and boron will not be doped into the intrinsic amorphous silicon layer 3 due to the blocking of the outer second silicon oxide layer 5 in this region.

[0105] A laser is used to ablate the boundary between the p-region (i.e., a region having the boron-doped polysilicon layer 7) and the n-region (i.e., a region having the phosphorus-doped polysilicon layer 9), and then the junction is etched using a NaOH solution to form an isolation groove 10 that separates the boron-doped polysilicon layer 7 from the phosphorus-doped polysilicon layer 9.

[0106] A chain acid polishing (HF+HNO₃) device is used to remove silicon oxide, phosphosilicate glass, polysilicon and borosilicate glass wrapped around on the front surface of the n-type silicon substrate 1. Next, the n-type silicon substrate 1 is sent to a slot cleaning machine, and a NaOH solution is utilized to texturize the front surface of the n-type silicon substrate 1, during which the back surface is not etched by the alkaline solution due to the protection of the phosphosilicate glass layer 4 and the borosilicate glass layer. Then, a mixed solution of HF and HCl is utilized for cleaning.

[0107] Aluminum oxide layers 12 (AlOx) with a thickness of 5 nm are respectively formed on the front surface and the back surface of the n-type silicon substrate 1 through ALD.

[0108] A passivation and anti-reflection layer 13 with a thickness of 75 nm is deposited on the front surface of the n-type silicon substrate 1 and a passivation and anti-reflection layer 13 with a thickness of 100 nm is deposited on the back surface of the n-type silicon substrate 1 through tubular PECVD.

[0109] A laser is utilized to form openings in the passivation and anti-reflection layer 13 on the back surface of the n-type silicon substrate 1, to form a first electrode contact hole which is communicated with the boron-doped polysilicon layer 7 and a second electrode contact hole which is communicated with the phosphorus-doped polysilicon layer 9, respectively.

[0110] A first electrode 14 is formed at the first electrode contact hole and a second electrode 15 is formed at the second electrode contact hole by screen printing. The first electrode 14 is connected to the boron-doped polysilicon layer 7, and the second electrode 15 is connected to the phosphorus-doped polysilicon layer 9.

[0111] Light is injected into the prepared solar cell 100 to obtain the n-type full back contact solar cell 100.

[0112] The method for preparing the solar cell 100 in this example is basically the same as that in Example 1, except that the first silicon oxide layer 2 and the intrinsic amorphous silicon layer 3 are sequentially formed on the back surface of the n-type silicon substrate I through the PECVD method. By using this preparation method, the wrap-around layer 11 formed on the front surface of the n-type silicon substrate 1 is less and is easier to remove, which is beneficial to improving the appearance and yield of the solar cell 100.

[0113] The method for preparing the solar cell 100 in this example is basically the same as that in Example 1, except that the mass percent of phosphorus (P) in the phosphosilicate glass layer 4 deposited on the intrinsic amorphous silicon layer 3 by APCVD in this example is reduced to 20% from 30% in Example 1.

[0114] That is, the doping concentration of the n-region of the solar cell 100 prepared in this example is reduced, and thus the concentration of phosphorus in the phosphorus-doped polysilicon layer 9 is reduced, which reduces the carrier recombination in the n-region, thereby improving the passivation performance of the n-region.

[0115] The method for preparing the solar cell 100 in this example is basically the same as that in Example 1, except that after forming the isolation groove 10, a third silicon oxide layer with a thickness of 50 nm to 200 nm is deposited in the isolation groove 10 by APCVD, and then the chain acid polishing to remove the wrap-around layer in step 8 and texturing are performed.

[0116] In the preparation method of this example, by depositing the third silicon oxide layer in the isolation groove 10, the laser grooved region on the back surface of the n-type silicon substrate 1 can be protected from being textured, which maintains the morphology of the polished surface on the back surface of the n-type silicon substrate and reduces the carrier recombination in this region, thereby improving the overall passivation performance of the back surface of the n-type silicon substrate 1.

[0117] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features are described in the embodiments. However, as long as there is no contradiction in the combination of these technical features, the combinations should be considered as in the scope of the present disclosure.

[0118] The above-described embodiments are only several implementations of the present disclosure, and the descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present disclosure. It should be understood by those of ordinary skill in the art that various modifications and improvements can be made without departing from the concept of the present disclosure, and all fall within the protection scope of the present disclosure. Therefore, the patent protection of the present disclosure shall be defined by the appended claims.