Operational amplifier

[0001] The present application is a Section 371 National Stage application of International Application No. PCT/CN2021/125339, filed on Oct. 21, 2021, which published as WO 2022/121526 A1, on Jun. 16, 2022, not in English, and claims priority to Chinese patent application No. 202011451042.9, filed on Dec. 10, 2020, entitled “Operational Amplifier”, the contents of which are incorporated herein by reference in their entireties.

[0002] The present disclosure relates to a technical field of electronic circuits, in particular to an operational amplifier.

[0003] OPA is an abbreviation of operational amplifier. In an actual circuit, a feedback network is usually combined with an OPA to form a module having a particular function. Operational amplifier was applied in analog computers in early days to realize mathematical operations, from which it got its name, and this name continues to this day. Operational amplifier is a circuit unit named from a functional point of view, and can be realized by a discrete device or in a semiconductor chip. With the development of semiconductor technology, most operational amplifiers now exist in a monolithic form of chip. Nowadays, there are many kinds of operational amplifiers, which are widely used in almost all industries.

[0004] Generally, an input terminal of an operational amplifier is not connected with any protection structure, which brings a disadvantage that in the circuit, if an input voltage difference of the operational amplifier is large, it may be difficult to handle a common terminal of an input transistor pair of the operational amplifier, as long as a source-drain voltage (VGS) corresponding to one of input terminals of the input transistor pair consisting of MOS (Metal Oxide Semiconductor) transistors exceeds a maximum voltage that can be withstood, the operational amplifier may be burned or operational amplifier performance may be changed.

[0005] As shown in FIG. 1, an operational amplifier 100 having an open-loop structure and an input transistor pair consisting of N-type MOS transistors is taken as an example here. VP and VN are represented as a power supply terminal and a virtual ground terminal of the operational amplifier, respectively. NMOS transistor MN1 and NMOS transistor MN2 are arranged as an input transistor pair. PMOS transistor MP1 and PMOS transistor MP2 are arranged as a loading transistor pair. (V+) and (V−) represent a non-inverting input voltage and an inverting input voltage, respectively. When a voltage difference between (V+) and (V−) is large, for example, when (V+) is 20V, (V−) is 2V, and VGS is 1V, a voltage VA at node A is VA=(V+)−VGS=20V−1V=19V, and at this time VGS (MN2)=(V−)−VA=2V−19V=−17V. Based on a general process, operating range of VGS of an MOS transistor is −5.5V˜5.5V. Obviously, VGS of NMOS transistor MN2 exceeds process limit. MN2 may be damaged.

[0006] Based on this, a solution proposed by the prior art is to clamp gate of the input transistor pair, as shown in FIG. 2. An operational amplifier 200 having an open-loop structure and an input transistor pair consisting of N-type MOS transistors is given here as an example. VP and VN are a power supply terminal and a virtual ground terminal of the operational amplifier, respectively. NMOS transistor MN1 and NMOS transistor MN2 are arranged as an input transistor pair. PMOS transistor MP1 and PMOS transistor MP2 are arranged as a loading transistor pair. (V+) and (V−) represent a non-inverting input voltage and an inverting input voltage, respectively.

VINP and VINN are gate voltages of MN1 and MN2, respectively. Diode D1 and diode D2 are clamping diodes between VINP and VINN (VD1 is a turn-on voltage of diode D1, which is 0.6 V generally).

[0007] When a voltage difference between (V+) and V− is large, for example, when (V+)=20V and (V−)=2V, VINP>VINN, D1 is turned on, and VINN is clamped, so that VINN=VINP−VD1. Therefore, a voltage difference between VINP and VINN is 0.6 V, that is, VINP−VINN=0.6 V. At this time, a conductive path is formed from (V+) to (V−) through resistor R1, diode D1 and resistor R2, thus a current I0 flowing from (V+) to (V−) is generated:
I0=((V+)−(V−)−VD1)/(R1+R2)=0.87mA,
therefore, VINP=(V+)−R1*I0=20V−10K*0.87mA=11.3V,

• • [0008] based on this, it can be obtained that the voltage VA at node A can be VA=VINP-VGS=11.3V−1V=10.3V,
    and VINN=VINP−0.6V=10.3V−0.6V=9.7V,
  • [0009] therefore, VGS (MN2)=VINN−VA=9.7V−10.3V=−0.6V, so that the VGS of the input transistor pair will not exceed process limit.

[0010] However, in this solution, there will be a current flowing from (V+) to (V−). In some specific application scenarios, it is not expected to have a current flowing through (V+), so this solution according to the prior art cannot meet requirements of those application scenarios.

[0011] In order to solve the above technical problems, an operational amplifier is provided according to embodiments of the present disclosure, and can allow a source-drain voltage of an input transistor pair included in the operational amplifier to be within a voltage range accepted by process, ensuring that an output voltage of the operational amplifier under normal conduction state is stabilized within a certain range, and improving stability of the operational amplifier.

[0012] According to embodiments of the present disclosure, an operational amplifier is provided, and comprises:

• • [0013] a loading input transistor pair;
  • [0014] a differential input transistor pair, connected with the loading input transistor pair, wherein a non-inverting input signal is applied to a non-inverting input terminal of the differential input transistor pair, and an inverting input signal is applied to an inverting input terminal of the differential input transistor pair;
  • [0015] a controller unit, configured to generate a first control signal according to the non-inverting input signal and a second control signal according to the inverting input signal;
  • [0016] a regulator unit, connected between the differential input transistor pair and ground, controlled by the first control signal and the second control signal, and configured to select an on/off state of the regulator unit itself according to a voltage difference between the non-inverting input signal and the inverting input signal.

[0017] In some embodiments, the loading input transistor pair comprises a first transistor and a second transistor,

• • [0018] a first terminal of the first transistor and a first terminal of the second transistor are jointly connected to a power supply terminal of the operational amplifier, and a control terminal of the first transistor and a control terminal of the second transistor are jointly connected to a second terminal of the first transistor.

[0019] In some embodiments, the differential input transistor pair comprises a third transistor and a fourth transistor,

• • [0020] the third transistor has a first terminal connected with the second terminal of the first transistor, a second terminal connected with the regulator unit, and a control terminal serving as the non-inverting input terminal for receiving the non-inverting input signal,
  • [0021] the fourth transistor has a first terminal connected with a second terminal of the second transistor, a second terminal connected with the regulator unit, and a control terminal serving as the inverting input terminal for receiving the inverting input signal.

[0022] In some embodiments, the regulator unit comprises:

• • [0023] a fifth transistor and a sixth transistor connected in series between the second terminal of the third transistor and the second terminal of the fourth transistor,
  • [0024] wherein a control terminal of the fifth transistor is configured to receive the first control signal, a control terminal of the sixth transistor is configured to receive the second control signal, and a connection node between the fifth transistor and the third transistor is a first node, a connection node between the fifth transistor and the sixth transistor is a second node, and a connection node between the sixth transistor and the fourth transistor is a third node.

[0025] In some embodiments, the regulator unit further comprises:

• • [0026] a first current source, which is connected between the first node and the ground and configured to provide a first current;
  • [0027] a second current source, which is connected between the second node and the ground and configured to provide a second current;
  • [0028] a third current source, which is connected between the third node and the ground and configured to provide a third current.

[0029] In some embodiments, any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor is a metal oxide semiconductor field effect transistor.

[0030] In some embodiments, each of the first transistor and the second transistor is a P-type metal oxide semiconductor field effect transistor,

[0031] and each of the third transistor, the fourth transistor, the fifth transistor and the sixth transistor is an N-type metal oxide semiconductor field effect transistor.

[0032] In some embodiments, each of the fifth transistor and the sixth transistor is a N-type metal oxide semiconductor field effect transistor with high withstand voltage.

[0033] In some embodiments, in response to the voltage difference between the non-inverting input signal and the inverting input signal being greater than a withstand voltage of the third transistor or the fourth transistor, both the fifth transistor and the sixth transistor are operated in turn-on state.

[0034] In some embodiments, the first control signal has a voltage which is numerically equal to a sum of a voltage of the non-inverting input signal and a preset voltage, and the second control signal has a voltage which is numerically equal to a sum of a voltage of the inverting input signal and the preset voltage, and the preset voltage is adjustable.

[0035] The present disclosure has following beneficial effects: the operational amplifier provided according to embodiments of the present disclosure comprises: a loading input transistor pair; a differential input transistor pair connected with the loading input transistor pair, wherein a non-inverting input signal is applied to a non-inverting input terminal of the differential input transistor pair, and an inverting input signal is applied to an inverting input terminal of the differential input transistor pair; a controller unit that generates a first control signal according to the non-inverting input signal, and a second control signal according to the inverting input signal; a regulator unit, which is connected between the differential input transistor pair and ground, controlled by the first control signal and the second control signal, and is configured to select an on/off state of the regulator unit itself according to a voltage difference between the non-inverting input signal and the inverting input signal. The voltage difference between the non-inverting input signal and the inverting input signal is transferred to the regulator unit and is withstood by MOS transistors (the fifth transistor and the sixth transistor) with high withstand voltage, thus allowing a source-drain voltage of the input transistor pair included in the operational amplifier to be within a voltage range accepted by process, ensuring that an output voltage of the operational amplifier under normal conduction state can be stabilized within a certain range, and improving stability of the operational amplifier.

[0040] For making the present disclosure easily understood, a more complete description of the present disclosure is provided below with reference to the associated drawings. Some preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in different forms and is not limited to the embodiments described herein. These embodiments are provided for making the present disclosure more thoroughly and fully understood. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as would normally be understood by those skilled in the art of the present disclosure. Terms used herein in the specification of the present disclosure are for an objective to describe specific embodiments only and are not intended to limit the present invention.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0042] FIG. 3 shows a circuit structure diagram of an operational amplifier provided according to an embodiment of the present disclosure.

[0043] Referring to FIG. 3, according to an embodiment of the present disclosure, an operational amplifier 300 is provided, wherein VP is a power supply terminal of the operational amplifier 300, VN is a virtual ground terminal of the operational amplifier 300, and (V+) and (V−) represent a non-inverting input voltage (hereinafter referred to as a non-inverting input signal) and an inverting input voltage (hereinafter referred to as an inverting input signal), respectively. The operational amplification 300 at least includes:

• • [0044] a loading input transistor pair;
  • [0045] a differential input transistor pair, which is connected to the loading input transistor pair, wherein the non-inverting input signal (V+) is applied to a non-inverting input terminal of the differential input transistor pair, and the inverting input signal (V−) is applied to an inverting input terminal of the differential input transistor pair;
  • [0046] a controller unit 110, configured to generate a first control signal VG1 according to the non-inverting input signal (V+) and a second control signal VG2 according to the inverting input signal (V−); and
  • [0047] a regulator unit 120, which is connected between the differential input transistor pair and ground, controlled by the first control signal and the second control signal, and configured to select an on/off state of the regulator unit itself according to a voltage difference between the non-inverting input signal and the inverting input signal.

[0048] Further, the loading input transistor pair comprises a first transistor MP1 and a second transistor MP2,

• • [0049] wherein a first terminal of the first transistor MP1 and a first terminal of the second transistor MP2 are jointly connected to the power supply terminal VP of the operational amplifier 300, and a control terminal of the first transistor MP1 and a control terminal of the second transistor MP2 are jointly connected to a second terminal of the first transistor MP1.

[0050] Further, the differential input transistor pair comprises a third transistor MN1 and a fourth transistor MN2, wherein a first terminal of the third transistor MN1 is connected to the second terminal of the first transistor MP1, a second terminal of the third transistor MN1 is connected to the regulator unit 120, a control terminal of the third transistor MN1 serves as the non-inverting input terminal of the operational amplifier to receive the non-inverting input signal (V+), a first terminal of the fourth transistor MN2 is connected to a second terminal of the second transistor MP2, a second terminal of the fourth transistor MN2 is connected to the regulator unit 120, and a control terminal of the fourth transistor MN2 serves as the inverting input terminal to receive the inverting input signal (V−).

[0051] Further, the regulator unit 120 comprises a fifth transistor MN3 and a sixth transistor MN4 connected in series between the second terminal of the third transistor MN1 and the second terminal of the fourth transistor MN2, wherein a control terminal of the fifth transistor MN3 receives the first control signal VG1, a control terminal of the sixth transistor MN4 receives the second control signal VG2, and a connection node between the fifth transistor MN3 and the third transistor MN1 is a first node A, a connection node between the fifth transistor MN3 and the sixth transistor MN4 is a second node B, and a connection node between the sixth transistor MN4 and the fourth transistor MN2 is a third node C.

[0052] Further, the regulator unit 120 further comprises:

• • [0053] a first current source, connected between the first node A and the virtual ground terminal VN for providing a first current I1; a second current source connected between the second node B and the virtual ground terminal VN for providing a second current I2; a third current source connected between the third node C and the virtual ground terminal VN for supplying a third current I3.

[0054] Further, any one of the first transistor MP1, the second transistor MP2, the third transistor MN1, the fourth transistor MN2, the fifth transistor MN3, and the sixth transistor MN4 is a metal oxide semiconductor field effect transistor (MOS transistor for short).

[0055] Further, in this embodiment, each of the first transistor MP1 and the second transistor MP2 is a P-type MOS transistor, and each of the third transistor MN1, the fourth transistor MN2, the fifth transistor MN3 and the sixth transistor MN4 is an N-type MOS transistor.

[0056] Further, in this embodiment, each of the fifth transistor MN3 and the sixth transistor MN4 is an N-type MOS transistor with high withstand voltage.

[0057] Further, in the controller unit 110, the first control signal VG1 serves as a gate voltage of the fifth transistor MN3, and has a voltage which is numerically equal to a sum of a voltage of the non-inverting input signal (V+) and a preset voltage ΔV; and the second control signal VG2 serves as a gate voltage of the sixth transistor MN4, and has a voltage which is numerically equal to a sum of the inverting input signal (V−) and the preset voltage ΔV, and the preset voltage ΔV is adjustable.

[0058] In an actual application, the preset voltage ΔV can be adjusted according to an operating voltage range of an actual operational amplifier and a turn-on voltage of the third transistor MN1 and the fourth transistor MN2 which constitute the differential input transistor pair.

[0059] Further, in the operational amplifier 300, in response to the voltage difference between the non-inverting input signal (V+) and the inverting input signal (V−) being larger than a withstand voltage (VDS) of the third transistor MN1 or the fourth transistor MN2, the fifth transistor MN3 and the sixth transistor MN4 are both in turn-on state, the voltage difference is withstood by the fifth transistor MN3 and the sixth transistor MN4 with high withstand voltage, thereby ensuring that VGS of the third transistor MN1 and the fourth transistor MN2 in the differential input transistor pair is within a voltage range accepted by process, and operational characteristics of the operational amplifier 300 can be normal.

[0060] In an embodiment, for example, the threshold voltages of the third transistor MN1 and the fourth transistor MN2 are both Vth, and the threshold voltages of the fifth transistor MN3 and the sixth transistor MN4 are both Vth_H.

[0061] In a first implementation scenario, the non-inverting input signal (V+) is 20V, the inverting input signal (V−) is 2V, the preset voltage ΔV is 2V, Vth=1V, and Vth_H=2V, then

• • [0062] the voltage VA at the first node A is VA=(V+)−Vth=19V,
  • [0063] the gate voltage of the fifth transistor MN3 is VG1=(V+)+ΔV=20V+2V=22V,
  • [0064] the gate-source voltage of the fifth transistor MN3 is
    VGS(MN3)=VG1−VA=22V−19V=3V>Vth_H,
  • [0065] therefore, the fifth transistor MN3 is in turn-on state, so VB=VA=19V.

[0066] The gate voltage of the sixth transistor MN4 is VG2=(V−)+ΔV=2V+2V=4V,

• • [0067] the voltage VC at the third node C is VC=VG2−Vth_H=4V−2V=2V,
  • [0068] the gate-source voltage of the fourth transistor MN2 is VGS (MN2)=(V−)−VC=2V−2V=0V, which does not exceed its process limit.

[0069] At this time, the source-drain voltage of the sixth transistor MN4 is
VDS(MN4)=VB−VC=19V−2V=17V,

[0070] A high voltage portion of the voltage difference between the non-inverting input signal (V+) and the inverting input signal (V−) is withstood by the sixth transistor MN4 having high withstand voltage. And since the gate-source voltage of the fourth transistor MN2 is VGS=0V, the fourth transistor MN2 is in turn-off state and the third transistor MN1, the fifth transistor MN3 and the sixth transistor MN4 are all in turn-on state, so that the first current I1, the second current I2 and the third current I3 all flow through the third transistor MN1. At this time, operational characteristics of the operational amplifier 300 are consistent with those of normal operational amplifiers.

[0071] In a second implementation scenario, where the non-inverting input signal (V+) is 2V, the inverting input signal (V−) is 20V, the preset voltage ΔV is 2V, Vth=1V, and Vth_H=2V, based on a principle similar to the first implementation scenario, it can be obtained that, in the second implementation scenario, the third transistor MN1 is in turn-off state, and the fourth transistor MN2, the fifth transistor MN3 and the sixth transistor MN4 are in turn-on state. Therefore, the first current I1, the second current I2 and the third current I3 all flow through the fourth transistor MN2. At this time, operational characteristics of the operational amplifier 300 are also consistent with those of normal operational amplifiers.

[0072] In a third implementation scenario, when both the non-inverting input signal (V+) and the inverting input signal (V−) are 2V, the preset voltage ΔV is 2V, Vth=1V, and Vth_H=2V, then

• • [0073] the voltage VA at the first node A is VA=(V+)−Vth=1V,
  • [0074] the gate voltage of the fifth transistor MN3 is VG1=(V+)+ΔV=2V+2V=4V,
  • [0075] the gate-source voltage of the fifth transistor MN3 is
    VGS(MN3)=VG1−VA=4V−1V=3V>Vth_H,
  • [0076] therefore, the fifth transistor MN3 is in turn-on state, so VB=VA=1V.

[0077] The gate voltage of the sixth transistor MN4 is VG2=(V−)+ΔV=2V+2V=4V,

• • [0078] the gate-drain voltage of the sixth transistor MN4 is
    VGD(MN4)=VG2−VB=4V−1V=3V>Vth_H,
  • [0079] therefore, the sixth transistor MN4 is also in turn-on state, so VC=VB=1V.

[0080] The gate-source voltage of the fourth transistor MN2 is VGS (MN2)=(V−)−VC=2V−1V=1V,

• • [0081] therefore, the fourth transistor MN2 is also in turn-on state, and at this time
  • [0082] the gate-source voltage of the third transistor MN1 is VGS (MN1)=VGS (MN2),
  • [0083] therefore, the first current I1, the second current I2, and the third current I3 each flow through the third transistor MN1 and the fourth transistor MN2 evenly. At this time, operational characteristics of the operational amplifier 300 are also consistent with those of normal operational amplifiers.

[0084] To sum up, an operational amplifier 300 provided according to embodiments of the present disclosure includes: a loading input transistor pair; a differential input transistor pair connected with the loading input transistor pair, wherein a non-inverting input signal is applied to a non-inverting input terminal of the differential input transistor pair, and an inverting input signal is applied to an inverting input terminal of the differential input transistor pair; a controller unit 110, configured to generate a first control signal VG1 according to the non-inverting input signal (V+) and a second control signal VG2 according to the inverting input signal (V−); and a regulator unit 120, which is connected between the differential input transistor pair and ground, controlled by the first control signal VG1 and the second control signal VG2, and configured to select an on/off state of the regulator unit itself according to a voltage difference between the non-inverting input signal (V+) and the inverting input signal (V−). When there is a large voltage difference between the gate voltages of the third transistor MN1 and the fourth transistor MN2 which constitute the differential input transistor pair, the operational amplifier 300 can selectively transfer the voltage difference to the regulator unit 120 to make the voltage difference withstood by the high-voltage MOS transistors (the fifth transistor MN3 and the sixth transistor MN4), thereby allowing the source-drain voltage of the input transistor pair included in the operational amplifier 300 to be within a voltage range accepted by process, ensuring that the output voltage of the operational amplifier 300 under normal conduction state can be stabilized within a certain range, and improving stability of the operational amplifier 300.

[0085] It should be noted that, in the description of the present disclosure, it should be understood that terms “up”, “down”, “inside” and the like denote an orientation or positional relationship for ease and simplification of describing the present disclosure only, and are not intended to indicate or imply that the referenced component or element must have a particular orientation, or be constructed and operate in a particular orientation, therefore cannot be construed as limiting to the present disclosure.

[0086] Moreover, in the present disclosure, terms “including”, “comprising” or any other variation thereof are intended to encompass non-exclusive inclusion, so that a process, method, article or equipment including a set of elements, may not only include those elements, but may also include other elements that are not explicitly listed, or may further include elements inherent to such process, method, article or equipment. In the absence of more limitations, an element limited by a statement “comprises a . . . ” does not preclude an existence of another identical element in the process, method, article or equipment including said element.

[0087] Finally, it should be noted that, it is obvious that the embodiments in accordance with the present disclosure are described above, and these embodiments neither exhaustively describe all the details nor limit the present disclosure to only specific embodiments. Other variations or modifications in different forms may be made on the basis of the above description for those of ordinary skill in the art. Providing an exhaustive list of all embodiments here is not necessary and is also impossible. However, obvious variations or modifications derived therefrom are still within the protection scope of the present disclosure.