Power converter having stable output voltage

[0001] This application claims the benefit of priority to Taiwan Patent Application No. 113101282, filed on Jan. 12, 2024. The entire content of the above identified application is incorporated herein by reference.

[0002] Some references, which may include patents, patent applications and various publications, may be cited and discussed in the description of this disclosure. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to the disclosure described herein. All references cited and discussed in this specification are incorporated herein by reference in their entireties and to the same extent as if each reference was individually incorporated by reference.

[0003] The present disclosure relates to power converters, and more particularly to a power converter having a stable output voltage.

[0004] For electronic devices, power converters are indispensable devices for adjusting power and supplying the adjusted power to the electronic devices. The high-side switch and the low-side switch of the power converter need to be switched according to the voltage or current data of circuit components of the power converter, so that the power converter can provide power to the load. However, the conventional control circuit of the power converter fails to effectively control the on-time of the high-side switch and the low-side switch, thus causing the output voltage of the power converter to be unstable when starting up, and when the input voltage of the power converter is excessively high, the output voltage cannot be adjusted to an appropriate voltage value.

[0005] In response to the above-referenced technical inadequacies, the present disclosure provides a power converter having a stable output voltage. The power converter having a stable output voltage of the present disclosure includes a high-side switch, a low-side switch, an error amplifier, a low-side feedback circuit, a pulse wave signal generator circuit, a control circuit and a driver circuit. A first end of the high-side switch is coupled to an input voltage. A first end of the low-side switch is connected to a second end of the high-side switch. A second end of the low-side switch is grounded. A node between the first end of the low-side switch and the second end of the high-side switch is connected to a first end of an inductor. A second end of the inductor is connected to a first end of an output capacitor. A second end of the capacitor is grounded. A first input end of the error amplifier is connected to the first input end of the output capacitor. A second input end of the error amplifier is coupled to a reference voltage. A low-side feedback circuit is connected to the second end and a control end of the low-side switch and an output end of the error amplifier, and configured to output a blank clock signal according to a voltage signal at the second end of the low-side switch, a low-side drive signal at the control end of the low-side switch, and an error amplification signal received from the output end of the error amplifier. A pulse wave signal generator circuit is connected to the low-side feedback circuit, and configured to set a frequency of a clock signal and output the clock signal according to the blank clock signal received from the low-side feedback circuit. A control circuit and is connected to the pulse wave signal generator circuit, and configured to output a control signal according to the clock signal received from the pulse wave signal generator circuit. The driver circuit is connected to the control circuit, a control end of the high-side switch and the control end of the low-side switch, and configured to output a high-side drive signal to the control end of the high-side switch and output the low-side drive signal to the control end of the low-side switch according to the control signal received from the control circuit.

[0006] As mentioned above, the present disclosure provides a power converter having a stable output voltage. The switching frequency of the high-side switch and the low-side switch of the power converter of the present disclosure can be modulated according to the output voltage of the power converter of the present disclosure, including automatically reducing the switching frequency of the high-side switch and the low-side switch when the on-time of the high-side switch reaches a minimum on-time, so that the output voltage of the power converter of the present disclosure is maintained at a stable value.

[0007] These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.

[0019] The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a,” “an” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure.

[0020] The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether or not a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first,” “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like.

[0021] Reference is made to FIG. 1, which is a circuit diagram of a power converter having a stable output voltage according to a first embodiment of the present disclosure.

[0022] In the first embodiment, the power converter of the present disclosure includes a high-side switch M1, a low-side switch M2, an error amplifier ERR, a low-side feedback circuit LSFB, a pulse wave signal generator circuit PS, a control circuit CTR and a driver circuit DRV.

[0023] A first end of the high-side switch M1 is coupled to an input voltage VIN. A first end of the low-side switch M2 is connected to a second end of the high-side switch M1. A second end of the low-side switch M2 is grounded. A node LX between the first end of the low-side switch M2 and the second end of the high-side switch M1 is connected to a first end of an inductor L. A second end of the inductor L is connected to a first end of an output capacitor Co. A second end of the output capacitor Co is grounded. The first end of the output capacitor Co can also be connected to the first end of the inductor L. A second end of an output resistor RL is grounded.

[0024] The node between the first end of the output capacitor Co and the second end of the inductor L is used as the output end of the power converter of the present disclosure. The voltage of the node between the first end of the output capacitor Co and the second end of the inductor L is used as an output voltage VOUT of the power converter of the present disclosure.

[0025] A first input end of the error amplifier ERR, such as the inverting input end (through the voltage divider circuit DV as shown in FIG. 1), is connected to the node between the first end of the output capacitor Co and the second end of the inductor L. A second input end of the error amplifier ERR, such as the non-inverting input end, is coupled to a reference voltage VREF.

[0026] The voltage divider circuit DV may include a first voltage divider resistor Rd1 and a second voltage divider resistor Rd2. A first end of the first voltage divider resistor Rd1 is used as an input end of the voltage divider circuit DV and is connected to the first end of the output capacitor Co. A first end of the second voltage divider resistor Rd2 is used as an output end of the voltage divider circuit DV and is connected to a second end of the first voltage divider resistor Rd1 and the first input end of the error amplifier ERR, such as the inverting input end. A second end of the second voltage divider resistor Rd2 is grounded.

[0027] The low-side feedback circuit LSFB is connected to a node between the second end of the low-side switch M2 and ground, and is connected to a control end of the low-side switch M2 and an output end of the error amplifier ERR.

[0028] The pulse wave signal generator circuit PS is connected to the low-side feedback circuit LSFB. The control circuit CTR is connected to the pulse wave signal generator circuit PS. The driver circuit DRV is connected to the control circuit CTR, a control end of the high-side switch M1 and the control end of the low-side switch M2.

[0029] As shown in FIG. 1, the output voltage VOUT of the power converter of the present disclosure (that is, the voltage of the node between the first end of the output capacitor Co and the second end of the inductor L) is divided by the voltage divider circuit DV to generate a divided voltage, which is transmitted as an output feedback voltage VOUTFB to the first input end of the error amplifier ERR, such as the inverting input end.

[0030] It should be understood that the voltage divider circuit DV is an optional component, and the present disclosure is not limited thereto. In practice, the voltage divider circuit DV can also be omitted in the power converter of the present disclosure. In this case, the output voltage VOUT of the power converter of the present disclosure is transmitted as the output feedback voltage VOUTFB to the first input end of the error amplifier ERR, such as the inverting input end.

[0031] The error amplifier ERR multiplies the difference between a divided voltage of the output voltage VOUT of the power converter of the present disclosure and a reference voltage VREF by a gain to output an error amplification signal EAO.

[0032] It is worth noting that the low-side feedback circuit LSFB sets a level of a pulse wave of a blank clock signal BLCLK according to the voltage signal received at the second end of the low-side switch M2 each time, the low-side drive signal LG of the control end of the low-side switch M2, and the error amplification signal EAO received from the output end of the error amplifier ERR and then sets a width of the pulse wave of the blank clock signal BLCLK. The low-side feedback circuit LSFB outputs the blank clock signal BLCLK.

[0033] The pulse wave signal generator circuit PS sets a frequency of a clock signal CLK according to the blank clock signal BLCLK received from the low-side feedback circuit LSFB, and outputs the clock signal CLK.

[0034] The control circuit CTR outputs a control signal PWM according to the clock signal CLK received from the pulse wave signal generator circuit PS and the error amplification signal EAO received from the output end of the error amplifier ERR.

[0035] For example, the control circuit CTR can modulate a pulse wave width modulation according to the clock signal CLK received from the pulse wave signal generator circuit PS and the error amplification signal EAO received from the output end of the error amplifier ERR, and outputs the pulse wave width modulation signal as a control signal PWM.

[0036] The driver circuit DRV outputs a high-side drive signal HG to the control end of the high-side switch M1 and a low-side drive signal LG to the control end of the low-side switch M2 according to the control signal PWM received from the control circuit CTR to drive the high-side switch M1 and the low-side switch M2.

[0037] Reference is made to FIGS. 2, 3 and 5 to 7. FIG. 2 is a circuit diagram of a power converter having a stable output voltage according to the second embodiment of the present disclosure, FIG. 3 is a circuit diagram of a first pulse wave signal generator of a power converter having a stable output voltage according to a third embodiment of the present disclosure, and FIGS. 5 to 7 are waveform diagrams of a signal of a power converter having a stable output voltage according to the second embodiment of the present disclosure.

[0038] In addition to the high-side switch M1, the low-side switch M2, the error amplifier ERR, the low-side feedback circuit LSFB, the pulse wave signal generator circuit PS, the control circuit CTR and the driver circuit DRV, the power converter of the present disclosure can further include a pulse wave reference input circuit INS, a compensation circuit SPS or a combination thereof as shown in FIG. 2.

[0039] The similarities between the second embodiment of the present disclosure and the first embodiment of the present disclosure will not be described again below.

[0040] In the second embodiment, as shown in FIG. 2, for example, the low-side feedback circuit LSFB may include a low-side detector LSN, a low-side comparator CMPLS, and a frequency modulation determination circuit LSAT. The pulse wave signal generator circuit PS may include a first pulse wave signal generator PU1 and a second pulse wave signal generator PU2.

[0041] The low-side detector LSN is connected to a node between the second end of the low-side switch M2 and ground.

[0042] The low-side comparator CMPLS is a comparator. A first input end of the low-side comparator CMPLS, such as the non-inverting input end, is connected to the low-side detector LSN. A second input end of the low-side comparator CMPLS, such as the inverting input end, is connected to the output end of the error amplifier ERR.

[0043] The frequency modulation determination circuit LSAT is connected to an output end of the low-side comparator CMPLS, the control end of the low-side switch M2 and the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS.

[0044] The frequency modulation determination circuit LSAT may include one or more logic components according to actual application requirements. If the non-inverting input end of the low-side comparator CMPLS is connected as the first input end to the low-side detector LSN, the inverting input end of the low-side comparator CMPLS is connected as the second input end to the output end of the error amplifier ERR, and the low-side switch M2 uses an n-type metal oxide semiconductor field effect transistor (NMOS) and is turned on with a high-level low-side drive signal LG, the frequency modulation determination circuit LSAT can include an AND gate LSAND as shown in FIG. 2. This is only an example, and the present disclosure is not limited thereto.

[0045] The first input end of the AND gate LSAND is connected to the output end of the low-side comparator CMPLS. The second input end of the AND gate LSAND is connected to the control end of the low-side switch M2. The output end of the AND gate LSAND is connected to the first input end of the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS.

[0046] A second input end of the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS can be connected to an output end of the pulse wave reference input circuit INS.

[0047] The pulse wave reference input circuit INS may include a comparator used as an input comparator CMIN, and may include an input diverter switch Min, a ramp signal generator circuit and an input logic circuit. The ramp signal generator circuit may include a current source CS and an input capacitor Cin, and the input logic circuit may include a flip-flop used as an input flip-flop ING (such as but not limited to an SR flip-flop).

[0048] In the ramp signal generator circuit, the current source CS is connected to a first end of the input capacitor Cin. A second end of the input capacitor Cin is grounded. A first input end of the input comparator CMIN, such as the non-inverting input end, is connected to the first end of the input capacitor Cin of the ramp signal generator circuit. A second input end of the input comparator CMIN is connected to an oscillation circuit (not shown in the figures).

[0049] An output end of the input comparator CMIN is connected to a second input end S of the input flip-flop ING. A first input end R of the input flip-flop ING is connected to an output end of the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS. An inverting output end QB of the input flip-flop ING is connected to an input end of the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS.

[0050] The first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS is connected to an input end of the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS and a control end of the input diverter switch Min.

[0051] A first end of the input diverter switch Min is connected to the first end of the input capacitor Cin and the first input end of the input comparator CMIN. A second end of the input diverter switch Min is grounded.

[0052] The control circuit CTR may include a comparison circuit CMPC and a control logic circuit. The comparison circuit CMPC may include a comparator used as a high-side comparator CMPHS, and the control logic circuit may include a flip-flop used as a control flip-flop CTLG.

[0053] An input end of the high-side detector HSN is connected to the first end of the high-side switch M1 and the second end of the high-side switch M1. The first input end, such as the non-inverting input end, of the high-side comparator CMPHS of the control circuit CTR is connected to an output end of the high-side detector HSN.

[0054] A second input end, such as the inverting input end, of the high-side comparator CMPHS of the control circuit CTR is connected to the output end of the error amplifier ERR.

[0055] The compensation circuit SPS may be connected to a node between the output end of the error amplifier ERR and the second input end, such as the inverting input end, of the high-side comparator CMPHS of the control circuit CTR.

[0056] A first input end R of the control flip-flop CTLG of the control circuit CTR is connected to an output end of the high-side comparator CMPHS. A second input end S of the control flip-flop CTLG of the control circuit CTR is connected to the output end of the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS. An output end Q of the control flip-flop CTLG of the control circuit CTR is connected to an input end of the driver circuit DRV.

[0057] The driver circuit DRV outputs the high-side drive signal HG to the control end of the high-side switch M1 to drive the high-side switch M1, and the driver circuit DRV outputs the low-side drive signal LG to the control end of the low-side switch M2 to drive the low-side switch M2.

[0058] The high-side detector HSN detects the current at the first end of the high-side switch M1 and converts a detected current at the first end of the high-side switch M1 into a voltage to output a high-side detecting voltage signal.

[0059] The error amplifier ERR uses a divided voltage of the output voltage VOUT of the power converter of the present disclosure as an output feedback voltage VOUTFB, and multiplies the difference between the output feedback voltage VOUTFB and the reference voltage VREF by a gain to output the error amplification signal EAO.

[0060] If necessary, the compensation circuit SPS can compensate the error amplification signal EAO output from the output end of the error amplifier ERR, and output a compensated error amplification signal EAO to the second input end, such as the inverting input end, of the high-side comparator CMPHS of the control circuit CTR.

[0061] The first input end, such as the non-inverting input end, of the high-side comparator CMPHS of the control circuit CTR receives a high-side detecting voltage signal VCSHS from the output end of the high-side detector HSN. The second input end, such as the inverting input end, of the high-side comparator CMPHS receives an error amplification signal EAO from the output end of the error amplifier ERR or from the compensation circuit SPS.

[0062] The high-side comparator CMPHS compares the voltage of the high-side detecting voltage signal VCSHS with the voltage of the error amplification signal EAO to output a high-side comparison signal.

[0063] The low-side detector LSN detects the current at the second end of the low-side switch M2 and converts the detected current at the second end of the low-side switch M2 into a voltage to output a low-side detecting voltage signal VCSLS. The first input end, such as the non-inverting input end, of the low-side comparator CMPLS receives the low-side detecting voltage signal VCSLS from the low-side detector LSN. The second input end, such as the inverting input end, of the low-side comparator CMPLS receives the error amplification signal EAO from the output end of the error amplifier ERR.

[0064] The low-side comparator CMPLS compares the voltage of the low-side detecting voltage signal VCSLS with the voltage of the error amplification signal EAO to output a low-side comparison signal.

[0065] The AND gate LSAND of the frequency modulation determination circuit LSAT outputs the blank clock signal BLCLK according to the low-side comparison signal received from the output end of the low-side comparator CMPLS and the low-side drive signal LG received from the control end of the low-side switch M2 (or the output end of the driver circuit DRV).

[0066] When the low-side comparison signal received by the first input end of the AND gate LSAND of the frequency modulation determination circuit LSAT is at a high level, and the low-side drive signal LG received by the second input end of the AND gate LSAND is at a high level, so that the low-side switch M 2 is turned on, the AND gate LSAND outputs a high-level blank clock signal BLCLK.

[0067] On the other hand, in the pulse wave reference input circuit INS, the current source CS supplies an input current to the input capacitor Cin to charge the input capacitor Cin. The voltage signal of the input capacitor Cin is transmitted as a ramp signal VRAMP to a first input end, such as a non-inverting input end, of an input comparator CMIN. The second input end, such as the inverting input end, of the input comparator CMIN receives an oscillation signal VTHOSC from an oscillation circuit.

[0068] The input comparator CMIN compares the voltage of a received ramp signal VRAMP with the voltage of an oscillation signal VTHOSC to output an input comparison signal.

[0069] The input flip-flop ING of the pulse wave reference input circuit INS outputs a pulse wave reference input signal INSS according to the input comparison signal received from the output end of the input comparator CMIN and the clock signal CLK received from the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS.

[0070] As shown in FIG. 5, during the charging process of the input capacitor Cin, a voltage signal of the input capacitor Cin used as a ramp signal VRAMP gradually rises. When the voltage of the ramp signal VRAMP rises to be equal to or higher than the voltage of the oscillation signal VTHOSC, the input comparator CMIN of the pulse wave reference input circuit INS outputs a high-level input comparison signal, such that an input inverting logic signal QBS output from the inverting output end QB of the input flip-flop ING is switched from a high level to a low level.

[0071] Whenever the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS receives the input inverting logic signal QBS from the input flip-flop ING, as shown in FIG. 5, the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS generates a pulse wave in an input diverter switch switching signal DICH output to the control end of the input diverter switch Min.

[0072] Whenever the charging of the input capacitor Cin is completed, the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS can output a high-level input diverter switch switching signal DICH to the control end of the input diverter switch Min to turn on the input diverter switch Min so as to discharge the input capacitor Cin.

[0073] The first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS outputs a first pulse wave signal PU1SOT according to the pulse wave reference input signal INSS received from the input flip-flop ING of the pulse wave reference input circuit INS and the blank clock signal BLCLK received from the AND gate LSAND of the frequency modulation determination circuit LSAT.

[0074] The second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS outputs the clock signal CLK to the second input end S of the control flip-flop CTLG of the control circuit CTR according to the first pulse wave signal PU1SOT received from the first pulse wave signal generator PU1.

[0075] As shown in FIG. 5, whenever the input capacitor Cin is discharged, the second pulse wave signal generator PU2 can output a pulse reset signal to the first input end R of the input flip-flop ING (such as but not limited to an SR flip-flop) to reset an input flip-flop ING.

[0076] The second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS switches the clock signal CLK from a low level at a time point of the input diverter switch switching signal DICH (that is, the time point at which the discharge of the input capacitor Cin ends), and from this point, the next pulse wave starts being generated by the clock signal CLK. At the time, the frequency of the pulse wave of the clock signal CLK is calculated by the following equation:

[0077] $\mathrm{Feq}=I1/\left[C\mathrm{in}\times \left(\mathrm{Vosc}\right)\right];$
in which, Feq represents the frequency of the pulse wave of the clock signal CLK, I1 represents the input current supplied by the current source CS, Cin represents an input capacitor Cin, and Vosc represents the voltage of the oscillation signal VTHOSC.

[0078] The control flip-flop CTLG of the control circuit CTR outputs the control signal PWM according to the high-side comparison signal received from the output end of the high-side comparator CMPHS and the clock pulse CLK received from the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS.

[0079] The driver circuit DRV outputs the high-side drive signal HG to the control end of the high-side switch M1 and the low-side drive signal LG to the control end of the low-side switch M2 according to the control signal PWM received from the control circuit CTR.

[0080] During the working cycle of the on-time signal TON as shown in FIG. 6 (i.e., a signal at the node LX between the first end of the low-side switch M2 and the second end of the high-side switch M1 as shown in FIG. 2, or in practice, the high-side drive signal of the high-side switch M1), the driver circuit DRV as shown in FIG. 2 turns on the high-side switch M1 and simultaneously turns off the low-side switch M2. On the contrary, during the non-working period of the on-time signal TON as shown in FIG. 6, the driver circuit DRV as shown in FIG. 2 turns off the high-side switch M1 and simultaneously turns on the low-side switch M2.

[0081] As shown in FIG. 6, whenever the low-side switch M2 is turned on during a non-working period of the on-time signal TON and the voltage of the voltage signal at the second end of the low-side switch M2 is higher than the voltage of the error amplification signal EAO, the output end of the AND gate LSAND) of the frequency modulation determination circuit LSAT of the low-side feedback circuit LSFB outputs a high-level blank clock signal BLCLK.

[0082] When the duty cycle of the on-time signal TON is greater than a minimum on-time of the high-side switch M1, there is no need to reduce the switching frequency FSW of the high-side switch M1 and the low-side switch M2. At the time, as shown in FIG. 6, the clock signal CLK is a constant frequency signal, and the frequency of each of the plurality of pulse waves of the clock signal CLK is fixed to a preset reference frequency.

[0083] As shown in FIGS. 6 and 7, when the input voltage VIN gradually increases, the duty cycle of the on-time signal TON gradually shortens. When the duty cycle of the on-time signal TON is shortened to be equal to a minimum on-time, the error amplification signal EAO output by the error amplifier ERR gradually decreases. As a result, the width of the pulse wave generated later among the plurality of pulse waves of the blank clock signal BLCLK output by the AND gate LSAND of the frequency modulation determination circuit LSAT of the low-side feedback circuit LSFB is greater.

[0084] When the low-side switch M2 is turned on and the voltage of the voltage signal at the second end of the low-side switch M2 is higher than the voltage of the error amplification signal EAO, the AND gate LSAND of the frequency modulation determination circuit LSAT of the low-side feedback circuit LSFB outputs a high-level blank clock signal BLCLK. On the contrary, when the low-side switch M2 is turned off or the voltage signal at the second end of the low-side switch M2 is not higher than the voltage of the error amplification signal EAO, the AND gate LSAND of the frequency modulation determination circuit LSAT of the low-side feedback circuit LSFB outputs a low-level blank clock signal BLCLK.

[0085] When a predetermined generation time point of the pulse wave of the clock signal CLK falls into a time interval in which the blank clock signal BLCLK is at a high level, the pulse wave signal generator circuit PS delays the generation of the pulse wave of the clock signal CLK to reduce the frequency of the pulse wave in the clock signal CLK, thereby reducing the switching frequency FSW of the high-side switch M1 and the low-side switch M2.

[0086] As shown in FIGS. 6 and 7, when the input voltage VIN coupled to the first end of the high-side switch M1 of the power converter of the present disclosure gradually rises and the duty cycle of the on-time signal TON of the power converter of the present disclosure (i.e., the on-time of the high-side switch M1) is shortened to be equal to a minimum on-time of the high-side switch M1 of the power converter of the present disclosure, the switching frequency FSW of the high-side switch M1 and the low-side switch M2 decreases linearly, so that the output voltage VOUT of the power converter of the present disclosure is maintained at a constant voltage value without overvoltage occurring.

[0087] Reference is made to FIGS. 3, 4, 8 and 9. FIG. 3 is a circuit diagram of a first pulse wave signal generator of a power converter having a stable output voltage according to a third embodiment of the present disclosure, FIG. 4 is a circuit diagram of a second pulse wave signal generator of a power converter having a stable output voltage according to the third embodiment of the present disclosure, and FIG. 8 and FIG. 9 are waveform diagrams of a signal of a power converter having a stable output voltage according to the third embodiment of the present disclosure.

[0088] For example, the first pulse wave signal generator PU1 of the pulse wave signal generator circuit PS As shown in FIG. 2 of the present application may include a first transistor T1, a first resistor R1, a second transistor T2, a third transistor T3, a first Schmitt trigger SHT1, a first NOR gate NOR1, a second NOR gate NOR2, a first NOT gate NOT1 and a first capacitor Cp1 as shown in FIG. 3.

[0089] As shown in FIG. 3, a first end of the first transistor T1 is coupled to a common voltage VCC. A second end of the first transistor T1 is connected to a first end of the first resistor R1. A second end of the first resistor R1 is connected to a first end of the second transistor T2. A second end of the second transistor T2 is grounded.

[0090] A control end of the first transistor T1 and a control end of the second transistor T2 are connected to an output end Q of the input flip-flop ING of the pulse wave reference input circuit INS to receive the pulse wave reference input signal INSS from the output end Q of the input flip-flop ING of the pulse wave reference input circuit INS.

[0091] A first end of the third transistor T3 is coupled to the common voltage VCC.

[0092] An input end of the first Schmitt trigger SHT1 is connected to the node NE1 between the first end of the second transistor T2 and the second end of the first resistor R1, and is connected to a second end of the third transistor T3 and a first end of the first capacitor Cp1. A second end of the first capacitor Cp1 is grounded.

[0093] A first input end of the first NOR gate NOR1 is connected to an output end of the first Schmitt trigger SHT1. A second input end of the first NOR NOR1 is connected to the output end Q of the input flip-flop ING of the pulse wave reference input circuit INS to receive the pulse wave reference input signal INSS from the pulse wave reference input circuit INS. A third input end of the first NOR gate NOR1 is connected to the AND gate LSAND of the frequency modulation determination circuit LSAT of the low-side feedback circuit LSFB, and the AND gate LSAND of the frequency modulation determination circuit LSAT receives the blank clock signal BLCLK.

[0094] A first input end of the second NOR gate NOR2 is connected to an output end of the first NOR gate NOR1. A second input end of the second inverter NOR2 is connected to the output end Q of the input flip-flop ING of the pulse wave reference input circuit INS to receive the pulse wave reference input signal INSS from the pulse wave reference input circuit INS. An output end of the second NOR gate NOR2 is connected to the input end of the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS.

[0095] An input end of the first NOT gate NOT1 is connected to the output end of the first NOR gate NOR1. An output end of the first NOT gate NOT1 is connected to a control end of the third transistor T3.

[0096] For example, the second pulse wave signal generator PU2 of the pulse wave signal generator circuit PS As shown in FIG. 2 of the present application may include a fourth transistor T4, a second resistor R2, and a fifth transistor T5, a sixth transistor T6, a second Schmitt trigger SHT2, a third NOR gate NOR3, a fourth NOR gate NOR4, a second NOT gate NOT2 and a second capacitor Cp2 as shown in FIG. 4.

[0097] As shown in FIG. 4, a first end of the fourth transistor T4 is coupled to the common voltage VCC. A control end of the fourth transistor T4 as shown in FIG. 4 is connected to the output end of the second NOR gate NOR2 of the first pulse wave signal generator PU1 as shown in FIG. 3.

[0098] A second end of the fourth transistor T4 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to a first end of the fifth transistor T5. A control end of the fifth transistor T5 is connected to an output end of the second inverter NOR2 of the first pulse wave signal generator PU1 as shown in FIG. 3. The second end of the fifth transistor T5 is grounded.

[0099] A first end of the sixth transistor T6 is coupled to the common voltage VCC.

[0100] An input end of the second Schmitt trigger SHT2 is connected to the node NE2 (the second voltage signal NES2 of the node N E2 changes as shown in FIG. 7 or FIG. 8) between the first end of the fifth transistor T5 and the second end of the second resistor R2, and connected to a second end of the sixth transistor T6 and a first end of the second capacitor Cp2. A second end of the second capacitor Cp2 is grounded.

[0101] A first input end of the third NOR gate NOR3 is connected to an output end of the second Schmitt trigger SHT2. A second input end of the third NOR gate NOR3 is connected to the output end of the second NOR gate NOR2 of the first pulse wave signal generator PU1 as shown in FIG. 3.

[0102] A first input end of the fourth NOR gate NOR4 is connected to an output end of the third NOR gate NOR3. A second input end of the fourth NOR gate NOR4 is connected to the output end of the second NOR gate NOR2 of the first pulse wave signal generator PU1 as shown in FIG. 3. An output end of the fourth inverter NOR4 is connected to the second input end S of the control flip-flop CTLG of the control circuit CTR.

[0103] An input end of the second NOT gate NOT2 is connected to the output end of the third NOR gate NOR3. An output end of the second NOT gate NOT2 is connected to a control end of the sixth transistor T6.

[0104] As shown in FIG. 8, when the pulse wave reference input signal INSS changes from a high level to a low level, since the first voltage signal NES1 at the node NE1 between the first end of the second transistor T2 and the second end of the first resistor R1 is at a low level, the first Schmitt trigger SHT1 outputs a high-level first Schmidt trigger signal.

[0105] When the first input end of the first NOR gate NOR1 receives the high-level first Schmitt trigger signal from the output end of the first Schmitt trigger SHT1, the second input end of the first NOR gate NOR1 receives a low-level pulse wave reference input signal INSS, the third input end of the first NOR gate NOR1 receives a low-level blank clock signal BLCLK, and the output end of the first NOR gate NOR1 outputs a low-level first NOR gate signal.

[0106] When the first input end of the second NOR gate NOR2 receives the low-level first NOR gate signal from the output end of the first NOR gate NOR1 and the second input end of the second NOR gate NOR2 receives the low-level pulse wave reference input signal INSS from the pulse wave reference input circuit INS, the output end of the second NOR gate NOR2 outputs a high-level first pulse wave signal PU1SOT.

[0107] When the voltage of the first voltage signal NES1 is higher than a Schmitt voltage threshold SMTH of the first Schmitt trigger SHT1, a first NOR gate signal output from the output end of the first NOR gate NOR1 changes from a low level to a high level, and the first pulse wave signal PU1SOT output from the output end of the second NOR gate NOR2 changes from a high level to a low level.

[0108] Or, as shown in FIG. 9, when the first input end of the first NOR gate NOR1 receives the low-level first Schmitt trigger signal from the output end of the first Schmitt trigger SHT1, the second input end of the first NOR gate NOR1 receives the low-level pulse wave reference input signal INSS, the third input end of the first NOR gate NOR1 receives the high-level blank clock signal BLCLK, and the output end of the first NOR gate NOR1 outputs the low-level first NOR gate signal.

[0109] Until the first input end of the first NOR gate NOR1 receives the low-level first Schmitt trigger signal from the output end of the first Schmitt trigger SHT1, the second input end of the first NOR gate NOR1 receives the low-level pulse wave reference input signal INSS, and the third input end of the first NOR gate NOR1 receives the blank clock signal BLCLK which changes from a high level to a low level, the first pulse wave signal PU1SOT output from the output end of the second NOR gate NOR2 changes from a high level to a low level. Accordingly, the pulse width of the first pulse wave signal PU1SOT output from the output end of the second NOR gate NOR2 is controlled by the blank clock signal BLCLK, so as to control the pulse width of the clock signal CLK output by the second pulse wave signal generator PU2 to the control circuit CTR.

[0110] Reference is made to FIG. 10, which is a waveform diagram of a signal of a power converter having a stable output voltage and a conventional power converter according to the first to third embodiments of the present disclosure.

[0111] In the startup state of a conventional power converter, even if there is a soft-start circuit to assist in switching the high-side switch and the low-side switch, since the initial output voltage of the conventional power converter is zero when it is turned on, the duty cycle of the high-side drive signal of the high-side switch is a low duty cycle and the frequency reduction operation is not performed at this time.

[0112] When the on-time of the high-side switch of the conventional power converter is a minimum on-time, a normal switching frequency indicator line CU30 of the conventional power converter as shown in FIG. 10 maintains switching of the high-side switch and the low-side switch at a fixed frequency. As a result, the output voltage VOUT of the conventional power converter will have an overvoltage event when being turned on, such as an output voltage curve CU10 shown in FIG. 10, while the output current IL of the conventional power converter will cause an overcurrent event during startup, such as an output current curve CU20 shown in FIG. 10.

[0113] When an overvoltage occurs in the output voltage VOUT of the conventional power converter, the switching frequency FSW of the conventional power converter has frequency-hopping, such as a switching frequency curve CU31 shown in FIG. 10. At this time, the output voltage VOUT of the conventional power converter is not stable, such as the output voltage curve CU11 shown in FIG. 10, and the output current IL is unstable, as an output current curve CU21 shown in FIG. 10.

[0114] When the power converter of the present disclosure is turned on, as the duty cycle of the high-side drive signal of the high-side switch increases, the switching frequency FSW of the power converter of the present disclosure changes linearly as a switching frequency curve CU32 shown in FIG. 10, so that no overvoltage event will occur in the output voltage VOUT when the power converter of the present disclosure is turned on, such as an output voltage curve CU12 shown in FIG. 10, and when the power converter of the present disclosure is turned on, the output current IL is stable as an output current curve CU22 shown in FIG. 10.

[0115] In summary, the present disclosure provides a power converter having a stable output voltage. The switching frequency of the high-side switch and the low-side switch of the power converter of the present disclosure can be modulated according to the output voltage of the power converter of the present disclosure, including automatically reducing the switching frequency of the high-side switch and the low-side switch when the on-time of the high-side switch reaches a minimum on-time, so that the output voltage of the power converter of the present disclosure is maintained at a stable value.

[0116] The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

[0117] The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.