US 12,633,817 B2Grant

Correction circuit

Issue Date:2026-05-19

•20 Claims

•17 Drawing Sheets

Abstract

A correction circuit for correcting one or more errors in a digitized current signal, the digitized current signal being a digital representation of an analog current signal of a current flow through an energy storage element, wherein the correction circuit is configured to correct the one or more errors in the digitized current signal by comparing the digitized current signal to the analog current signal, and correcting the digitized current signal based on the outcome of the comparison.

Metadata

Assignee

Renesas Design (UK) Limited

Inventors

Codrin Hora
Guillaume De Cremoux
Vladislav Vasilev

Application Information

Application Number:US 18/361,240

Filing Date:2023-07-28

Priority Date:2023-07-28

Art Unit:2838

Classifications

IPC:

H02M3/158H02M1/00H02M1/088H02M3/157

Field of Search:

H02M 3/157H02M 3/158H02M 3/56H02M 3/1563H02M 3/586H02M 1/088H02M 1/084H02M 1/0845H02M 1/082H02M 1/0009H02M 1/0003

Patent Drawings (17 sheets)

Description

[0001] The present disclosure relates to a correction circuit for correcting one or more errors in a digitized current signal. In particular, the present disclosure relates to a correction circuit as may be applied to a switching converter.

Background

[0002] FIG. 1 is a schematic of a digital buck converter 100 comprising a power stage 101, analog to digital converters (ADC) 102, 104, 106 and a controller 108. The power stage 101 comprises switches 110, 112, an inductor 114 and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates and output voltage VOUT.

[0003] While the power stage 101 and passive components (the inductor 114 and the capacitor 116) remain the same as for an analog buck converter, the ADC 102 converts the output voltage VOUT into a digital number. Optionally, the inductor current IL of the inductor 114, and the input voltage VIN can also be converted from analog to digital, depending on the digital control method.

[0004] We distinguish:

- [0005] The switching frequency (FSW) of the buck converter 100, for example 2 MHz. FSW is equal to 1/TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage.
- [0006] The processing frequency of the digital controller 108 (FS), for example about 100 MHz. FS is equal to 1/TS, where TS is the processing period of the controller 108. FS can also optionally be the sampling frequency of ADC 102.

[0007] Digital systems, such as the digital buck converter 100, may use a digital signal that is representative of a current flow through an energy storage element during operation. For example, a digitized current signal may be required by a controller for control of the switching operation of the digital switching converter.

[0008] In the present example, the digitized current signal is a digitized inductor current DIL, as provided by the ADC 104 converting an analog current signal indicative of the inductor current IL into a digital format. It will be appreciated components and methods other than the ADC 104 may be used to generate the digitized inductor current DIL. The digitized inductor current DIL may be generated using sensor based or sensor-less techniques. The digitized inductor current DIL is provided to the controller 108, which uses the information on the inductor current IL to control the switching operation of the power switches 110, 112. The dependency of the control scheme on the inductor current means such a system may be referred to as a current mode converter using current mode control.

[0009] For effective operation of the buck converter, or any other digital system that uses a digitized current signal during operation, it is desirable that the digitized current signal DIL accurately represents the analog current signal IL. With reference to the buck converter 100, it is desirable that the digitized inductor current DIL accurately represents the inductor current IL. It should be noted that the analog current signal and the inductor current may both be denoted by the variable “IL” to denote that the analog current signal is representative of the current flow through the inductor. It will be appreciated that the analog current signal IL may not be a current signal itself, but may, for example, be a voltage signal that is representative of a current signal.

Summary

[0010] It is desirable to provide a system for improving the accuracy of a digitized current signal, when compared to existing methods.

[0011] According to a first aspect of the disclosure there is provided a correction circuit for correcting one or more errors in a digitized current signal, the digitized current signal being a digital representation of an analog current signal of a current flow through an energy storage element, wherein the correction circuit is configured to correct the one or more errors in the digitized current signal by comparing the digitized current signal to the analog current signal, and correcting the digitized current signal based on the outcome of the comparison.

[0012] Optionally, the digitized current signal is provided by a current synthesizer.

[0013] Optionally, the correction circuit is configured to generate a correction signal that is dependent on the outcome of the comparison, and provide the correction signal to the current synthesizer, the correction signal being suitable for correcting the one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on the outcome of the comparison.

[0014] Optionally, the correction circuit is configured to correct an offset error between the digitized current signal and the analog current signal.

[0015] Optionally, the correction circuit is configured to compare the digitized current signal to the analog current signal to determine the offset error, and correct the digitized current signal using the determined offset error.

[0016] Optionally, the correction circuit is configured to determine the offset error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, calculating a first duration between the first time step and the second time step, determining a first slope of at least one of the digitized current signal and the analog current signal, multiplying the first duration by the first slope, thereby determining the offset error.

[0017] Optionally, the first digital threshold is approximately equal to a digitized first analog threshold.

[0018] Optionally, the correction circuit comprises a comparator configured to provide an output that is indicative of analog current signal crossing the first analog threshold, the output being used to determine the second time step.

[0019] Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal.

[0020] Optionally, the correction circuit is configured to compare the digitized current signal to the analog current signal to determine the relative slope error, and correct the digitized current signal using the relative slope error, as determined.

[0021] Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, detecting a third time step when the digitized current signal crosses a second digital threshold, detecting a fourth time step when the analog current signal crosses a second analog threshold, calculating a first digital slope delay between the first time step and the third time step, calculating a first analog slope delay between the second time step and the fourth time step, dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtracting one from the first delay parameter, thereby determining the relative slope error.

[0022] Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal.

[0023] Optionally, the correction circuit is configured to correct the relative slope error prior to correcting the offset error.

[0024] Optionally, the correction circuit is configured to compare the digitized current signal to the analog current signal to determine the relative slope error and the offset error, and correct the digitized current signal using the relative slope error and offset error, as determined.

[0025] Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, detecting a third time step when the digitized current signal crosses a second digital threshold, detecting a fourth time step when the analog current signal crosses a second analog threshold, calculating a first digital slope delay between the first time step and the third time step, calculating a first analog slope delay between the second time step and the fourth time step, dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtracting one from the first delay parameter, thereby determining the relative slope error.

[0026] Optionally, the correction circuit is configured to determine the offset error by calculating a first duration between the first time step and the second time step, determining a first slope of the analog current signal by calculating an analog threshold difference by subtracting the second analog threshold from the first analog threshold, and dividing the analog threshold difference by the first analog slope delay, and multiplying the first slope of the analog current signal by the first duration, thereby determining the offset error.

[0027] Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal during operation of a switching converter comprising the energy storage element.

[0028] Optionally, the switching converter is one of a buck converter, a boost converter and a buck-boost converter.

[0029] Optionally, the energy storage element comprises an inductor.

[0030] Optionally, the correction circuit is configured to correct the one or more errors in the digitized current signal two or more times during operation of the switching converter, or in response to an external signal, or in response to one of the one or more errors exceeding a threshold value, or in response to a mode change of the switching converter, or in response to a transient.

[0031] Optionally, the correction circuit is configured to correct the one or more errors in the digitized current signal periodically or non-periodically during operation of the switching converter.

[0032] According to a second aspect of the disclosure there is provided a method of correcting one or more errors in a digitized current signal using a correction circuit, the digitized current signal being a digital representation of an analog current signal of a current flow through an energy storage element, the method comprising comparing the digitized current signal to the analog current signal, and correcting the digitized current signal based on the outcome of the comparison.

[0033] It will be appreciated that the method of the second aspect may include features set out in the first aspect and can incorporate other features as described herein.

Brief Description of the Drawings

[0034] The disclosure is described in further detail below by way of example and with reference to the accompanying drawings, in which:

[0035] FIG. 1 is a schematic of a digital buck converter;

[0036] FIG. 2 is a graph of the inductor current varying with time during operation of the buck converter of FIG. 1;

[0037] FIG. 3 is a timing graph showing an example of how parameters relating to the operation of the buck converter vary with time during operation;

[0038] FIG. 4 shows timing graphs showing examples of how parameters relating to the operation of the buck converter vary with time during operation, and for different inductor current values;

[0039] FIG. 5 is a timing graph showing representative waveforms of the digital inductor current and the inductor current IL as a result of a load transient during operation of the buck converter;

[0040] FIG. 6(a) is a schematic of a correction circuit in accordance with a first embodiment of the present disclosure, FIG. 6(b) is a schematic of the correction circuit and an energy storage element in accordance with a second embodiment of the present disclosure;

[0041] FIG. 7 is a timing graph showing the digitized current signal and the analog current signal during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 6(a);

[0042] FIG. 8 is a timing graph showing the digitized current signal and the analog current signal during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 6(a);

[0043] FIG. 9(a) is a timing graph of the digitized inductor current during operation of an example embodiment of the present disclosure, for example in relation to the apparatus presented in FIG. 6(a), FIG. 9(b) is a timing graph of the digitized inductor current during operation of an example embodiment of the present disclosure, for example in relation to the apparatus presented in FIG. 6(a);

[0044] FIG. 10 is a timing graph showing the digitized current signal and the analog current signal during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 6(a);

[0045] FIG. 11 is a schematic of a specific embodiment of the correction circuit and the switching converter, in accordance with a third embodiment of the present disclosure;

[0046] FIG. 12 is a timing showing the digitized current signal and the analog current signal during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 11;

[0047] FIG. 13 is a timing graph showing simulation results of a practical implementation of a known system that uses a low bandwidth correction mechanism;

[0048] FIG. 14(a) is a timing graph showing simulations results of a practical implementation of the system illustrated in FIG. 11, FIG. 14(b) is the timing graph of FIG. 14(a) over a shorter time scale; and

[0049] FIG. 15 is a schematic of a comparator unit that may be used for one or both of the two comparator units of FIG. 11.

Detailed Description

[0050] FIG. 2 is a graph of the inductor current IL varying with time during operation of the buck converter 100 of FIG. 1. During operation, the inductor 114 switches between coupling to the input voltage VIN via the switch 110 (the magnetization phase, labelled by numeral 202) and coupling to ground PGND via the switch 112 (the demagnetization phase, labelled by numeral 204).

[0051] The graph shows a first trace 206 showing an idealised inductor current. The inductor current IL may have an idealised shape that made of straight lines and is as is used in U.S. Pat. No. 9,419,627B2 and U.S. Pat. No. 9,667,260B2. The graph also shows a second trace 208 showing a more realistic current profile where the slope of each phase has a non-linear shape (exponential decay for the falling slope).

[0052] Note that the timing diagrams are continuous time and continuous data to aid in the clarity of the explanation.

[0053] For some switching converters, a straight-line approximation of the inductor current IL can be sufficient for an effective control scheme. However, having a more accurate, non-linear, digitized inductor current DIL waveform is desirable as it can ensure more precise current control. Furthermore, a digitized inductor current DIL having improved accuracy can be used for additional applications beyond just regulation, such as for over current protection.

[0054] There are several suitable methods for the generation of the digitized inductor current DIL, as will be known to the skilled person. For example, the digitized inductor current DIL may be generated using the ADC 104 as described in relation to FIG. 1, or may be generated using a current synthesizer. The following description relates to the generation of the digitized inductor current DIL using a current synthesizer.

[0055] In the discrete time domain (so clocked at TS, which is the processing period of the controller 108), the digitized inductor current DIL during the magnetization phase, may be represented as follows:

[0056]

\begin{matrix} D I L [n] = D I L [n - 1] - \frac{T S}{L} \times R_{MAG} \cdot D I L [n - 1] + \frac{T S}{L} \times (DIN - DOUT) & (1) \end{matrix}

[0057] The digitized inductor current DIL during the demagnetization phase may be represented as follows:

[0058]

\begin{matrix} D I L [n] = D I L [n - 1] - \frac{T S}{L} \times R_{DEMAG} \cdot D I L [n - 1] - \frac{T S}{L} \times (DOUT) & (2) \end{matrix}

[0059] The variable terms R_MAGand R_DEMAGare thus the non-linear corrections to ideal slopes for the magnetization phase, and the demagnetization phase, respectively. L is the inductance of the inductor 114, DIN is a digital input voltage signal, DOUT is a digital output voltage signal, and n is an integer.

[0060]

\begin{matrix} R_{MAG} = DCR + RHS & (3) \end{matrix}

\begin{matrix} R_{DEMAG} = DCR + RLS & (4) \end{matrix}

where RHS is the on-resistance of the transistor 110, RLS is the on-resistance of the transistor 112 and DCR is the series resistance of the inductor 114.

[0061] It will be appreciated that the digitized inductor current DIL may have the profile shown by the trace 206 by using a straight line approximation by setting R_MAG=R_DEMAG=0 for equations (1) and (2).

[0062] A current synthesiser may be used to generate the digitized inductor current DIL using equations (1) to (4).

[0063] By way of example, and with reference to equations (1)-(4), it is evident that achieving an accurate digitized inductor current DIL depends on accurate values for the parameters used in the equations (for example L, RHS, RLS, DCR, DIN, DOUT). Other sources of error may include, but are not limited to:

- [0064] Driver speed.
- [0065] Dead-times between LS and HS switch conduction
- [0066] Temperature variations of resistances
- [0067] Inductor aging

[0068] Temperature-induced errors tend to be slowly varying. Errors in digitized inductor current DIL related to driver speed change with a time constant of L/R, where R is as follows:

[0069]

\begin{matrix} R = D \cdot (RHS + DCR) + (1 - D) \cdot (RLS + DCR) & (5) \end{matrix}

where D is the duty cycle of the buck converter 100. Errors related to the dead-zone can occur withing one clock cycle. The accumulations of these errors can introduce large discrepancies between the digitized inductor current DIL and the IL (up to 1.3 A observed in simulations).

[0070] FIG. 3 is a timing graph showing an example of how parameters relating to the operation of the buck converter 100 vary with time during operation. A trace 300 shows the inductor current IL as it varies with time; a trace 302 shows the pulse width modulation (PWM) signal varying with time; and a trace 304 showing a voltage at the switching node SW. The PWM signal is used to control the switching operation of the buck converter 100, and the use of PWM in this context will be well known to the skilled person.

[0071] The timing graph of FIG. 3 shows a simplified and exaggerated view of the driver delay (Tdly1, Tdly2) and dead-zones (Tdz1, Tdz2) for a particular inductor current IL.

[0072] In this case, there is a delay between rising edge of PWM signal and the power switches reacting to this change (Tdly1). A similar (but not equal) delay is present on the falling edge of the PWM signal (Tdly2).

[0073] From an analogue point of view, we consider MAG, denoting the magnetization phase, to be the portion of time during which the inductor current IL is rising. The inductor current IL is close to zero.

[0074] From equations (1) and (2), it can be seen that the expressions during the magnetization phase differs from that during demagnetization phase therefore it is desirable to accurately know the timing of the transition between the phases. If the PWM signal is used to identify the time of the transition it is evident that that will introduce errors due to the Tdly1 and Tdly2.

[0075] Furthermore, the different slope of the inductor current IL during the dead-zones, Tdz1 and Tdz2, compared to the slope during the rest of the magnetization phase (where SW=VIN) is not taken into account in the equations (1) and (2). The errors mentioned above are highly dependent on the IL, VIN, VOUT and Temperature.

[0076] FIG. 4 shows timing graphs showing examples of how parameters relating to the operation of the buck converter 100 vary with time during operation, and for different inductor current IL values.

[0077] FIG. 4 shows how the effective MAG duration changes with the inductor current IL (for a fixed demanded PWM duration). More precisely, the effective MAG duration changes depending on the valley current (IL_valley) and the peak current (IL_peak) of the inductor current IL at the end of MAG and end of DEMAG stages. This is due to the current conduction through the freewheeling body diode which is dependent on the polarity of the inductor current IL. The change of switching node SW voltage depends on the polarity of the inductor current IL at end of DEMAG and end of MAG.

[0078] It is possible to correct for these errors (and more) in a feed-forward fashion which can reduce the magnitude of (DIL-IL) error. However, even small residual errors can be integrated and ultimately lead to increasing discrepancies over time.

[0079] FIG. 5 is a timing graph showing representative waveforms of the digital inductor current DIL (a trace 500) and the inductor current IL (a trace 502) as a result of a load transient during operation of the buck converter 100.

[0080] After the transient, there is a mismatch between the waveforms. For single phase converters, the errors between the DIL and IL may still permit functioning of the system, but are nonetheless undesirable due to a degradation of performance under transient loads and an unsuitability of the digitized inductor current DIL for use in applications such as overcurrent protection. For multiphase converters, mismatch between the phase currents is highly undesirable as they can degrade transient performance and efficiency. As the DIL to IL errors are independent of each other, the effective mismatch between the inductor current IL of two different converter phases can be doubled with respect to the DIL to IL mismatch of a single phase converter.

[0081] It is desirable the digitized inductor current DIL has the following properties:

- [0082] Accurate average value compared to IL
- [0083] Accurate ripple magnitude compared to IL
- [0084] Rapid correction for any introduced errors.
- [0085] No divergence over time with respect to IL
- [0086] Similar non-linear shape as IL

[0087] FIG. 6(a) is a schematic of a correction circuit 600 for correcting one or more errors in a digitized current signal DIL, in accordance with a first embodiment of the present disclosure. The digitized current signal DIL is a digital representation of an analog current signal IL of a current flow through an energy storage element 602.

[0088] It should be noted that the variables “IL” and “DIL” are used for consistency with the previous description where the energy storage element comprises an inductor that is part of a buck converter. In the present embodiment, the energy storage element 602 is considered generally. In specific embodiments, the energy storage element 602 may comprise an inductor, or a different circuit component in accordance with the understanding of the skilled person.

[0089] During operation, the correction circuit 600 corrects the one or more errors in the digitized current signal DIL by comparing the digitized current signal DIL to the analog current signal IL and then correcting the digitized current signal DIL based on the outcome of the comparison.

[0090] The digitized current signal DIL may be provided by a current synthesizer 612. The correction circuit 600 may be configured to generate a correction signal 601 that is dependent on the outcome of the comparison, and to provide the correction signal 601 to the current synthesizer 612.

[0091] The correction signal 601 is a signal that is suitable for correcting the one or more errors in the digitized current signal DIL when received by the current synthesizer 612. Therefore, during operation, the current synthesizer 612 uses the correction signal 601 to correct the digitized current signal DIL based on the outcome of the comparison.

[0092] The correction signal 601 may include information relating to a mismatch between the two signals IL, DIL, as will be the case if the digitized current signal DIL is not an accurate digital representation of the analog current signal IL. The current synthesizer 612 may then use the information provided by the comparison signal 601 to adjust, or otherwise correct, the digitized current signal DIL to decrease the mismatch and ensure that it more accurately represents the analog current signal IL digitally.

[0093] If the digitized current signal DIL is already a sufficiently accurate representation of the analog current signal IL, as may be defined by a threshold, then the mismatch as indicated by the correction signal 601 may be suitably small such that no correction is required to be applied by the current synthesiser 612.

[0094] FIG. 6(b) is a schematic of the correction circuit 600 and the energy storage element 602 in accordance with a second embodiment of the present disclosure. In the present embodiment, the energy storage element 602 is a component of a switching converter 604 which comprises at least one power switch 606.

[0095] In the present embodiment, the correction circuit 600 corrects the one or more errors in the digitized current signal DIL during operation of the switching converter 604. The switching converter 604 may be a buck converter, a boost converter, or a buck-boost converter.

[0096] The correction circuit 600 may correct the one or more errors in the digitized current signal DIL on one or more occasions. In a specific embodiment, the correction may be undertaken periodically or non-periodically. In a further embodiment, the correction may be undertaken in response to an external signal; in response to at least one of the errors exceeding a threshold value; in response to a transient; or in response to a mode change of the switching converter. In further embodiments, the correction may be applied based on one or more of the above conditions.

[0097] It will be appreciated that the correction process may be applied more than once during operation of the overall system comprising the energy storage element 602. This may be necessary if an event occurs that results in an increase in the mismatch between the digitized current signal DIL and the analog current signal IL, such as a transient.

[0098] In a specific embodiment, the correction circuit 600 may be configured to correct an offset error between the digitized current signal DIL and the analog current signal IL.

[0099] FIG. 7 is a timing graph showing the digitized current signal DIL and the analog current signal IL during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 6(a). In the present example, there is an offset error (denoted by ΔI) between the digitized current signal DIL (a trace 700) and the analog current signal IL (a trace 702).

[0100] As discussed previously, continuous time and value representations for the digitized current signal DIL are used to aid the clarity of the explanation. However, in reality the digitized current signal DIL comprises values that vary with discrete time steps.

[0101] The following description assumes that the energy storage element 602 is an inductor that is used as part of a buck converter. However, it will be appreciated that the concept is applicable to other switching converter topologies including, but not limited to boost converters, buck-boost converters and multi-switch converters, in accordance with the understanding of the skilled person.

[0102] With reference to FIG. 7, the waveforms IL, DIL are phase aligned because the digitized inductor current DIL is a digital representation of the analog inductor current IL. Furthermore, the slew rates of the digitized inductor current DIL and the analog inductor current IL are equal during the demangetization phase (denoted by “DEMAG”), which is also assumed to be true during the magnetization phase (denoted by “MAG”). The slew rates are denoted by “SR” and have units of amps per unit time (for example A/s, where “A” denotes amperes and “s” denotes seconds). The slew rates may also be referred to as “slopes”.

[0103] The offset error ΔI indicates a mismatch between the average levels of the digitized current signal DIL and the analog current signal IL, which may be referred to as their direct current (DC) levels. For an accurate representation of the analog current signal IL by the digitized current signal DIL, the offset error ΔI should be approximately equal to zero.

[0104] In relation to a specific embodiment of the present disclosure, to correct for the offset error ΔI, the correction circuit 600 compares the digitized current signal DIL to the analog current signal IL to determine the offset error ΔI. Using this information the correction circuit 600 then applies a correction to the digitized current signal DIL to reduce the offset error ΔI to approximately zero, thereby correcting the digitized current signal DIL.

[0105] In the present example, a digital threshold DISET1 has its analog representation ISET1 obtained via a DAC 704 receiving the threshold DISET1 to generate the analog threshold ISET1 in FIG. 7. The digital threshold DISET1 is approximately equal to the analog threshold ISET1 because the two signals represent the same quantity in different domains. Therefore, the thresholds DISET1, ISET1 are aligned in FIG. 7.

[0106] The digital threshold DISET1 may be an arbitrary threshold between the peak of the digitized inductor current DIL and valley of the digitized inductor current DIL), with the analog threshold ISET1 being similarly defined in relation to the analog inductor current IL.

[0107] A point P1 is obtained from the digitized inductor current DIL (a digital signal) crossing a digital threshold DISET1. It will be appreciated that this is a digital comparison.

[0108] A point P2 is obtained from the analog inductor current IL (a real, analogue signal) crossing a real threshold ISET1. This an analogue comparison will result in a real event (such as a comparator output).

[0109] In a specific embodiment, the correction circuit 600 may comprises a comparator (not shown) configured to provide an output that is indicative of the analog current signal IL crossing the threshold ISET1, with the output being used to determine the time step t2.

[0110] Using the two comparison points P1, P2 the offset ΔI between the DIL and IL waveforms can be determined.

[0111] In a specific embodiment, the offset error ΔI is determined by the correction circuit 600, initially, detecting a time step t1 at the point P1 when the digitized current signal DIL crosses a digital threshold DISET1; detecting a time step t2 at the point P2 when the analog current signal IL crosses an analog threshold ISET1; and then calculating a duration ΔT between the two time steps. ΔT may be calculated by subtraction the time step t2 from the time step t1.

[0112] Furthermore, the correction circuit 600 is configured to determine a slope SR of one of the signals IL, DIL. In the present embodiment, the slopes are equal and therefore the slope SR can be determined from either of the signals DIL, IL.

[0113] During operation, the correction circuit 600 then determines the offset error ΔI using the following relationship between the slope SR and the duration ΔT.

[0114]

\begin{matrix} Δ I = SR \cdot Δ T & (6) \end{matrix}

[0115] If the SR and ΔT can be measured (or are known otherwise), the offset between the waveforms can be corrected. If ΔI=0, the two waveforms, DIL and IL, are aligned, meaning the DIL representation of IL is accurate.

[0116] If the waveforms IL, DIL are spaced apart such that the analog inductor current IL does not cross the threshold ISET1, an accurate value for the offset can be determined by first applying a coarse correction in an attempt to bring the two waveforms DIL, IL close enough for a measurement to be taken.

[0117] In a further specific embodiment, the correction circuit 600 may be configured to correct a relative slope error between the digitized current signal DIL and the analog current signal IL.

[0118] FIG. 8 is a timing graph showing the digitized current signal DIL and the analog current signal IL during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 6(a). In the present example, there is a relative slope error between the digitized current signal DIL (a trace 800) and the analog current signal IL (a trace 802).

[0119] As for FIG. 7, FIG. 8 shows the digitized current signal DIL with a continuous time representation, and the following example will be described in relation to a buck converter.

[0120] In the present example, the slopes are unequal. The slope of the digitized inductor current DIL is labelled “SR_DIL” and the slope of the analog inductor current IL is labelled “SR_IL”.

[0121] In relation to a specific embodiment of the present disclosure, to correct for the relative slope error, the correction circuit compares the signals IL, DIL to determine the relative slope error SR_ERR. Using this information the correction circuit 600 then applies a correction to the digitized current signal DIL to reduce the relative slope error SR_ERR to be approximately equal to zero, thereby correcting the digitized current signal DIL.

[0122] In the present example the threshold ISET1 and DISET1 are as described in relation to FIG. 7. In the present example, a digital threshold ISET2 has its analog representations ISET2 obtained via a DAC 804 receiving the threshold DISET2 to generate the analog threshold ISET2 in FIG. 8. The digital threshold DISET2 is approximately equal to the analog threshold ISET2 because the two signals represent the same quantity in different domains. Therefore, the thresholds DISET2, ISET2 are aligned in FIG. 8.

[0123] A point P3 is obtained from the digitized inductor current DIL (a digital signal) crossing a digital threshold DISET2. It will be appreciated that this is a digital comparison.

[0124] A point P4 is obtained from the analog inductor current IL (a real, analogue signal) crossing a real threshold ISET2. This an analogue comparison will result in a real event (such as a comparator output).

[0125] In a specific embodiment, the relative slope error SR_ERR is determined by the correction circuit 600, detecting the time steps t1 and t2 as described in relation to FIG. 7; detecting a time step t3 at the point P3 when the digitized current signal DIL crosses the digital threshold DISET2; detecting a time step t4 at the point P4 when the analog current signal IL crosses the analog threshold ISET2; calculating a digital slope delay ΔT_DIL between the time steps t1, t3; calculating an analog slope delay ΔT_IL between the time steps t2, t4; and dividing the slope delays ΔT_DIL, ΔT_IL to calculate the relative slope error SR_ERR.

[0126] We may define the following equations relating to the thresholds:

[0127]

\begin{matrix} Δ ISET = ISET 1 - ISET 2 & (7) \end{matrix}

\begin{matrix} Δ DISET = DISET 1 - DISET 2 & (8) \end{matrix}

[0128] As described previously, the three delay measurements ΔT, ΔT_DIL, ΔT_DIL can be derived from the results of the digital comparisons of the digitized inductor current DIL with the digital thresholds DISET1, DISET and the analog comparisons of the analog inductor current IL with the analog thresholds ISET1, ISET2.

[0129] The relative slope error SR_ERR may be calculated as follows:

[0130]

\begin{matrix} SR_ERR = \frac{SR_DIL - SR_IL}{SR_IL} = \frac{ΔT_IL}{ΔT_DIL} - 1 & (9) \end{matrix}

where SR_DIL is the slope of the digitized inductor current DIL, and SR_IL is the slope of the analog inductor current IL.

[0131] The value of relative slew rates of the analog inductor current IL and the digitized inductor current DIL is provided by the relative slope error SR_ERR and can be used to apply a correction to the digitized inductor current DIL signal to align its slope SR_DIL with the slope of the analog inductor current SR_IL.

[0132] There are several methods available to adjust the slope SR_DIL, as will be clear to the skilled person. For example, one option, and with reference to equations (1) and (2) is to change the L parameter value used in the expression used to compute DIL[n]. L denotes the inductance of the inductor of the energy storage element 602.

[0133] In a further embodiment, the correction circuit 600 may be configured to correct the relative slope error and the offset error. For example, the correction circuit 600 may be configured to compare the digitized current signal DIL to the analog current signal IL to determine the offset and relative slope errors, and then correct the digitized current signal DIL based on the errors, as determined.

[0134] In a specific embodiment, the expressions (1) and (2) can be modified as follows to allow the corrections for error and slope to be accounted for in the generation of the digitized inductor current DIL[n]:

[0135]

\begin{matrix} D I L [n] = D I L [n - 1] + \frac{T S}{L \times SR_ERR} \times (DIN - DOUT) - \frac{T S}{L \times SR_ERR} \times R_{MAG} \cdot D I L [n - 1] - Δ I & (10) \end{matrix}

D I L [n] = D I L [n - 1] + \frac{T S}{L \times SR_ERR} \times (DIN - DOUT)

\begin{matrix} D I L [n] = D I L [n - 1] - \frac{T S}{L \times SR_ERR} \times (DOUT) - \frac{T S}{L \times SR_ERR} \times R_{DEMAG} \cdot D I L [n - 1] - Δ I & (11) \end{matrix}

D I L [n] = D I L [n - 1] - \frac{T S}{L \times SR_ERR} \times (DOUT)

[0136] As the expressions provided by equations (10) and (11) are recursive (dependent on the previous value), the offset correction need to be done only once after being calculated (to avoid integrating that correction).

[0137] Once the offset error is corrected, all future DIL[n] will become corrected. The relative slope error term, SR_ERR, can (and should) be used for every subsequent DIL[n] value calculation.

[0138] The offset error may determined as described in relation to FIG. 7 or FIG. 8. The relative slope error may be determined as described in relation to FIG. 8.

[0139] It is desirable that the slopes of the waveforms DIL, IL are equal during the demagnetization phase (DEMAG) and the magnetization phase (MAG), and prior to the correction of the offset error. Therefore, in a specific embodiment, the relative slope error may be corrected prior the correction of the offset error.

[0140] With reference to the labels provided on FIG. 8, the offset error may be determined using the following equation:

[0141]

\begin{matrix} Δ I = SR_IL \cdot ΔT & (12) \end{matrix}

where :

\begin{matrix} SR_IL = \frac{Δ ISET}{ΔT_IL} & (13) \end{matrix}

[0142] Equations (12) and (13) may be used to correct the offset error ΔI after the relative slope error has been corrected.

[0143] If there is a relative slope error present, it is preferable to apply the relative slope error correction prior to correcting the offset error. However, embodiments of the present disclosure may apply the offset error correction prior to the relative slope error correction. Further embodiment may apply the offset error correction only.

[0144] FIG. 9(a) is a timing graph of the digitized inductor current DIL during operation of an example embodiment of the present disclosure, for example in relation to the apparatus presented in FIG. 6(a). In the present example, the offset error has been corrected by aligning the digitized inductor current DIL (a trace 900) with the analog inductor current IL (a trace 902). In the present example, the digitized inductor current DIL has been aligned with the analog inductor current IL at the thresholds DISET1, ISET1.

[0145] FIG. 9(b) is a timing graph of the digitized inductor current DIL during operation of an example embodiment of the present disclosure, for example in relation to the apparatus presented in FIG. 6(a). In the present example, the offset error has been corrected by aligning the digitized inductor current DIL (a trace 904) with the analog inductor current IL (a trace 906). In the present example, the digitized inductor current DIL has been aligned with the analog inductor current IL at the thresholds DISET2, ISET2.

[0146] If the slopes of DIL (SR_DIL) and IL (SR_IL) are not identical and the offset is corrected, the two waveforms may be aligned at the ISET1, DISET1 threshold (as in FIG. 9(a)) or may be aligned at the ISET2, DISET2 threshold (as in FIG. 9(b)). However, the average digitized inductor current (which may be denoted by <DIL>) and the average analog inductor current (which may be denoted by <IL>) will be unequal.

[0147] FIG. 10 is a timing graph showing the digitized current signal DIL and the analog current signal IL during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 6(a), where the energy storage element 602 is an inductor that is part of a buck converter. The present example may use the offset error correction and relative slope error correction method as described in relation to FIG. 8.

[0148] In the present example, during operation the relative slope error and then the offset error is corrected by the correction circuit 600. there is shown a trace 1000 of the digitized inductor current DIL, and a trace 1002 of the analog inductor current. In the present example, the correction circuit 600 applies relative slope error correction and offset error correction at the end of two successive demagnetization phases at a time 1006 and a time 1008. After the time 1008, the signals DIL, IL can be seen to be aligned and therefore the correction circuit 600 has corrected the digitized current signal DIL. It will be appreciated that in a further embodiment, the correction may be applied at the end of the magnetization phase, rather than the end of the demagnetization phase.

[0149] It will be appreciated that in further embodiments, the correction may be applied at any point during the switching cycle.

[0150] In further embodiments, the correction procedure provided by the correction circuit 600 may be applied based on one or more of the following conditions:

- [0151] every switching cycle
- [0152] every N switching cycles, where N is an integer
- [0153] non-periodically
- [0154] on demand, as determined either from measured errors or from an external source
- [0155] when calculated errors exceed a pre-defined threshold
- [0156] at mode changes (for example when changing from single phase operation to multi phase operation)
- [0157] when transients are detected (for example load transients, supply transients or temperature changes)

[0158] These corrections can thus prevent any residual errors from accumulating. The corrections, thought they might still have some residual errors themselves, may be enforced whenever necessary thus clamping the (DIL-IL) error.

[0159] FIG. 11 is a schematic of a specific embodiment of the correction circuit 600 and the switching converter 604, where the switching converter 604 is a buck converter, and in accordance with a third embodiment of the present disclosure. In the present embodiment, the buck converter 604 comprises a capacitor 1100, the power switch 606 being a high side switch, and a low side switch 1101; the correction circuit 600 comprises a logic block 1102 and two comparator units 1104; an analog to digital converter (which may function as the current synthesiser 612 as described previously, with DIL being generated based on equations (1) and (2)); the comparison circuit 608 comprises a timing extraction unit 1106, a timing extraction unit 1108, an offset and relative slope error extraction unit 1110, and, optionally, a filter unit 1112. The timing extraction unit 1108 comprises time to digital converters 1108a, 1108b.

[0160] It will be appreciated that the ADC 612 represents one method of generating the digitized inductor current DIL, and further embodiments may use alternative methods of digitized inductor current DIL generation, in accordance with the understanding of the skilled person. The method of digitized inductor current DIL may, for example, be sensor based or sensor-less.

[0161] Each of the comparator units 1104 comprise a comparator in the present embodiment. It will be appreciated that in further embodiments, alternative implementations are possible, in accordance with the understanding of the skilled person.

[0162] In the present example, the current flow IL is sensed by measuring the voltage drop across the low side switch LS 1101, and is described in more detail below. In a further embodiment, the current flow IL may be sensed using the HS switch 606 and the alignment of IL and DIL can then happen during MAG instead of during DEMAG. As discussed previously the analog current signal IL (that is used for comparison with the digitized current signal DIL) and the current flow through the inductor 602 are both denoted by the variable “IL” to denote that the analog current signal IL is representative of the current flow through the inductor. The logic block 1102 is used to generate DISET1 and DISET2 such that they are between the peak of DIL and valley of DIL.

[0163] In the present embodiment, the offset error signal (denoted by I_ERR) and the relative slope error (denoted by SR_ERR) are examples of the correction signal 601 as described previously. Using the information provided by these signals, the current synthesizer 612 corrects the offset error and the relative slope error in the generation of the digitized inductor current DIL.

[0164] FIG. 12 is a timing showing the digitized current signal DIL (a trace 1200) and the analog current signal IL (1202) during operation of an example embodiment of the present disclosure, for example, in relation to the apparatus presented in FIG. 11. There is also shown a first comparator output signal COMP1 (a trace 1204) being an output from one of the comparators of one of the comparator units 1104; a second comparator output signal COMP2 (a trace 1206) being an output from the comparator of the other comparator unit 1104; and a clock signal CLKS (a trace 1208).

[0165] In previous timing graphs, the digitized inductor current DIL was shown as continuous time. As discussed, in practice the digitized inductor current DIL will be a discrete-time, discrete-value digital signal. The analog current signal IL is representative of the real inductor current so is continuous in time and values.

[0166] It will be appreciated that there are multiple possible methods to determine the timing of the points as discussed previously. The following discussion relates to one such example method as described in relation to FIGS. 11 and 12.

[0167] Points C and D on FIG. 12 are referenced to the real current flow IL (t) through the inductor 602. In the present example, the comparator units 1104 are used to detect the analog inductor current IL and compare the analog inductor current IL to the thresholds ISET1, ISET2. Each of the two comparator units 1104 is configured to compare the analog inductor current IL to one of the thresholds ISET1, ISET2.

[0168] In the present embodiment, the comparators would detect the digitized inductor current IL as a voltage drop across the low side switch's 1101 device resistance. The thresholds ISET1, ISET2 are voltage references that are obtained via a DAC 1114 from the digital thresholds DISET1, DISET2.

[0169] Assuming zero offset and zero delays for the comparators of the comparator units 1104, the outputs COMP1 and COMP2 will be generated. The rising edge of COMP1 represents point C and rising edge of COMP2 represents point D. The delay between these signals can then be measured and converted to a digital number via the timing extraction unit 1108 comprising the Time to Digital Converters 1108a, 1108b. It will be appreciated that in further embodiments alternative methods may be used to extract the timing delay, in accordance with the understanding of the skilled person.

[0170] Points A and B are referenced to the digitized inductor current DIL[n], which is a discrete-time, discrete-value signal. A simple way to compute the T_AB delay is to monitor the digitized inductor current DIL values at each clock cycle and determine whether the DISET1 (or DISET2) level has been crossed.

[0171] By knowing the values of the digitized inductor current DIL before and after the crossing, interpolation (for example linear interpolation) can be undertaken to determine the time that the digitized inductor current DIL crossed DISET1 or DISET2. By knowing the integer number of clock cycles between A and B and the fractional part of a processing period TS, the time step T_A and the time step T_B, one can calculate the total T_AB. T_AB may correspond to ΔT_DIL as described in relation to FIG. 8.

[0172] Determination of the delay T_AC uses two points referenced two the two different signals DIL, IL that are in different domains (digital and analog). A potential solution is to measure the time T_C instead of directly measuring T_CD. This then allows T_AC to be computed as:

[0173]

\begin{matrix} T_AC = T_A + N \cdot T S - T_C & (14) \end{matrix}

where N is the integer number of clock periods elapsed between end of the T_A measurement and the end of T_C measurement, and N=2 in FIG. 12.

[0174] It will be appreciated that the method used to determine T_AC may also be applied in the determination of T_BC or T_BD.

[0175] It will be appreciated that the digitized inductor current DIL and the analog inductor current IL as shown in FIG. 12 comprise linear slopes as their values both rise and fall.

[0176] It will be appreciated that the method of extracting time delays T_AB, T_CD, T_AC, T_BD as described in relation to FIG. 12 may also be applied to non-linear slopes, for example including exponentially decaying waveform portions for both IL and DIL. However, the accuracy might be degraded when compared to the linear examples, as the previously described method uses a linear slope approximation. It will be appreciated that for non-linear slopes, different methods to determine the delays may be performed, in accordance with the understanding of the skilled person.

[0177] FIG. 13 is a timing graph showing simulation results of a practical implementation of a known system that uses a low bandwidth correction mechanism. There is shown an output voltage of a buck converter (a trace 1300); the analog inductor current IL (a trace 1302); the digitized inductor current DIL (a trace 1303); and the current error I_ERR which is equal to DIL-IL after filtering (a trace 1304). The traces 1302, 1303 appear to overlap in the graph.

[0178] The error I_ERR before the transient, as occurring at a time TA, is small due to a long settling time (more than 500 μs). After the load transient, a large error I_ERR is rapidly accumulated. The error I_ERR reduces with time to a minimum value of −740 mA at a very slow rate.

[0179] FIG. 14(a) is a timing graph showing simulations results of a practical implementation of the system illustrated in FIG. 11, and using cycle-by-cycle correction. The present simulation results shown the same load transient as shown in FIG. 13 and in the present example, the system reaches a steady state faster than the example shown in FIG. 13. There is shown the output voltage of the buck converter (a trace 1400); an analog inductor current IL (a trace 1402); a digitized inductor current DIL (a trace 1403); a current error I_ERR being equal to DIL-IL after filtering (a trace 1404); a digitized inductor current slope SR_DIL (a trace 1406); and an analog inductor current slope SR_IL (a trace 1408).

[0180] The error I_ERR starts from a similar value (45 mA) and reaches-290 mA due to the load transient induced errors. The error I_ERR is then rapidly corrected. The SR_IL and SR_DIL are also shown before and after the load transient. SR_IL and SR_DIL converge quickly despite having filtering applied to the slope correction. In a further embodiment, the relative slope error may be fully corrected in one cycle.

[0181] FIG. 14(b) is the timing graph of FIG. 14(a) over a shorter time scale. The offset correction is applied at the end of MAG (t=251 μs).

[0182] FIG. 15 is a schematic of a comparator unit 1500 that may be used for one or both of the two comparator units 1104 of FIG. 11. The comparator unit 1500 comprises switches 1502, 1504, 1506, 1508, 1510, 1512; capacitors 1514, 1516, 1518; an op amp 1520 and a comparator 1522.

[0183] The examples above mentioned the desirability of a zero-delay, zero-offset comparator to determine the points C and D. For the present disclosure, some approximations can be made that allow to effectively emulate a zero-delay, zero-offset comparator. The present example can achieve zero offset and zero delays when used in embodiments disclosed herein by clarifying that the nature of the buck converter (or other switching converter) allows some assumptions regarding the inputs to these comparators to be made.

[0184] In determining the T_CD, the absolute comparator delay is not important, as long as the delays between the two comparators are matched. The absolute delay of the comparator is, however, important for offset correction (based on either point C or D).

[0185] In consideration of FIG. 15, one of the comparator's 1522 inputs will be constant (VN) and the other input will have a relatively predictable slope, defined by the SR_IL. Current sources 1114 are sized in such a way that the comparator 1522 toggles when IL=ISET1 of IL=ISET2.

[0186] This system 1500 can achieve near zero-offset and, considering the IL slope constant, a near zero-delay. The system 1500 samples the residual voltage VOFFS at the time the comparator 1522 toggles and, based on that, adjusts an additional offset (VOFFS_COMP) at the input of the comparator 1522 such that VP=(VSW_SNS+VOFFS_COMP).

[0187] The steady-state is achieved when the comparator 1522, COMP, toggles exactly when the residual offset, VOFFS, is zero. This results in effectively zero-delay and zero-offset comparator.

[0188] This works if the slope of the inductor current, SR_IL does not change. When the slope changes (due to VIN/VOUT, load transient or temperature effects), the system will introduce an error until settling again to the new steady-state.

[0189] In summary, embodiments of the present disclosure may be used to correct for the DIL-IL error, both in terms of offset and ripple (via slope adjustments). Specific embodiments described here perform correction of offset errors in a digitized inductor current DIL in a switching mode power converter by aligning it to one or more measured points of the real inductor current (or a signal derived from the real inductor current), labelled “IL”. Embodiments of the present disclosure perform correction of the slope (slew rate) errors of a digitized inductor current DIL in a switching mode power converter by aligning it to two or more measured points of the real inductor current (or a signal derived from the real inductor current), labelled “IL”. Embodiments of the present disclosure perform correction of both offset and slope (slew rate) errors of a digitized inductor current DIL in a switching mode power converter by aligning it to two or more measured points of the real inductor current (or a signal derived from the real inductor current), labelled “IL”. Embodiments of the present disclosure use delay measurements (in analogue domain) and direct delay calculations (in digital domain) in the computation of offset and slope (slew rate) correction.

[0190] Various improvements and modifications may be made to the above without departing from the scope of the disclosure.

Claims

The invention claimed is:

1. A correction circuit configured to:

compare a digitized current signal to an analog current signal, wherein the digitized current signal is a digital representation of the analog current signal, and the analog current signal is a current flowing through an energy storage element; and

correct one or more errors in the digitized current signal based on the outcome of the comparison.

2. The correction circuit of claim 1, wherein the digitized current signal is provided by a current synthesizer.

3. The correction circuit of claim 2, is further configured to:

generate a correction signal that is dependent on the outcome of the comparison; and

provide the correction signal to the current synthesizer, the correction signal being used by the current synthesizer for correcting the one or more errors in the digitized current signal.

4. The correction circuit of claim 1 is further configured to correct an offset error between the digitized current signal and the analog current signal.

5. The correction circuit of claim 4 is further configured to:

compare the digitized current signal to the analog current signal to determine the offset error; and

correct the digitized current signal using the determined offset error.

6. The correction circuit of claim 5 is further configured to:

determine the offset error by:

detecting a first time step when the digitized current signal crosses a first digital threshold;

detecting a second time step when the analog current signal crosses a first analog threshold;

calculating a first duration between the first time step and the second time step;

determining a first slope of at least one of the digitized current signal and the analog current signal; and

multiplying the first duration by the first slope, thereby determining the offset error.

7. The correction circuit of claim 6, wherein the first digital threshold is approximately equal to a digitized first analog threshold.

8. The correction circuit of claim 6 comprises a comparator configured to provide an output that is indicative of analog current signal crossing the first analog threshold, the output being used to determine the second time step.

9. The correction circuit of claim 1 is further configured to correct a relative slope error between the digitized current signal and the analog current signal.

10. The correction circuit of claim 9 is further configured to:

compare the digitized current signal to the analog current signal to determine the relative slope error; and

correct the digitized current signal using the relative slope error, as determined.

11. The correction circuit of claim 10 is further configured to:

determine the relative slope error by:

detecting a first time step when the digitized current signal crosses a first digital threshold;

detecting a second time step when the analog current signal crosses a first analog threshold;

detecting a third time step when the digitized current signal crosses a second digital threshold;

detecting a fourth time step when the analog current signal crosses a second analog threshold;

calculating a first digital slope delay between the first time step and the third time step;

calculating a first analog slope delay between the second time step and the fourth time step; and

dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtracting one from the first delay parameter, thereby determining the relative slope error.

12. The correction circuit of claim 4 is further configured to correct a relative slope error between the digitized current signal and the analog current signal.

13. The correction circuit of claim 12 is further configured to correct the relative slope error prior to correcting the offset error.

14. The correction circuit of claim 13 is further configured to:

compare the digitized current signal to the analog current signal to determine the relative slope error and the offset error; and

correct the digitized current signal using the relative slope error and offset error, as determined.

15. The correction circuit of claim 14 is further configured to:

determine the relative slope error by:

detecting a first time step when the digitized current signal crosses a first digital threshold;

detecting a second time step when the analog current signal crosses a first analog threshold;

detecting a third time step when the digitized current signal crosses a second digital threshold;

detecting a fourth time step when the analog current signal crosses a second analog threshold;

calculating a first digital slope delay between the first time step and the third time step;

calculating a first analog slope delay between the second time step and the fourth time step;

16. The correction circuit of claim 15 is further configured to:

determine the offset error by:

calculate a first duration between the first time step and the second time step;

determine a first slope of the analog current signal by:

calculating an analog threshold difference by subtracting the second analog threshold from the first analog threshold; and

dividing the analog threshold difference by the first analog slope delay; and

multiply the first slope of the analog current signal by the first duration, thereby determining the offset error.

17. The correction circuit of claim 1 is further configured to correct one or more errors in the digitized current signal during operation of a switching converter comprising the energy storage element.

18. The correction circuit of claim 17, wherein the energy storage element comprises an inductor.

19. The correction circuit of claim 17 is further configured to correct the one or more errors in the digitized current signal:

two or more times during operation of the switching converter; or

in response to an external signal; or

in response to one of the one or more errors exceeding a threshold value; or

in response to a mode change of the switching converter; or

in response to a transient.

20. A method of correcting one or more errors in a digitized current signal, the method comprising:

comparing the digitized current signal to an analog current signal, wherein the digitized current signal is a digital representation of the analog current signal, and the analog current signal is a current flowing through an energy storage element; and

correcting the one or more errors in the digitized current signal based on the outcome of the comparison.

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Abstract

Description

Background

[0004] We distinguish:

- [0005] The switching frequency (FSW) of the buck converter 100, for example 2 MHz. FSW is equal to 1/TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage.
- [0006] The processing frequency of the digital controller 108 (FS), for example about 100 MHz. FS is equal to 1/TS, where TS is the processing period of the controller 108. FS can also optionally be the sampling frequency of ADC 102.