Lateral power semiconductor device

[0001] This application is based upon and claims priority to Chinese Patent Application No. 202310591908.3, filed on May 24, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present invention belongs to the technical field of power semiconductors, and relates to a lateral power semiconductor device.

[0003] In the field of power integrated circuits, power semiconductor devices are widely applied. In particular, in the field of integrated drive circuits, a laterally-diffused metal-oxide semiconductor (LDMOS) plays an indispensable role due to the characteristic of easy integration. A reduce surface field (RESURF) is often used to improve the electrical characteristics of LDMOS. The power LDMOS usually requires low specific on resistance (R_on,sp), large safe operating area (SOA) and high breakdown voltage. The schematic diagram of a traditional LDMOS device is shown in FIG. 1, and a metal field plate is connected to a source electrode. A high-current device usually has large switching loss, which will affect the performance and life of the device.

[0004] To reduce a switching loss and obtain a high-current low-resistance device, a lateral power semiconductor device with a double gate structure is introduced. As shown in FIG. 2A, the voltage of a control gate when the device is switched off may be separately set, and a negative potential is given to the control gate to make the control gate assist a drift area in depletion, which is conducive to obtaining an expected breakdown voltage at a higher drift area concentration, thereby increasing the on current, reducing R_on,sp, and not reducing the breakdown voltage of the device. However, to avoid hot-carrier effect and advanced breakdown caused by excessively strong electric field modulation effect of the control gate on a silicon surface, the thickness of an insulating dielectric layer under SAB is adjusted to make the dielectric layer close to a drain area thicker, so that the advanced breakdown problem of the device can be effectively relieved, where SAB is salicide block. On the control gate, polysilicon with a PN junction is used, thereby reducing the gate-drain coupling charge number and the equivalent capacitance C_GD.

[0005] Based on the above theoretical analysis, the double gate structure and different dielectric layers introduced by the present invention can adjust the voltage of the control gate to reduce the loss and the specific on resistance of the device, optimize the breakdown voltage of the device and relieve the hot-carrier injection effect. The present invention appears under this background.

[0006] To achieve the aforementioned objective of the present invention, the technical solution of the present invention is as follows:

• • [0007] a lateral power semiconductor device includes: a second doping type substrate 1, a first doping type buried layer 2 above the second doping type substrate 1, a second doping type epitaxial layer 3 above the first doping type buried layer 2, a first doping type drift area 4 above an interior of the second doping type epitaxial layer 3, a left-side second doping type first body area 5 and a right-side first doping type drain area 8 inside the first doping type drift area 4, and a first doping type source area 7 and a second doping type second body area 6 on an inner upper surface of the second doping type first body area 5, where the first doping type source area 7 is adjacent to and short-connected to the second doping type second body area 6; a dielectric layer 13 is arranged on an upper surface of the first doping type drift area 4;
  • [0008] a source electrode 9, a main gate 10, a salicide block (SAB) structure 11, a control gate 14 and a drain electrode 12 are arranged inside the dielectric layer 13 from left to right, the source electrode 9 is in ohmic contact with the first doping type source area 7, and the source electrode 9 is in ohmic contact with the second doping type second body area 6; the main gate 10 is located above the second doping type first body area 5 and the first doping type drift area 4, and is isolated from semiconductor silicon through the dielectric layer 13; the control gate 14 is located above the salicide block (SAB) structure 11, the salicide block (SAB) structure 11 is located above the first doping type drift area 4, and the salicide block (SAB) structure 11 is isolated from a surface of the first doping type drift area 4 through the dielectric layer 13; and the drain electrode 12 is in ohmic contact with the first doping type drain area 8.

[0009] As a preferred manner, the width of the main gate 10 is greater than the length of the channel, so that an accumulation area is formed on the surface of the first doping type drift area 4. The on resistance is reduced, the static characteristic is improved, and the loss of the device is reduced.

[0010] In a traditional structure, the control gate is deposited on the salicide block (SAB) structure 11 and connected to the source electrode 9, and has the same fixed potential, thereby increasing the breakdown voltage of the device. The present invention provides a lateral power semiconductor device having a double gate structure. The control gate 14 is separately led out and connected to different potentials, and the main gate 10 is connected to a low potential. When the device is switched off, a negative voltage is provided to the control gate 14 to assist the first doping type drift area 4 below the control gate in depletion. Therefore, the first doping type drift area 4 with higher concentration may be used to reduce R_on,sp and increase the saturation current without reducing the breakdown voltage.

[0011] As a preferred manner, the lateral power semiconductor device includes a double gate structure with the control gate 14 and the main gate 10, where the control gate 14 structure is led out and separately connected to a potential, and when the device is in an off state, the main gate 10 is connected to a low potential, the source electrode 9 is connected to the low potential or is grounded, the drain electrode 12 is connected to a high potential, and the control gate 14 provides the low potential.

[0012] As a preferred manner, when the device is in an on state, the main gate 10 is connected to a high potential, the source electrode 9 is connected to a low potential or is grounded, the drain electrode 12 is connected to a high potential, the control gate 14 is connected to the high potential, and the high potential is in a positive voltage. More carriers are induced on a silicon surface below the control gate, thereby further increasing the saturation current of the device, and reducing the loss and R_on,sp of the device.

[0013] As a preferred manner, before the main gate 10 is connected to a low potential and the device is switched off, a signal of the control gate 14 is connected to the low potential in advance.

[0014] Specifically, the low potential of the signal of the control gate 14 is ahead of a switch-off signal of the main gate, so it is beneficial to reduce the current when the device is switched off, reduce the loss and increase the switch-off speed. The additionally introduced electrical signal of the control gate 14 can increase the switching speed of the device, reduce the switching loss of the device, and optimize the static and dynamic characteristics of the device.

[0015] As a preferred manner, when the device is switched on, the main gate 10 is connected to a high potential, the source electrode 9 is connected to a low potential or is grounded, the drain electrode 12 is connected to a high potential, and an electrode of the control gate 14 is connected to the high potential; before the main gate 10 is connected to the low potential and the device is switched off, a signal of the control gate 14 is connected to the low potential in advance; and when the device is switched off, the main gate 10 is connected to the low potential, and a signal of the control gate 14 is connected to the low potential.

[0016] Specifically, in the proposed device structure, when the potential of the main gate 10 is a high potential and the device is switched on, a positive voltage is provided to the control gate 14; before the gate voltage is converted from a high potential to a low potential, a negative voltage is provided to the control gate 14, so that the current when the device is switched off is reduced; and when the device is switched off, the control gate 14 provides a negative voltage to assist the drift area in depletion. Therefore, the concentration of the drift area can be increased to reduce R_on,sp without the breakdown voltage is not changed, increase the saturation current, increase the switching speed of the device and reduce the loss.

[0017] The additionally introduced electrical signal of the control gate 14 is used to increase the switching speed of the device, reduce the switching loss of the device and optimize the static and dynamic characteristics of the device, thereby obtaining a lateral power semiconductor device with the characteristics of high current and low loss.

[0018] As a preferred manner, a body electrode 15 is arranged on a left side of the source electrode 9, the source electrode 9 and the body electrode 15 are separately connected to potentials, and the source electrode 9 can be connected to different potentials to sample current signals, thereby achieving different waveform control.

[0019] As a preferred manner, the dielectric layer below the salicide block (SAB) structure 11 and the control gate 14 is in a stepped shape, and the dielectric layer close to a drain terminal is thicker. The modulation effect of the control gate 14 can be reduced, so that the hot-carrier injection effect can be reduced, and the advanced breakdown of the device can be avoided, thereby achieving high current, low R_on,sp and good static characteristic without reducing the breakdown voltage. The structure characteristic is to introduce insulating layers with different thicknesses to reach an expected breakdown voltage. The dielectric layer may be made into multiple steps, and can better regulate and control the electric field distribution of the silicon surface compared with a single step.

[0020] As a preferred manner, the dielectric layer below the salicide block (SAB) structure 11 and the control gate 14 is in slope shape, and the dielectric layer is thickened uniformly in a direction from a source terminal to a drain terminal. Therefore, the modulation effect of the control gate on the silicon surface is reduced linearly with the decrease of a distance from the drain area, and the curvature effect introduced by the stepped structure can be avoided.

[0021] As a preferred manner, no metal is deposited on the salicide block (SAB) structure 11, but second doping type polysilicon 22 and first doping type polysilicon 23 are deposited on the salicide block (SAB) structure; the second doping type polysilicon 22 and the first doping type polysilicon 23 form the control gate 14; and in a case that a negative bias voltage is applied to the control gate, a PN junction in the control gate is in a reverse bias depletion state and has a large depletion capacitance. The introduction of the capacitance makes the capacitance of the dielectric layer and the gate-drain capacitance converted from a parallel connection relationship to a series connection relationship, thereby reducing the coupling capacitance, increasing the switching speed of the device, reducing the loss of the device, and optimizing the static and dynamic characteristics of the device.

[0022] The present invention has the following beneficial effects: the present invention provides a lateral power semiconductor device with a control gate besides a main gate. Compared with the traditional LDMOS, the device can reduce the loss of the power device, increase the on current, and reduce the R_on,sp and capacitance of the device. The carrier distribution is changed by adjusting the waveform of the signal of the control gate, so that the electric field distribution is adjusted to reach an expected breakthrough voltage, and R_on,sp is reduced to obtain a high-current device. The thickness of the insulating layer is adjusted under the SAB structure, so that the hot-carrier injection effect close to the drain electrode is reduced, and the breakthrough voltage is effectively increased. A polysilicon electrode is introduced on the SAB structure of the LDMOS device, thereby reducing the gate-drain capacitance and the loss of the device.

[0038] 1: second doping type substrate; 2: first doping type buried layer; 3: second doping type epitaxial layer; 4: first doping type drift area, 5: second doping type first body area; 6: second doping type second body area; 7: first doping type source area; 8: first doping type drain area; 9: source electrode; 10: main gate; 11: salicide block (SAB) structure; 12: drain electrode; 13: dielectric layer; 14: control gate; 15: body electrode; 22: second doping type polysilicon; 23: first doping type polysilicon.

[0039] The implementation manners of the present invention are described below by the specific embodiments. Those skilled in the art may easily understand other advantages and effects of the present invention by the contents disclosed by the specification. The present invention can be implemented or applied through other different specific implementation manners. Various modifications or changes can be made to various details in the specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] The following specific implementation structure, in particular, a method for introducing a control gate to optimize a static parameter, is not only suitable for LDMOS, but also suitable for IGBT devices, or power integrated semiconductor devices by means of a RESURF technology and a super junction (SJ) technology.

[0041] In the following embodiments:

• • [0042] a source electrode 9, a drain electrode 12 and a body electrode 15 are made of metal.

[0043] A main gate 10 is made of polysilicon.

[0044] A salicide block (SAB) structure 11 is made of silicon rich oxide (SRO), SiO₂, SiON or Si₃N₄.

[0045] A dielectric layer 13 is made of silicon dioxide.

[0046] A control gate 14 is made of metal.

[0047] A first doping type is N-type doping, and a second doping type is P-type doping.

[0048] As shown in FIG. 2A, a lateral power semiconductor device includes: a second doping type substrate 1, a first doping type buried layer 2 above the second doping type substrate 1, a second doping type epitaxial layer 3 above the first doping type buried layer 2, a first doping type drift area 4 above an interior of the second doping type epitaxial layer 3, a left-side second doping type first body area 5 and a right-side first doping type drain area 8 inside the first doping type drift area 4, and a first doping type source area 7 and a second doping type second body area 6 on an inner upper surface of the second doping type first body area 5, where the first doping type source area 7 is adjacent to and short-connected to the second doping type second body area 6; a dielectric layer 13 is arranged on an upper surface of the first doping type drift area 4;

• • [0049] a source electrode 9, a main gate 10, a salicide block (SAB) structure 11, a control gate 14 and a drain electrode 12 are arranged inside the dielectric layer 13 from left to right; the source electrode 9 is in ohmic contact with the first doping type source area 7, and the source electrode 9 is in ohmic contact with the second doping type second body area 6; the main gate 10 is located above the second doping type first body area 5 and the first doping type drift area 4, and they are isolated from a semiconductor silicon through the dielectric layer 13; the control gate 14 is located above the salicide block (SAB) structure 11, the salicide block (SAB) structure 11 is located above the first doping type drift area 4, and the salicide block (SAB) structure 11 is isolated from the surface of the first doping type drift area 4 through the dielectric layer 13; and the drain electrode 12 is in ohmic contact with the first doping type drain area 8.

[0050] To improve the static and dynamic characteristics of the device, the present invention introduces a new way to apply voltage, and the voltage waveform of the control gate 14 and the main gate 10 is shown in FIG. 2B. In a case that the main gate 10 is connected to a low potential, the control gate 14 is connected to the low potential which is in a negative voltage.

[0051] The working principle of this embodiment is: when the device is in an off state, the main gate 10 is connected to a low potential, the source electrode 9 is connected to the low potential or is grounded, the drain electrode 12 is connected to a high potential, the control gate 14 is connected to the low potential which may be in a negative voltage, electrons are repelled at a silicon surface below the control gate 14, and the first doping type drift area 4 below the control gate are assisted in depletion, so that the breakdown voltage of the device can be improved. Therefore, the device can obtain low R_on,sp and a high saturation current by increasing the concentration of the first doping type drift area 4, and the control gate 14 can provide a negative voltage to maintain the breakdown voltage unchanged.

[0052] FIG. 9 is a simulation structure diagram of a traditional lateral power semiconductor device and Embodiment 1. In the traditional structure, the control gate 14 is short-connected to the source electrode 9 and is connected to a zero potential, the structure 1 is a lateral power semiconductor device structure provided in Embodiment 1; the control gate 14 and the source electrode 9 are separated and may be separately connected to different potentials, and a higher-concentration structure 1 increases the concentration of the first doping type drift area 4 based on the structure 1.

[0053] FIG. 10 is a breakdown curve of a traditional lateral power semiconductor device and Embodiment 1 in an off state at different drift area concentrations and control gate voltages. In FIG. 10, the structure 1 is a lateral power semiconductor device structure provided in Embodiment 1; and a higher-concentration structure 1 increases the concentration of the first doping type drift area 4 based on the structure 1. The traditional structure and the structure 1 have the same concentration of the first doping type drift area 4. The breakdown voltage of the high-concentration drift area is lower than that of the low-concentration drift area. Different negative voltages are applied to the control gate 14, so that the breakdown voltage of the device can remain constant while the concentration of the first doping type drift area 4 and the saturation current are increased.

[0054] FIG. 11 is an output characteristic curve of a traditional lateral power semiconductor device and Embodiment 1 at different drift area concentrations and control gate voltages. The structure 1 is a lateral power semiconductor device structure provided in Embodiment 1; and a higher-concentration structure 1 increases the concentration of the first doping type drift area 4 based on the structure 1. It can be seen from the figure that the structure in Embodiment 1 may adopt a higher concentration of the first doping type drift area 4 to increase the saturation current; furthermore, the higher the voltage of the control gate 14, the higher the switch-on speed of the device and the higher the breakdown voltage in an on state.

[0055] FIG. 12 is a specific on resistance and a saturation current of a traditional lateral power semiconductor device and Embodiment 1 at different drift area concentrations and control gate voltages. The structure 1 is a lateral power semiconductor device structure provided in Embodiment 1; and a higher-concentration structure 1 increases the concentration of the first doping type drift area 4 based on the structure 1. It can be seen from the figure that the higher the voltage of the control gate 14, the lower the R_on,sp and the higher the saturation current.

[0056] As shown in FIG. 3A, FIG. 3B and FIG. 3C, the difference between this embodiment and Embodiment 1 is as follows: the control gate 14 and the main gate 10 have different signal waveform.

[0057] As shown in FIG. 3A, when the device is in an on state, the main gate 10 is connected to a high potential, the source electrode 9 is connected to a low potential or is grounded, the drain electrode 12 is connected to a high potential, the control gate 14 is connected to the high potential, and the high potential is in a positive voltage Therefore, more electrons are induced on the silicon surface below the control gate 14, the carrier concentration of a conductive path is increased, the saturation current and the switch-on speed of the device are further increased, and R_on,sp is reduced.

[0058] As shown in FIG. 3B, before the main gate 10 is connected to a low potential and the device is switched off, the control gate 14 is connected to the low potential in advance, so that the on current can be reduced, the switch-off speed of the device can be increased, and the switching loss can be reduced.

[0059] As shown in FIG. 3C, when the device is switched on, the main gate 10 is connected to a high potential, the source electrode 9 is connected to a low potential or is grounded, the drain electrode 12 is connected to a high potential, and the control gate 14 is connected to the high potential; before the main gate 10 is connected to the low potential and the device is switched off, the control gate 14 is connected to the low potential in advance; and when the device is switched off, the main gate 10 is connected to the low potential, and the control gate 14 is connected to the low potential. Therefore, a lateral power semiconductor device with the characteristics of high current and low loss can be obtained, and a high negative voltage can be provided to the control gate 14 to ensure that the breakdown voltage of the device is not reduced.

[0060] As shown in FIG. 4, the difference between this embodiment and Embodiment 1 is as follows: a body electrode 15 is arranged on a left side of the source electrode 9, the source electrode 9 and the body electrode 15 are separately connected to potentials, the potential of the source electrode 9 may float, and the source electrode 9 may be connected to different potentials to sample current signals.

[0061] As shown in FIG. 5, the difference between this embodiment and Embodiment 1 is as follows: the dielectric layer below the salicide block (SAB) structure 11 and the control gate 14 is in a stepped shape, and the dielectric layer close to a drain terminal is thicker. The electric field modulation effect of the control gate 14 and the hot-carrier injection effect can be reduced, and the advanced breakdown of the device can be avoided, so that the breakdown voltage of the device can be optimized, and good static characteristic can be achieved.

[0062] As shown in FIG. 6, the difference between this embodiment and Embodiment 4 is as follows: the dielectric layer below the salicide block (SAB) structure 11 and the control gate 14 has a stepped shape including multiple steps. The dielectric layer has more steps and has better electric field modulation effect compared with the single step, thereby avoiding breakdown before reaching the expected voltage.

[0063] As shown in FIG. 7, the difference between this embodiment and Embodiment 1 is as follows: the dielectric layer below the salicide block (SAB) structure 11 and the control gate 14 is in a slope shape, and the dielectric layer is thickened uniformly in a direction from a source terminal to a drain terminal. Therefore, the modulation effect of the control gate 14 is reduced uniformly with the decrease of the distance from the drain terminal. Meanwhile, the structure also can reduce the curvature effect at the dielectric layer introduced by Embodiment 4 and Embodiment 5.

[0064] As shown in FIG. 8, the difference between this embodiment and Embodiment 1 is as follows: no metal is deposited on the salicide block (SAB) structure 11, but second doping type polysilicon 22 and first doping type polysilicon 23 are deposited on the salicide block (SAB) structure 11; the second doping type polysilicon 22 and the first doping type polysilicon 23 form the control gate 14; in a case that a negative bias voltage is applied to the control gate, and PN junction in the control gate is in a reverse bias state.

[0065] The control gate is formed by polysilicon with PN junction in a reverse bias depletion state, which has large depletion capacitance. The introduction of the capacitance makes the capacitance of the dielectric layer and the gate-drain capacitance converted from a parallel connection relationship to a series connection relationship, thereby reducing the coupling capacitance, increasing the switching speed of the device, reducing the loss of the device, and optimizing the static and dynamic characteristics of the device.

[0066] In particular, the structures in the specification may be combined with each other, and parameters can be adjusted according to the actual process conditions to achieved the optimal characteristics of the device. In addition, the first doping type drain area 8 in each embodiment is changed into a second doping type semiconductor, and an LIGBT structure can be formed.

[0067] The above embodiments are only intended to exemplarily illustrate the principle and effect of the present invention, but not intended to limit the present invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the art without departing the spirit and technical ideal disclosed by the present invention should still be covered within the claims of the present invention.