Interconnect based address mapping for improved reliability

[0001] FIGS. 1A-1B are a block diagrams illustrating an example memory system.

[0002] FIG. 2 is a block diagram illustrating an example buffered memory module system.

[0003] FIG. 3 is a flowchart illustrating a method of operating a memory module.

[0004] FIG. 4 is a flowchart illustrating a method of determining a transformation to reverse an interconnect based address transformation.

[0005] FIG. 5 is a flowchart illustrating a method of determining address transformations.

[0006] FIG. 6 is a flowchart illustrating a method of reversing address transformations.

[0007] FIG. 7 is a flowchart illustrating a method of transmitting addresses.

[0008] FIG. 8 is a block diagram of a processing system.

[0009] Repeated row activations of the same row in a memory device (e.g., dynamic random access memory—DRAM), whether malicious or accidental, may cause cells in the neighborhood of the repeatedly activated row to lose a stored value. This effect on storage reliability has been termed “row hammer.” Row hammer, when applied to the multiple, parallel, memory device accesses that occur with memory modules, can cause multiple errors across multiple devices on the module. When many errors occur across multiple memory devices, error detection and correction schemes such as Chipkill (a.k.a., “single device data correct”—SDDC) and SSDC/DSDD (i.e., “single symbol data correct”—SSDC with “double symbol data detect”—DSDD) may be overwhelmed by the number and distribution of errors and thereby unable to correct these row hammer caused errors (or in some cases, detect the errors).

[0010] In an embodiment, row addressing received by a module is mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device (i.e., the addresses received via the command/address interface of a given device) to respective internal row addresses (i.e., an ordinal row number of the row in the respective device's memory core—for example, if the rows of the array are addressed in order, from top to bottom, the internal row address that selects a row from top to bottom are 0, 1, 2, 3, . . . ) ensure that each set of neighboring rows for a given row address received by the module is different for each memory device in a module's rank, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device during a column access (Read or Write). By confining the row hammer errors to a single memory device per column access, the row hammer errors are correctible using a SDDC scheme. In an embodiment, the module row address to device row address mappings comprise different permutations of the module row address bits for each memory device on the module.

[0011] The descriptions and embodiments disclosed herein are made primarily with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example where, due at least to the widespread adoption of DRAM technology, “row-hammer” has been observed and studied. It should be understood that other memory technologies that may be susceptible to “row-hammer” and therefore may also benefit from the methods and/or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM—a.k.a., programmable metallization cell—PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and/or combinations thereof. Accordingly, it should be understood that in the disclosures and/or descriptions given herein, these aforementioned technologies may be substituted for, included with, and/or encompassed within, the references to DRAM, DRAM devices, and/or DRAM arrays made herein.

[0012] FIGS. 1A-1B are a block diagrams illustrating an example memory system. In FIGS. 1A-1B, memory system 100 comprises controller 120 and memory module 150. Controller 120 includes interfaces operatively coupled with memory module 150 (e.g., memory channel interfaces comprising command/address and data interfaces) and reliability, availability, and serviceability (RAS) circuitry 123 (e.g., error detect and correct—EDC, error correcting code—ECC, chipkill SDDC, memory scrubbing, etc. circuitry). Memory module 150 includes memory devices 110a-110c, command/address (CA) interface 151, data (DQ) interfaces 152a-152c, and address mapping interconnect 155a-155c. Memory devices 110a-110c, respectively, include memory device CA interfaces 111a-111c, DQ interfaces 112a-112c, control circuitry 113a-113c, memory arrays 130a-130c, and row decoders 117a-117c. Control circuitry 113a-113c, respectively, include reconstruction circuitry 114a-114c.

[0013] Rows 131a-134a of memory array 130a, rows 131b-134b of memory array 130b, and rows 131c-134c of memory array 130c are also illustrated in FIGS. 1A-1B. The vertical position of row 131a in memory array 130a is equivalent to the vertical position of row 131b in memory array 130b and row 131c in memory array 130c. This is intended to convey that rows 131a-131c each have the same internal row address. Thus, it should be understood that rows 132a-132c each have the same internal row address, rows 133a-133c each have the same internal row address, and rows 134a-134c each have the same row address. Because rows 131a-131c are each illustrated as physically next to rows 132a-132c, respectively, it should also be understood that rows 131a-131c are physically adjacent (i.e., are neighboring rows) to rows 132a-132c, respectively. Similarly, rows 133a-133c are neighboring rows to rows 134a-134c, respectively.

[0014] CA interfaces 111a-111c, of memory devices 110a-110c, respectively, are operatively coupled to memory arrays 130a-130c, respectively. Row addresses received via CA interfaces 111a-111c (a.k.a., external row addresses) are respectively operatively coupled to memory arrays 130a-130c via row decoders 117a-117c (e.g., row address decoders, buffers, etc.) Column addresses received via CA interface 111a-111c are operatively coupled to memory arrays 130a-130c, respectively, via column circuitry (e.g., column address decoders, buffers, etc.).

[0015] Controller 120 and memory devices 110a-110c may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 120, manages the flow of data going to and from memory devices and/or memory modules (e.g., memory module 150). Memory devices 110 may be standalone devices, or may be components of a memory module such as a DIMM module used in servers. In an embodiment, memory devices 110a-110c may be a devices that adhere to, or are compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory devices 110a-110c may be, or comprise, a device that is or includes other memory device technologies and/or specifications. Memory devices 110a-110c may be or comprise a stack of integrated circuit dies. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 120 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), one or more dies in a stack of integrated circuit dies, or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0016] DQ interfaces 152a-152c of memory module 150 are operatively coupled to controller 120. DQ interfaces 152a-152c of memory module 150 are respectively operatively coupled to DQ interfaces 112a-112c of memory devices 110a-110c. Thus, DQ interfaces 112a-112c of memory devices 110a-110c are operatively coupled to controller 120 via DQ interfaces 152a-152c of memory module 150. DQ interfaces 112a-112c of memory devices 110a-110c are operatively coupled to controller 120 to at least communicate data to be written/read to/from memory devices 110a-110c, respectively.

[0017] CA interface of controller 120 is operatively coupled to CA interface 151 of memory module 150. The CA interface of controller 120 is operatively coupled to CA interface 151 to communicate commands and addresses (e.g., row and column addresses) from controller 120 to memory module 150. CA interface 151 of memory module 150 is operatively coupled to device CA interfaces 111a-111c of memory devices 110a-110c. CA interface 151 of memory module 150 is operatively coupled to device CA interfaces 111a-111c of memory devices 110a-110c to communicate commands and addresses from CA interface 151 to CA interfaces 111a-111c. In particular, CA interface 151 is operatively coupled to CA interface 111a via address mapping interconnect 155a; CA interface 151 is operatively coupled to CA interface 111b via address mapping interconnect 155b; and, CA interface 151 is operatively coupled to CA interface 111c via address mapping interconnect 155c.

[0018] The commands communicated from controller 120 to memory module 150 include activate commands and an associated external row address to be communicated with memory devices 110a-110c. In an embodiment, memory module 150, and address mapping interconnects 155a-155c may permute and/or invert the bits of external row addresses received via CA interface 151. Address mapping interconnects 155a-155c may permute and/or invert the bits of external row addresses received via CA interface 151 in order to ensure that for any row address in a memory device's 110a-110c memory arrays 130a-130c, respectively, has unique neighbors compared to the other memory device's 110a-110c memory arrays 130a-130c being accessed. In other words, for any given external row address that's being activated, the external row address that maps to a neighboring row(s) will be different in each memory device's 110a-110c memory arrays 130a-130c. This ensures that errors are confined to a single memory device 110a-110c.

[0019] In an embodiment, address mapping interconnects 155a-155c uniquely (among the memory devices 110a-110c and address mapping interconnects 155a-155c on memory module 150) permute and/or invert the bits of at least external row addresses received via CA interface 151 before the external row addresses are received by memory devices 110a-110c . . . . In an embodiment, address mapping interconnects 155a-155c uniquely (among the memory devices 110a-110c and address mapping interconnects 155a-155c on memory module 150) permute and/or invert the bits of some (but not all) of the external row addresses received via CA interface 151 before the external row addresses are received by memory devices 110a-110c. In an embodiment, a one of address mapping interconnects 155a-155c does not permute and/or invert the bits of external row addresses received via CA interface 151. In this case, other of address mapping interconnects 155a-155c permute and/or invert the bits of at least external row addresses to create unique (among memory devices 110a-110c) permutations and/or inversion of the bits of external row addresses received by memory devices 110a-110c. In an embodiment, CA interface 151 and/or CA interfaces 111a-111c communicate using differential signaling. Thus, inversions of bits may be accomplished by address mapping interconnects 155a-155c by exchanging, relative to how they were received by CA interface 151, the true and complement conductors of the differential signaling pair they are connected to at CA interface 111a-111c.

[0020] Each memory device 110a-110c receives external row addresses (e.g., associated with an activate command-ACT) via respective CA interfaces 111a-111c and provides the external row addresses to respective row decoders 117a-117c. Row decoders 117a-117c each activate a respective row in memory arrays 130a-130c.

[0021] In an embodiment, however, because address mapping interconnects 155a-155c have uniquely (among memory devices 110a-110c on memory module 150) permuted and/or inverted the row addresses received by respective memory devices 110a-110c, row decoders 117a-117c may each activate a row in a respective memory array 130a-130c that are each different (i.e., different internal row address) from the rows activated by the other row decoders 117a-117c. This is illustrated in FIG. 1B by the vertical positioning in memory arrays 130a-130c of rows 131a-134a, by the arrow running from row decoder 117a to row 132a of memory array 130a, the arrow running from row decoder 117b to row 134b of memory array 130b, and the arrow running from row decoder 117c to a row in memory array 130c that does not have the same internal address as either row 132a or 134b.

[0022] By uniquely configuring the address translations made by address mappings interconnects 155a-155c as they couple CA interface 151 to CA interfaces 111a-111c, the unique mappings may be selected such that row hammer affects different neighboring row address in each memory device 110a-110c. Because the CA interface 151 address to CA interfaces 111a-111c address mappings are selected to ensure that each set of neighboring rows inside of memory devices 110a-110c for a given CA interface 151 addressed row is different for each memory device 110a-110c on memory module 150, row hammering of a given CA interface 151 addressed row is spread across different internally addressed rows on respective memory devices 110a-110c. This has the effect of confining row hammer errors for each internal row that is hammered to a single memory device per CA interface 151 addressed neighboring row. By confining the row hammer errors to a single memory device 110a-110c (per column access), the row hammer errors are correctible by RAS circuitry 123 using, for example, a SDDC scheme.

[0023] In an embodiment, the mappings that address mapping interconnects 155a-155c apply may be selected from a set of row address bit permutations. For example, address mapping interconnects 155a-155c may each circularly left shift (or circularly right shift) the CA interface 151 received row address to generate row addresses that are provided to CA interfaces 111a-111c that each select a different row in their respective memory arrays 130a-130c.

[0024] It should be understood that in some instances, multiple neighboring rows may be affected by row hammer. In an embodiment, address mapping interconnects 155a-155c may be selected to ensure the two (or more) nearest neighbors on either side of the hammered row are unique in each memory device 110a-110c being accessed. For example, circularly left shifting (or right shifting) by two bits increases the number of unique neighbor row addresses that are next to a hammered row.

[0025] Table 1 illustrates an abbreviated example of unique bit shifts per memory device 110a-110c that may be provided by address mapping interconnects 155a-155c to translate CA interface 151 received row addresses to unique memory device 110a-110c received row addresses that result in accesses to a given CA interface 151 received address having different neighboring rows internal to each memory device 110a-110c of memory module 150. The CA interface 151 received and the memory device 110a-110c received addresses in Table 1 are given in hexadecimal format. In the example of Tables 1, memory arrays 130a-130c have 32 rows resulting in 5-bit internal and external row addresses.

[0026]

TABLE 1
	DRAM#0	DRAM#1	DRAM #2
	Controller	Controller	Controller
	Row	Row	Row
	Address that	Address that	Address that
	Maps to	Maps to	Maps to
	memory array	memory array	memory array
	internal	internal	internal
	row address	row address	row address
Device CA	shown in First	shown in First	shown in First
received	Column of	Column of	Column of
and/or	this Table	this Table	this Table
corresponding	Circular left	Circular left	Circular left
DRAM Core	shift of	shift of	shift of
Row	Controller	Controller	Controller
(Internal Row	Row Address	Row Address	Row Address
Address)	by 0 bits	by 1 bit	by 2 bits	. . .
00	00	00	00	. . .
01	01	10	08
02	02	01	10
03	03	11	18
04	04	02	01
05	05	12	09
. . .	. . .	. . .	. . .
1C	1C	0E	07
1D	1D	1E	0F
1E	1E	0F	17
1F	1F	1F	1F

[0027] In an embodiment, control circuitry 113a-113c may receive and perform commands that have operands and/or data communicated via signal lines that have been mapped by address mapping interconnects 155a-155c. Reconstruction circuitry 114a-114c may be configured to respectively undo (i.e., unmap) the mapping applied by address mapping interconnects 155a-155c. In this manner, the operands and/or data communicated via signal lines that have been mapped by address mapping interconnects 155a-155c may be correctly interpreted and/or used by control circuitry 113a-113c. Sources of information to configure reconstruction circuitry 114a-114c may include serial presence detect storage on memory module 150, commands from controller 120, hardwired external configuration signals, etc.

[0028] In an embodiment, to develop the configuration information and/or configure reconstruction circuitry, controller 120 may place one or more memory devices 110a-110c in a training mode. Controller 120 may then transmit a training sequence of addresses to memory module 150 (e.g., a walking “1” or “0” pattern). When the training sequence is transformed by address mapping interconnects 155a-155c on memory module 150, each memory device 110a-110c receives a modified (e.g., with permuted and/or inverted bits) training sequence. Based on the respective modified training sequence that each memory device 110a-110c receives, the respective control circuitry 113a-113c determines a respective reverse transformation (i.e., reconstruction transformation) and/or configuration of reconstruction circuitry 114a-114c that undoes the effects of the address mapping interconnects 155a-155c connected to that respective memory device 110a-110c.

[0029] FIG. 2 is a block diagram illustrating an example buffered memory module system. In FIG. 2, memory system 200 comprises controller 220 and memory module 250. Controller 220 includes data (DQ) interfaces 222a-222c, command/address interface 221, reliability, availability, and serviceability (RAS) circuitry 223 (e.g., error detect and correct-EDC, error correcting code—ECC, chipkill SDDC, memory scrubbing, etc. circuitry), and control circuitry 229. DQ interfaces 222a-222c and command/address interface 221 are operatively coupled with memory module 250 (i.e., DQ interfaces 222a-222c and command/address interface 221 form a controller memory channel interface comprising command/address and data functions.)

[0030] Memory module 250 includes memory devices 210a-210c, registering clock driver (RCD) 219, command/address (CA) interface 251, data (DQ) interfaces 252a-252c, and address mapping interconnect 255a-255c. DQ interfaces 252a-252c of memory module 250 are respectively operatively coupled to DQ interfaces 222a-222c of controller 220. DQ interfaces 252a-252c of memory module 250 are respectively operatively coupled to DQ interfaces of memory devices 210a-210c. Thus, the DQ interfaces of memory devices 210a-210c are operatively coupled to DQ interfaces 222a-222c of controller 220 via DQ interfaces 252a-252c of memory module 150. The DQ interfaces of memory devices 210a-210c are operatively coupled to controller 220 to at least communicate data to be written/read to/from memory devices 210a-210c, respectively.

[0031] Command address interface 251 is operatively coupled to RCD 219—alternatively called a “Address-buffer component”. RCD 219 is operatively coupled to memory devices 210a-210c. RCD 219 is operatively coupled to memory devices 210a-210c to selectively interpret and retransmit, to memory devices 210a-210c, the control signals and addresses transmitted by controller 220 via CA interface 221 and received by memory module 250 via CA interface 251.

[0032] Memory devices 210a-210c receive commands/addresses from controller 220 via RCD 219. Memory device 210a receives commands/addresses from RCD 219 via address mapping interconnect 255a. Memory device 210b receives commands/addresses from RCD 219 via address mapping interconnect 255b. Memory device 210c receives commands/addresses from RCD 219 via address mapping interconnect 255c, and so on for other devices that may be included on memory module 250.

[0033] In an embodiment, the address translations made by address mapping interconnects 255a-255c as they couple RCD 219 to memory devices 210a-210a are unique to each memory device 210a-210c. These unique mappings may be selected such that row hammer affects different neighboring row address in each memory device 210a-210c are reduced, mitigated, or eliminated. The address mappings implemented by address mapping interconnects 255a-255c as they couple RCD 219 to memory devices 210a-210c are selected to ensure that each set of neighboring rows inside of memory devices 210a-210c are different for each memory device 210a-210c on memory module 250. Thus, row hammering of a given addressed row (via CA interface 221 and CA interface 251) is spread across different internally addressed rows on respective memory devices 210a-210c. This has the effect of confining row hammer errors for each internal row that is hammered to a single memory device per controller 220 addressed neighboring row (per column access). By confining the row hammer errors to a single memory device 210a-210c, the row hammer errors are correctible by RAS circuitry 223 using, for example, a SDDC scheme.

[0034] In an embodiment, as described herein with reference to FIG. 1, the mappings that address mapping interconnects 255a-255c apply may be selected from a set of row address bit permutations. For example, address mapping interconnects 255a-255c may each circularly left shift (or circularly right shift) the controller 220 transmitted row address to generate row addresses that are provided to CA interfaces 211a-211c that each select a different row in their respective memory arrays 230a-230c. It should be understood that in some instances, multiple neighboring rows may be affected by row hammer. In an embodiment, address mapping interconnects 255a-255c may be selected to ensure the two (or more) nearest neighbors on either side of the hammered row are unique in each memory device 210a-210c being accessed. For example, circularly left shifting (or right shifting) by two bits increases the number of unique neighbor row addresses that are next to a hammered row.

[0035] As illustrated by the multiple arrows coming from RCD 219 that represent multiple CA interfaces, the set of memory devices 210a-210c that work together on a Read or a Write can be split among these multiple CA interfaces coming out of the RCD 219. It should then be understood, for example, that 8-10 memory devices 210a-210c on module 250 may respond to a Read or Write command. If all memory devices 210a-210c on module 250 were on the same CA interface coming from the RCD 219 the electrical loading may make signal integrity very difficult to achieve. Thus RCD 219 may have multiple CA interfaces (“arms”) with a portion (e.g., one-half, one-quarter, etc.) of the memory devices 210a-210c on module 250 on a given, single, CA interface, and the other portion(s) on another CA interface(s). In an embodiment, module 250 may implement different address maps on each arm. Module 250 may implement different address maps on each arm such that all memory devices 210a-210c on both arms have unique internal neighboring rows for each external row address (because all memory devices 210a-210c on both arms work together to reply to each Read/Write request).

[0036] FIG. 3 is a flowchart illustrating a method of operating a memory module. One or more steps illustrated in FIG. 3 may be performed by, for example, memory system 100, memory system 200, and/or their components. Via a command/address interface, a first row address composed of a first plurality of address bits is received (302). For example, memory module 150 may receive, from controller 120, a first row address associated with a command (e.g., activate command).

[0037] By a first dynamic random access memory (DRAM) device on the memory module that includes a first memory array, a second row address composed of a first permutation of the first plurality of address bits is received (304). For example, memory device 110a may receive a second row address that is at least a permutation, by address mapping interconnect 155a, of the bits of the first address. Based on the second row address, a first row in the first memory array that has a first internal row address is accessed, where the first row is physically next to a first neighboring row having a first internal neighboring row address (306). For example, based on the second row address, memory device 110a may access row 132a that is physically next to row 131a.

[0038] By a second DRAM device on the memory module that includes a second memory array, a third row address composed of a second permutation of the first plurality of address bits is received (308). For example, memory device 110b may receive a third row address that is at least a permutation, by address mapping interconnect 155b, of the bits of the first address.

[0039] Based on the third row address, a second row is accessed in the second memory array that has a second internal row address, where the second row is physically next to a second neighboring row having a second internal neighboring row address, and where a first external row address received via the command/address interface that maps to the first internal neighboring row address and a second external row address received via the command/address interface that maps to the second internal neighboring row address are not equal (310). For example, based on the third row address, memory device 110b may access row 134b that is physically next to row 133b, where the internal addresses of row 131a and row 133b are not equal.

[0040] FIG. 4 is a flowchart illustrating a method of determining a transformation to reverse an interconnect based address transformation. One or more steps illustrated in FIG. 4 may be performed by, for example, memory system 100, memory system 200, and/or their components. By a memory module, a first row address map training sequence is received (402). For example, controller 120 may transmit, via CA interface 151 and to CA interface 151, a first training sequence to be used by memory devices 110a-110c to find, or determine, the effects, mappings, and/or transformations made by address mapping interconnects 155a-155c, respectively. For example, controller 120 may transmit a “walking” one or zero pattern where the first address in the sequence is all zeros except for the least significant bit, the second address in the sequence is all zeros except for the second least significant bit, the third address in the sequence is all zeros except for the third least significant bit, and so on.

[0041] By the memory module, the first row address map training sequence is transformed to a second row address map training sequence (404). For example, the training sequence transmitted by controller 120 may be transformed by address mapping interconnect 155a on memory module 150 into a second training sequence, derived from the first training sequence by the permutation and/or inversion of bits from the first training sequence by address mapping interconnect 155a. By a first memory device on the memory module, the second row address map training sequence is received (406). For example, memory device 110a may receive the second training sequence, which was derived from the first training sequence by a permutation and/or inversion of bits by address mapping interconnect 155a.

[0042] Based on the received second row address map training sequence, a reverse transformation is determined that reverses the memory module transform of the first row address map training sequence (408). For example, control circuitry 113a may, based on the second training sequence, determine what permutation and/or inversions were applied to the first training sequence by address mapping interconnect 155a. Once the permutation and/or inversions applied by address mapping interconnect 155a are known, control circuitry 113a can determine how to configure reconstruction circuitry 114a to undo the permutation and/or inversions.

[0043] FIG. 5 is a flowchart illustrating a method of determining address transformations. One or more steps illustrated in FIG. 5 may be performed by, for example, memory system 100, memory system 200, and/or their components. By a memory module that includes a first memory device and a second memory device, a first training sequence of address values is received (502). For example, controller 120 may transmit, via CA interface 151 and to CA interface 151, a first training sequence of address values to memory module 150 that the memory devices 110a-110c on memory module 150 may use to find, or determine, the effects, mappings, and/or transformations made by address mapping interconnects 155a-155c, respectively. For example, controller 120 may transmit a “walking” one or zero pattern to memory module 150.

[0044] Using a first permutation of bits in the address values and by the memory module, the first training sequence of address values are transformed into a first transformed sequence of address values (504). For example, the address values in the training sequence transmitted by controller 120 may be transformed by address mapping interconnect 155a on memory module 150 into a first transformed training sequence of address values that is derived from the training sequence transmitted by controller 120 by the permutation and/or inversion of bits from the training sequence by address mapping interconnect 155a.

[0045] By the first memory device, the first transformed sequence of address values is received (506). For example, memory device 110a may receive the address values of the first transformed training sequence of address values. Memory device 110a may, for example, transmit the first transformed sequence of address values to controller 120 for analysis. Memory device 110a may, for example, transmit the first transformed sequence of address values to controller 120 for analysis using DQ interface 112a. Using a second permutation of bits in the address values and by the memory module, the first training sequence of address values are transformed into a second transformed sequence of address values (508). For example, the address values in the training sequence transmitted by controller 120 may be transformed by address mapping interconnect 155b on memory module 150 into a second transformed training sequence of address values that is derived from the training sequence transmitted by controller 120 by the permutation and/or inversion of bits from the training sequence by address mapping interconnect 155b.

[0046] By the second memory device, the second transformed sequence of address values is received (510). For example, memory device 110b may receive the address values of the second transformed training sequence of address values. Memory device 110b may, for example, transmit the first transformed sequence of address values to controller 120 for analysis. Memory device 110b may, for example, transmit the first transformed sequence of address values to controller 120 for analysis via DQ interface 112b. Based on the first transformed sequence of address values, it is determined that the first memory device is receiving addresses that have been transformed by at least the first permutation (512). For example, control circuitry 113a and/or controller 120 may, based on first transformed sequence of address values, determine that the first permutation was applied to the first training sequence of address values by address mapping interconnect 155a before being received by memory device 110a. Based on the second transformed sequence of address values, it is determined that the second memory device is receiving addresses that have been transformed by at least the second permutation (514). For example, control circuitry 113b and/or controller 120 may, based on second transformed sequence of address values, determine that the second permutation was applied to the first training sequence of address values by address mapping interconnect 155b before being received by memory device 110b.

[0047] FIG. 6 is a flowchart illustrating a method of reversing address transformations. One or more steps illustrated in FIG. 6 may be performed by, for example, memory system 100, memory system 200, and/or their components. A first indicator that a first memory device on a memory module is receiving addresses that have been transformed by at least a first permutation is received (602). For example, controller 120 may receive information (e.g., from memory module 150, a host, SPD circuitry on memory module 150 etc.) indicating that address mapping interconnect 155a will permute, with a first permutation, row address transmitted by controller 120 to memory module 150. A second indicator that a second memory device on a memory module is receiving addresses that have been transformed by at least a second permutation is received (604). For example, controller 120 may receive information (e.g., from memory module 150, a host, SPD circuitry on memory module 150 etc.) indicating that address mapping interconnect 155b will permute, with a second permutation, row address transmitted by controller 120 to memory module 150.

[0048] The first memory device is configured to reverse the first permutation on received addresses (606). For example, controller 120 may configure reconstruction circuitry 114a to reverse the effects of address mapping interconnect 155a. The second memory device is configured to reverse the second permutation on received addresses (608). For example, controller 120 may configure reconstruction circuitry 114b to reverse the effects of address mapping interconnect 155b.

[0049] A first address is transmitted to the memory module (610). For example, controller 120 may transmit an address to memory module 150 in association with a command to set a register. By the first memory device, an unpermuted version of the first address is used (612). For example, memory device 110a may use an unpermuted version, as reconstructed by reconstruction circuitry 114a, of the address transmitted in association with the command to set a register. By the second memory device, an unpermuted version of the first address is used (614). For example, memory device 110b may use an unpermuted version, as reconstructed by reconstruction circuitry 114b, of the address transmitted in association with the command to set a register.

[0050] FIG. 7 is a flowchart illustrating a method of transmitting addresses. One or more steps illustrated in FIG. 7 may be performed by, for example, memory system 100, memory system 200, and/or their components. A first indicator that a first memory device on a memory module is receiving addresses that have been transformed, by the memory module and by a first transformation that includes a first permutation (702). For example, controller 120 may receive information indicating that addresses transmitted to memory module 150 will be transformed by address mapping interconnect 155a before being received by memory device 110a, where address mapping interconnect 155a performs a first permutation of the address bits (e.g., circular left shift by 1 bit).

[0051] A second indicator that a second memory device on the memory module is receiving addresses that have been transformed, by the memory module and by a second transformation that includes a second permutation that is not equivalent to the first permutation (704). For example, controller 120 may receive information indicating that addresses transmitted to memory module 150 will be transformed by address mapping interconnect 155b before being received by memory device 110b, where address mapping interconnect 155b performs a second permutation of the address bits that is not equivalent to the first permutation (e.g., circular left shift by 2 bits).

[0052] To a first address value, a first reverse transformation of the first transformation is applied to generate a second address value (706). For example, in order to send a first address value (e.g., ‘00000001’) to memory device 110a, controller 120 may apply a reverse transformation (e.g., circular right shift by 1 bit) of the first permutation (e.g., circular left shift by one bit) to generate a second address value (e.g., ‘10000000’) that is the reverse transformed version of the first address value. The second address value is transmitted to the memory module (708). For example, controller 120 may transmit the reverse transformed first address value (e.g., ‘10000000’) By the first memory device, the first address value is received (710). For example, the reverse transformed value sent by controller 120 may be transformed by address mapping interconnect 155a from the second address value (e.g., ‘10000000’) back in to the first address value (e.g., ‘00000001’ and then is received by memory device 110a.

[0053] To the first address value, a second reverse transformation of the second transformation is applied to generate a third address value (712). For example, in order to send a first address value (e.g., ‘00000001’) to memory device 110b, controller 120 may apply a reverse transformation (e.g., circular right shift by 2 bits) of the second permutation (e.g., circular left shift by two bits) to generate a third address value (e.g., ‘01000000’) that is the second reverse transformed version of the first address value. The third address value is transmitted to the memory module (714). For example, controller 120 may transmit the second reverse transformed first address value (e.g., ‘01000000’) By the second memory device, the first address value is received (716). For example, the second reverse transformed value sent by controller 120 may be transformed by address mapping interconnect 155b from the third address value (e.g., ‘01000000’) back in to the first address value (e.g., ‘00000001’ and then is received by memory device 110a.

[0054] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, memory system 200, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0055] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3½ inch floppy media, CDs, DVDs, and so on.

[0056] FIG. 8 is a block diagram illustrating one embodiment of a processing system 800 for including, processing, or generating, a representation of a circuit component 820. Processing system 800 includes one or more processors 802, a memory 804, and one or more communications devices 806. Processors 802, memory 804, and communications devices 806 communicate using any suitable type, number, and/or configuration of wired and/or wireless connections 808.

[0057] Processors 802 execute instructions of one or more processes 812 stored in a memory 804 to process and/or generate circuit component 820 responsive to user inputs 814 and parameters 816. Processes 812 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and/or verify electronic circuitry and/or generate photomasks for electronic circuitry. Representation 820 includes data that describes all or portions of memory system 100, memory system 200, and their components, as shown in the Figures.

[0058] Representation 820 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 820 may be stored on storage media or communicated by carrier waves.

[0059] Data formats in which representation 820 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0060] User inputs 814 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 816 may include specifications and/or characteristics that are input to help define representation 820. For example, parameters 816 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and/or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0061] Memory 804 includes any suitable type, number, and/or configuration of non-transitory computer-readable storage media that stores processes 812, user inputs 814, parameters 816, and circuit component 820.

[0062] Communications devices 806 include any suitable type, number, and/or configuration of wired and/or wireless devices that transmit information from processing system 800 to another processing or storage system (not shown) and/or receive information from another processing or storage system (not shown). For example, communications devices 806 may transmit circuit component 820 to another system. Communications devices 806 may receive processes 812, user inputs 814, parameters 816, and/or circuit component 820 and cause processes 812, user inputs 814, parameters 816, and/or circuit component 820 to be stored in memory 804.

[0063] Implementations discussed herein include, but are not limited to, the following examples:

[0064] Example 1: A memory module, comprising: a command/address interface to receive a first row address; a first memory device including a first memory array, the first memory device to receive a second row address generated from the first row address using a first mapping, the second row address to access a first row in the first memory array having a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address; and a second memory device including a second memory array, the second memory device to receive a third row address generated from the first row address using a second mapping, the third row address to access a second row in the second memory array having a second internal neighboring row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, wherein the first internal neighboring row address and the second internal neighboring row address do not address a same row.

[0065] Example 2: The memory module of example 1, wherein the first mapping comprises a first permutation function relating signals of the command/address interface to command/address signals of a first device command/address interface of the first memory device and the second mapping comprises a second permutation function relating signals of the command/address interface to signals of a second device command/address interface of the second memory device.

[0066] Example 3: The memory module of example 2, wherein the first mapping further comprises an inversion of a first signal between the command/address interface and the first device command/address interface of the first memory device.

[0067] Example 4: The memory module of example 2, further comprising a buffer integrated circuit that receives the signals of the command/address interface and transmits, to the first device command/address interface of the first memory device, a first permutation of the signals of the command/address interface made according to the first permutation function.

[0068] Example 5: The memory module of example 2, wherein the first permutation function circularly shifts the first row address by a first number of bits when mapping the first row address to the second row address, and the second permutation function circularly shifts the first row address by a second number of bits when mapping the first row address to the third row address.

[0069] Example 6: The memory module of example 3, further comprising a buffer integrated circuit that performs the inversion.

[0070] Example 7: The memory module of example 1, wherein the first memory device includes circuitry to, when in a first operating mode, translate the second row address to the first row address.

[0071] Example 8: The memory module of example 1, wherein the second memory device includes circuitry to, when in a second operating mode, translate the third row address to the first row address.

[0072] Example 9: A memory module, comprising: a command/address interface comprising a first plurality of command/address signals to receive a plurality of external row addresses; first signal interconnections operatively coupling the command/address interface and a first device command/address interface of a first memory device, the first signal interconnections implementing a first permutation of the first plurality of command/address signals between the command/address interface and the first device command/address interface; second signal interconnections operatively coupling the command/address interface and a second device command/address interface of a second memory device, the second signal interconnections implementing a second permutation of the first plurality of command/address signals between the command/address interface and the second device command/address interface, wherein the first permutation and the second permutation are not functionally equivalent.

[0073] Example 10: The memory module of example 9, wherein the command/address interface is to receive a first row address and the first permutation causes the first device command/address interface to receive a second row address, the second row address to access a first row in a first memory array of the first memory device having a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address.

[0074] Example 11: The memory module of example 10, wherein the second permutation causes the second device command/address interface to receive a third row address, the third row address to access a second row in a second memory array of the second memory device having a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, wherein the first internal neighboring row address and the second internal neighboring row address are to be not equal.

[0075] Example 12: The memory module of example 11, wherein the first memory device comprises circuitry to undo the first permutation and the second memory device comprises circuitry to undo the second permutation.

[0076] Example 13: The memory module of example 12, wherein the first memory device undoes the first permutation based on receiving a mode setting command and the second memory device undoes the second permutation based on receiving the mode setting command.

[0077] Example 14: The memory module of example 13, wherein the first memory device comprises circuitry to detect the first permutation and configure the first memory device to undo the first permutation, and the second memory device comprises circuitry to detect the second permutation and configure the second memory device to undo the second permutation.

[0078] Example 15: A method of operating a memory module, comprising: receiving, via a command/address interface, a first row address composed of a first plurality of address bits; receiving, by a first dynamic random access memory (DRAM) device on the memory module that includes a first memory array, a second row address composed of a first permutation of the first plurality of address bits; based on the second row address, accessing a first row in the first memory array that has a first internal row address, the first row to be physically next to a first neighboring row having a first internal neighboring row address; receiving, by a second DRAM device on the memory module that includes a second memory array, a third row address composed of a second permutation of the first plurality of address bits; and based on the third row address, accessing a second row in the second memory array that has a second internal row address, the second row to be physically next to a second neighboring row having a second internal neighboring row address, wherein a first external row address received via the command/address interface that maps to the first internal neighboring row address and a second external row address received via the command/address interface that maps to the second internal neighboring row address are not equal.

[0079] Example 16: The method of example 15, further comprising: mapping, by a first interconnect network on the memory module, the first row address to the second row address; and mapping, by a second interconnect network on the memory module, the first row address to the third row address.

[0080] Example 17: The method of example 15, wherein the first permutation of the first plurality of address bits is a first circular shift of the first row address by a first number of bits, and the second permutation of the first plurality of address bits is a second circular shift of the first row address by a second number of bits, wherein the first number of bits and the second number of bits produce circularly shifted outputs that are not equivalent.

[0081] Example 18: The method of example 15, further comprising: receiving a training sequence via the command/address interface; based on the training sequence, determining, by the first DRAM device, a third permutation function that reverses the first permutation; and based on the training sequence, determining, by the second DRAM device, a fourth permutation function that reverses the second permutation.

[0082] Example 19: The method of example 18, further comprising: receiving, via the command/address interface, first data composed of a first plurality of data bits; and by the first DRAM device, using the third permutation function to generate second data from the first plurality of data bits.

[0083] Example 20: The method of example 19, further comprising: by the second DRAM device, using the fourth permutation function to generate the second data from the first plurality of data bits.

[0084] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.