Intelligent semiconductor switch

[0001] This application claims priority to German Application No. 102022106935.4, filed on Mar. 24, 2022, which application is hereby incorporated herein by reference.

[0002] The present description relates to the field of smart semiconductor switches, which, besides the switching element (e.g. a MOS transistor), comprise further circuits for “smart” operation of the switch.

[0003] A wide variety of types of smart semiconductor switches are known for different applications (e.g. in automotive or industrial applications). Such semiconductor switches contain further circuits besides the actual switch (usually a high-side power MOSFET), for example in order to switch the switch on and off and in order to output diagnostic information (e.g. load current, temperature, etc.) if appropriate or to protect the switch against overload (e.g. due to excessive temperature or excessive load currents). A smart semiconductor switch can also comprise multiple channels, each of which contains a switch for driving a load.

[0004] Smart semiconductor switches can comprise temperature sensors, and also a protective circuit that deactivates the switch in the event of excessive temperature in order to prevent a thermal overload. In some applications, both the junction temperature of the semiconductor switch and a chip temperature away from the semiconductor switch are measured. The protective circuit can then evaluate e.g. the temperature difference between the junction temperature and the chip temperature away from the semiconductor switch. A current measuring circuit may also be implemented in order to measure the load current flowing through the semiconductor switch. In the simplest case, a current measuring resistor can be used for current measurement. However, other approaches for current measurement are also known, such as e.g. the use of a few transistor cells as a “sense transistor”. The thresholds for an overcurrent tripping or an overtemperature tripping can be configurable, with the result that the smart semiconductor switch can be matched to different applications.

[0005] For some applications, such as for example switching capacitive loads, existing concepts are inflexible, and the inventors have identified a need for improvements.

[0006] In various embodiments, the present disclosure provides a circuit for a smart semiconductor switch. According to one exemplary embodiment, the circuit includes: an electronic switch electrically coupled between an output node and a supply node; an overcurrent protective circuit configured to generate an overcurrent signal in response to a load current flowing through the electronic switch exceeding a first overcurrent threshold, and to cause the electronic switch to be tripped; and a control circuit configured to in a first mode, switch the electronic switch on and off based on an input signal, and, in a second mode, drive a load connected to the output node by repeatedly switching the electronic switch on and off, and prevent the electronic switch from being permanently tripped by the overcurrent protective circuit.

[0007] In addition, a method for a smart semiconductor switch is provided in one or more embodiments. According to one exemplary embodiment, the method includes switching an electronic switch on and off based on an input signal in a first mode, the electronic switch being electrically coupled between an output node and a supply node. The method further includes causing the electronic switch to be tripped in response to detecting that a load current flowing through the electronic switch has exceeded a first overcurrent threshold. In addition, the method includes driving a load connected to the output node by repeatedly switching the electronic switch on and off in a second mode and preventing the electronic switch from being permanently.

[0008] In one or more embodiments, a device is provided that includes a capacitive load switching mode detection circuit configured to output a capacitive load switching signal based on an input signal. A control circuit is configured to activate a normal mode or a capacitive load switching mode based on the capacitive load switching signal. An overcurrent threshold generation circuit is configured to generate a first overcurrent threshold in the normal mode and a second overcurrent threshold in the capacitive load switching mode, and the second overcurrent threshold is higher than the first overcurrent threshold. An overcurrent protective circuit is configured to: generate a first overcurrent signal in response to a load current flowing through the electronic switch exceeding the first overcurrent threshold in the normal mode; and generate a second overcurrent signal in response to the load current exceeding the second overcurrent threshold in the capacitive load switching mode.

[0018] Before various exemplary embodiments are discussed in more detail, an example of a smart semiconductor switch will first be explained. The example depicted in FIG. 1 shows a smart semiconductor switch having one channel, i.e. one power transistor T_S for driving a load. It goes without saying that the concepts described here can also be applied to multichannel systems. The switching element in the example shown is a MOS transistor, in particular a MOSFET (metal-oxide semiconductor field effect transistor) in the form of a DMOS field effect transistor (double-diffused metal-oxide semiconductor field effect transistor). It goes without saying that other types of electronic switches may also be used, such as e.g. bipolar transistors, IGBTs (insulated gate bipolar transistors) or the like.

[0019] In the example depicted in FIG. 1, the switching element (power transistor T_S) is connected between an output node OUT and a supply node VS. Both the output node OUT and the supply node VS can be connected directly (e.g. by way of bonding wires or the like) to appropriate chip contacts (e.g. pins). That is to say that when the power transistor T_S is activated (on) the load current flows from the supply node VS (which is connected to a power supply) via the load current path of the power transistor T_S to the output node OUT, which, during operation, is connected to a load that is symbolized by the resistor R_L in FIG. 1. In the present case, the power transistor T_S operates as a high-side switch. It goes without saying that the concepts described here can also be applied to systems containing low-side switches.

[0020] The fact that the power transistor T_S is connected between the nodes VS and OUT does not preclude a further element such as e.g. the current measuring resistor R_S from being able to be arranged between the power transistor T_S and one of the nodes VS or OUT. In the example shown, the measuring resistor R_S (sense resistor) is connected between the source electrode of the (n-channel) power transistor T_S and the nodes OUT. The voltage drop i_L·R_S across the measuring resistor R_S represents the load current i_L flowing through the load current path (in the case of a MOS transistor the drain-source current path) of the transistor.

[0021] The control electrode of the power transistor T_S (in the case of a MOS transistor the gate electrode) is driven by a gate driver circuit ii. Said circuit is designed to take a logic signal ON (input signal of the gate driver) as a basis for switching the power transistor T_S on and off. The gate driver 11 may also be designed to control the gradient of the switching edges (i.e. the slew rate). In the example shown, the slew rate is dependent on the signal SR supplied to the gate driver 11. Suitable gate driver circuits are known per se and are therefore not discussed in more detail here.

[0022] The logic signal ON is the result of a logic function relating to multiple other logic signals. In the example shown, the logic signal ON is output by the AND gate 13, which performs the function ON=OT·IN′·OC. The dot (“·”) denotes a logic AND function and the overline above OT and OC denotes a negation. OT is a logic signal that indicates an overtemperature state, and OC is a logic signal that indicates an overcurrent state. In the example shown, both an overtemperature state (OT=1, OT=0) and an overcurrent state (OC=1, OC=0) result in the power transistor T_S being tripped. The logic signal IN′ can be regarded as a switching command for switching the transistor T_S on and off. It is dependent on the input signal received at the input node IN. The logic signal IN′ signals that the transistor T_S is switched on if either the input signal received at the input node IN indicates a logic “1” or the signal CLS indicates a logic “1”. CLS can also be understood as the abbreviation for “capacitive load switching” (switching a capacitive load). In the example shown, this OR function is performed by the OR gate 14, the output signal from which is the logic signal IN′. The CLS mode will be explained in more detail later on, but overcurrent and overtemperature protection are discussed first.

[0023] The overcurrent protective circuit 31 depicted in FIG. 1 is designed to compare the current measurement signal with an associated threshold. In the present example, the overcurrent protective circuit 31 signals an overcurrent state (OC=1) if the load current i_L exceeds the associated threshold i_OCT (e.g. i_L·R_S>i_OCT·R_S). Essentially, the overcurrent protective circuit 31 contains a comparator circuit. Suitable comparator circuits are known per se and are therefore not discussed further here. The specific implementation of the overcurrent protective circuit 31 is also dependent, inter alia, on the current measuring circuit used. Instead of the current measuring resistor R_S shown, a so-called sense FET arrangement can also be used, in which some transistor cells of the power transistor are used for current measurement.

[0024] The threshold i_OCT is configurable and, in the example shown, is generated by the circuit 32 (denoted by “overcurrent threshold generation” in FIG. 1) on the basis of the input from an external circuit. The overcurrent protective circuit 31 receives the present threshold i_OCT from the circuit 32. The latter can receive a signal containing information about the desired threshold i_OCT from an external circuit, e.g. an external controller. In one example, the circuit 32 can communicate with an external controller by way of a digital communication interface, for example by means of an SPI (Serial Peripheral Interface). Alternatively, configuration of the threshold by means of a component (e.g. resistor) connected to a configuration pin is also possible (cf. FIG. 5).

[0025] In the example shown, two temperature values are measured. A first temperature value T_J represents the temperature of the transistor cell array of the power transistor T_S, ideally the junction temperature of the power transistor. Alternatively, a temperature measurement in the hot area close to the transistor is also possible. A second temperature value T_A represents the chip temperature away from the power transistor, i.e. at a comparatively “cool” place on the semiconductor chip as far away as possible from the “Hot-Spot” in the transistor cell array. Suitable temperature sensors integrated in the chip are known per se and are therefore not described further here. The overtemperature protective circuit 23 is designed to take the two temperature measured values T_J and T_A as a basis for indicating an overtemperature state (OT=1).

[0026] An overtemperature state can be triggered by various circumstances. By way of example, the overtemperature protective circuit 23 may signal an overtemperature state if the junction temperature T_J of the transistor T_S exceeds a temperature threshold, which in some embodiments may represent a permissible maximum value T_J,max(T_J>T_J,max). Furthermore, the overtemperature protective circuit 23 may signal an overtemperature state if the temperature difference T_J-T_A exceeds a temperature difference threshold, which in some embodiments may represent a permissible maximum value ΔT_max (T_J−T_A>ΔT_max). The overtemperature protective circuit 23 (i.e. the comparator contained therein) can exhibit a hysteresis. As such, for example an overtemperature state may be signalled if the condition T_J−T_A>ΔT_max is satisfied, but the overtemperature state can be cancelled again only if the condition T_J−T_A<ΔT_max−T_H is satisfied. The value T_H here represents the hysteresis. In particular, the values ΔT_max and T_H are configurable. The value T_J,max may also be configurable (for example by means of a digital communication interface). The thresholds ΔT_max and ΔT_max−T_H may also be dependent on whether the smart semiconductor switch operates in a CLS mode, which is described below.

[0027] As mentioned, CLS denotes switching on a capacitive load (capacitive load switching). Depending on the implementation, the CLS mode can be activated in different ways. By way of example, there may be provision for a specific chip pin, and the CLS mode can be activated if e.g. a high level is applied to this chip pin. In the example shown, the circuit 21 (denoted by “CLS mode detection” in FIG. 1) detects and activates the CLS mode if a pulse-width-modulated (PWM) signal having e.g. a duty cycle of 50 percent and a defined frequency is applied to the input node IN. This frequency can be e.g. in the kilohertz range (e.g. 30 kHz). The circuit 21 can detect this frequency in the input signal and use a high level of the logic signal CLS to indicate the CLS mode (CLS=1). A low level of the logic signal CLS signals a normal mode, in which the transistor T_S is switched on if the signal applied to the input node has a high level.

[0028] The transistor T_S is also activated/switched on in the CLS mode, but the transition to the CLS mode results in some operating parameters of the smart semiconductor switch being altered. In the example shown in FIG. 1, the circuit 22 (denoted by “CLS settings” in FIG. 1) is designed to reconfigure the gate driver 11 in such a way that the slew rate (SR) of the switching edges is lowered (compared to the normal mode). In addition, the circuit 22 may be designed to reconfigure the parameters (temperature thresholds and hysteresis) of the overtemperature protective circuit 23 and to reset them to the previous (standard) values again on leaving the CLS mode.

[0029] When overcurrent protection is active, a problem can arise in the CLS mode that is explained below on the basis of the timing charts shown in FIG. 2. The top chart in FIG. 2 shows one possibility for activating the CLS mode, namely modulating the input signal supplied to the input node IN, said signal likewise being denoted by IN in FIG. 2. The modulation of the input signal is detected by the circuit 21, and the signal CLS is then set to high (CLS=1). Consequently, the logic signal IN′ changes to “high” (IN′=1) and so does the logic signal ON (ON=1), therefore, which results in the transistor T_S being switched on. FIG. 2 relates to the case of a capacitive load, resulting in a very high inrush current.

[0030] The high inrush current can result in very rapid heating of the transistor T_S and in an overcurrent tripping due to the condition T_J-T_A>ΔT_max (OT=0), the value T_J,max being able to be lower in the CLS mode than in the normal mode. As a consequence of the overcurrent tripping, the transistor T_S cools slightly (T_J-T_A<ΔT_max−T_H), resulting in the transistor T_S being switched on again. The hysteresis of the overtemperature protective circuit 23 results in toggling, i.e. regular switching of the transistor T_S off and on again, with the inrush current i_L charging the capacitance of the load further in each cycle and the output voltage V_OUT (i.e. the voltage V_OUT) rising somewhat in each cycle. This process is depicted in the middle chart in FIG. 2. The regular switching of the load current on and off (toggling) is depicted in the third chart in FIG. 2.

[0031] In one exemplary embodiment, the permissible maximum value T_J,max or the permissible maximum value ΔT_max (or both) is set to higher values in the CLS mode than in the normal mode. The permissible maximum values can be configured on the basis of the level of the logic signal CLS.

[0032] Regardless of whether different (higher) permissible maximum values are possibly used in the overtemperature protective circuit 23 in the CLS mode than in the normal mode, in practice it may be that during the “toggling” depicted in FIG. 2 a current peak triggers an undesirable overcurrent tripping in the CLS mode because the load current i_L exceeds the threshold i_OCT set for the respective application at least for a short time. In the example depicted in FIG. 2, the overcurrent tripping is triggered at the time t_A. Switching on again after an overcurrent event generally requires the smart semiconductor switch to be reset.

[0033] FIG. 3 shows a modification of the example from FIG. 1 that facilitates a solution to the problem explained on the basis of FIG. 2. The example depicted in FIG. 3 is broadly identical to the example from FIG. 1, and additional reference is made to the explanations above. The text below primarily discusses the differences between the examples from FIG. 3 and FIG. 1.

[0034] Specifically, unlike in the example from FIG. 1, the circuit 32 for generating the overcurrent threshold i_OCT in FIG. 3 is designed to generate a different overcurrent threshold for the overcurrent protective circuit 31 in the CLS mode than in the normal mode. While the smart semiconductor switch is not being operated in the CLS mode, the overcurrent threshold I_OCT corresponds to the configured value i_OCT,set. As already mentioned, the circuit 32 is designed to receive information relating to the desired threshold and to set the overcurrent threshold i_OCT accordingly. This information can be received via a digital communication interface, for example, or can also be ascertained on the basis of a device parameter of an external component connected to a chip pin (e.g. on the basis of the resistance value of a connected resistor, see FIG. 5). When the CLS mode is active, this configuration is overwritten (override) and the circuit 32 sets the overcurrent threshold i_OCT to a predefined or selected standard value i_OCT,max, which may correspond to a permissible maximum overcurrent threshold, for example. When the CLS mode is left, the overcurrent threshold i_OCT is reset from the predefined or selected standard value i_OCT,max to the previously configured i_OCT,set again.

[0035] The (undesirable) permanent overcurrent tripping, depicted in FIG. 2, when a capacitive load is switched on is prevented by temporarily raising the threshold i_OCT from i_OCT,set to i_OCT,max. In this context, “permanent” means “until a reset command is received”, since the detection of an overcurrent condition i_L>i_OCT is stored in a latch (flipflop). That is to say that, after an overcurrent state has been detected, the logic signal OT remains at a high level (OT=1) until the latch is reset. It is therefore not possible for the smart semiconductor switch to automatically switch on again. The reset command generally needs to be produced by an external controller. The control electronics of the smart semiconductor switch (in particular the circuit 21 for detecting the CLS mode and the circuit 32 for overcurrent threshold generation) are thus designed to prevent the electronic switch from being permanently tripped by the overcurrent protective circuit 31 (using the AND gate 13) in the CLS mode.

[0036] The way in which the circuit from FIG. 3 functions is explained in more detail below on the basis of the timing charts in FIG. 4. The top timing chart in FIG. 4 is the same as in FIG. 2, and in this example too the control command for activating the smart semiconductor switch in the CLS mode consists in a PWM signal with a e.g. 50 percent duty cycle and a defined frequency of e.g. 30 kHz being supplied to the input node IN. This input signal can be generated and supplied to the input node IN e.g. by an external controller (for example a microcontroller).

[0037] The bottom timing chart in FIG. 4 shows the characteristic of the load current i_L as the result of the regular switching of the power transistor T_S on and off (toggling), which, as explained above, is dependent on the temperature T_J of the power transistor T_S, in particular on the difference temperature T_J−T_A. The middle timing chart shows the resultant gradual rise in the output voltage V_OUT until (approximately) the level of the supply voltage V_S is reached (V_OUT≈V_S).

[0038] The bottom timing chart likewise depicts the overcurrent threshold i_OCT and also the “changeover” of the threshold i_OCT from the threshold i_OCT,set configured for the respective application to the standard (maximum) value i_OCT,max and back to the value i_OCT,set again. It can be seen that the temporary increase of the overcurrent threshold i_OCT prevents detection of an overcurrent state and the associated permanent tripping of the power transistor (i.e. until a reset command is received).

[0039] The circuit in FIG. 5 is a modification of the circuit from FIG. 3. In particular, FIG. 5 shows a possible implementation of the circuit 32 that generates the overcurrent threshold i_OCT for the overcurrent protective circuit 31. As shown in FIG. 5, the circuit 32 is connected to a configuration pin OC, to which an external resistor, denoted by R_OC in FIG. 5, can be connected during operation. The circuit 32 is designed to set the overcurrent threshold i_OCT on the basis of the resistance value of the external resistor R_OC. By way of example, the circuit 32 can apply a defined (e.g. constant) voltage U_ROC to the configuration pin OC and set the overcurrent threshold i_OCT on the basis of the resultant current U_ROC/R_OC. As in the previous examples already, the overcurrent threshold i_OCT is set to a standard value/maximum value if the signal CLS indicates the activation of the CLS mode. When the CLS mode ends, the overcurrent threshold i_OCT is reset to the value predefined by the external resistor R_OC again. Otherwise, the circuit from FIG. 5 is the same as that in FIG. 3, and reference is made to the above description in relation to FIG. 3.

[0040] As mentioned, the circuit 32 (optionally in combination with further circuit components) in the exemplary embodiments described here is designed to prevent the power transistor T_S from being permanently tripped (i.e. up to a reset) by the overcurrent protective circuit 31. According to the examples shown in FIGS. 3 and 5, this permanent tripping is prevented by temporarily—while the CLS mode is active—increasing the overcurrent threshold i_OCT. In the example from FIG. 6, this permanent tripping is prevented by temporarily, in particular while the CLS mode is active, deactivating the overcurrent circuit 31.

[0041] FIG. 6 shows a modification of the circuit from FIG. 3. As shown in FIG. 6, the logic signal CLS, which indicates an active CLS mode, is used as a disable signal DIS for the circuit 31. That is to say that the overcurrent protective circuit 31 is inactive while the CLS mode is active. The circuit 32 generates the desired/configured threshold i_OCT for example on the basis of the value of an external resistor. The components in FIG. 6 that are not explained at this juncture are the same as in FIG. 3, and reference is made to the description above.

[0042] According to a further exemplary embodiment, the aforementioned permanent tripping is prevented by virtue of the overcurrent protective circuit 31 being designed to signal an overcurrent state (OC=1) at least in the CLS mode only when the overcurrent condition i_L>i_OCT is satisfied for a determined, defined delay time. That is to say that an overcurrent state (OC=1) is signaled only after the delay time, and very short, transient incursions above the overcurrent threshold i_OCT are filtered/ignored. Suitable circuits that omit/suppress short, transient pulses shorter than the delay time in the logic signal OC are known per se and are therefore not discussed further here. The functioning of such a circuit, which may be contained in the overcurrent protective circuit 31, is shown in FIG. 7. Short, transient overcurrent states i_L>i_OCT such as for example at the time t₁ (see FIG. 7, overcurrent state from t₁ to t₁+T_P) do not result in tripping. As soon as the state i_L>i_OCT lasts for a defined delay time T_F, an overcurrent state is signalled by the logic signal OC=1 and tripping is triggered (see FIG. 7, overcurrent state from time t₂ results in tripping at the time t₂+T_F).

[0043] The example from FIG. 8 is a modification of the example from FIG. 3, in which a switch-on command for activating the power transistor in the normal mode, a command for activating (and optionally deactivating) the CLS mode and the overcurrent threshold to be set are received via a digital communication interface 35. In this example, the switch-on signal IN, which results in the power transistor T_S being switched on, is generated by the logic circuit 34 on the basis of the data received via the interface 35. The circuit 21 generates the logic signal CLS on the basis of the received data. As in the previous examples, a high level of the signal CLS indicates the CLS mode. FIG. 8 likewise shows an explicit reset for the overcurrent protective circuit 31 by way of a command received via the communication interface. In the example shown, the communication interface generates a reset signal RES for the overcurrent protective circuit 31, resulting in a signaled overcurrent state being cancelled and it being possible for the power transistor T_S to be switched on again. It goes without saying that in other exemplary embodiments the reset signal RES can also be generated in another way and does not necessarily have to be generated on the basis of data that are received via a digital interface.

[0044] It goes without saying that the circuits depicted in the figures are merely examples. A person skilled in the art is capable of also implementing the same or an equivalent function using (in part) other components. It goes without saying that logic levels at one or more nodes of the circuits can be inverted, which does not result in the functioning of the circuit being changed if the logic components are adapted as appropriate. All of the logic functions can therefore be implemented e.g. using NAND or NOR gates without significantly changing the functioning of the circuit by and large.