CMOS data clearing circuit

[0001] This application claims the priority benefit of Taiwan application serial no. 112115444, filed on Apr. 26, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

[0002] The disclosure generally relates to a data clearing circuit, and more particularly to a data clearing circuit for cleaning CMOS data of an electronic device.

[0003] Electronic devices encounter system instability, unstable power supply, etc. and cannot operate smoothly (or crash). Therefore, a user stops the electronic device from receiving power (for example, force shutdown, removes the power cord or battery), disassembles the casing of the electronic device, and finds a pin header for clearing CMOS data.

[0004] Generally, the pin header has three pins. A first pin of the pin header is floating. A second pin of the pin header is connected to the control chip of the electronic device. A third pin of the pin header is connected to a reference low voltage (for example, ground). The user first connects the second pin to the third pin using a jumper. After a few seconds, the user connects the second pin to the first pin and disconnects the connection between the second pin and the third pin.

[0005] It should be noted that the above operations on the pin header are performed by the user, such that the above operations consume labor costs and time costs. Therefore, how to provide a mechanism for automatically clearing CMOS data that can save labor costs and time costs is one of the research focuses of those skilled in the art.

[0006] The disclosure provides a CMOS data clearing circuit that can control an electronic device to clear CMOS data.

[0007] The CMOS data clearing circuit of the disclosure is used to clear the CMOS data of the main board of the electronic device. The electronic device includes a control chip and a pin header. The CMOS data clearing circuit includes a controller and a connection port. The controller generates a pulse signal and operation signals. The connection port has an input pin and an output pin. The output pin is coupled to a first pin of the pin header. The connection port conducts the input pin to the output pin in response to the operation signal, so as to transmit the pulse signal to the first pin of the pin header via the output pin. The control chip clears the CMOS data of the main board according to the pulse signal received by the first pin.

[0008] Based on the above, the controller generates a pulse signal in response to the operation signal. The control chip automatically clears the CMOS data in the main board based on the voltage variation of the pulse signal. In this way, the labor cost and time cost required for clearing CMOS data could be saved.

[0009] To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

[0015] Some embodiments of the disclosure accompanied with the drawings will now be described in detail. In the reference numerals recited in description below, the same reference numerals shown in different drawings will be regarded as the same or similar elements. These embodiments are only a part of the disclosure and do not disclose all possible implementations of the disclosure. To be more precise, these embodiments are only examples of the appended claims of the disclosure.

[0016] Please refer to FIG. 1, FIG. 1 illustrates a schematic diagram of a CMOS data clearing circuit according to an embodiment of the disclosure. In the embodiment, the CMOS data clearing circuit 100 is used to clear a CMOS data DT of an electronic device ED. The electronic device ED is, for example, a personal computer, a notebook computer, a tablet computer, or any form of system host, but the disclosure is not limited thereto. The electronic device ED includes a control chip CCP, a pin header HD and a main board MB. The control chip CCP clears the CMOS data DT based on the voltage variation of pins of the pin header HD. The control chip CCP is, for example, a South bridge chip. The control chip CCP and pin header HD are disposed on the main board MB. The pin header HD includes pins PIN1, PIN2 and PIN3. The pin PIN1 is coupled to the control chip CCP. The pin PIN2 is coupled to a reference low voltage (for example, ground). The pin PIN3 is floated.

[0017] In the embodiment, the CMOS data clearing circuit 100 includes a connection port 110 and a controller 120. The CMOS data clearing circuit 100 can be detachably connected to the pin header HD through the connection port 110. The controller 120 is operated to generate the pulse signal RTC and the operation signal SO. The connection port 110 has an input pin 111 and an output pin 112. The output pin 112 is coupled to the pin PIN1 of the pin header HD. The connection port 110 conducts the input pin 111 to the output pin 112 in response to the operation signal SO, so as to transmit the pulse signal RTC to the pin PIN1 via the output pin 112. Therefore, the control chip CCP can receive the pulse signal RTC via the pin PIN1, and clear the CMOS data DT of the main board MB based on the voltage variation of the pulse signal RTC.

[0018] For example, when receiving the operation signal SO, the input pin 111 is shorted to the output pin 112. On the other hand, when the operation signal SO is not received, the input pin 111 and the output pin 112 are electrically isolated from each other.

[0019] In an embodiment, the CMOS data clearing circuit 100 can connect or cut-off the electrical connection between the input pin 111 and the output pin 112 by a switching element (not shown). For example, one terminal of the switching element is electrically connected to the input pin 111, and another terminal of the switching element is electrically connected to the output pin 112. When receiving the operation signal SO, the switching element is turned on in response to the operation signal SO. Therefore, the input pin 111 is electrically connected to the output pin 112. When the operation signal SO is not received, the switching element is turned off. The input pin 111 and the output pin 112 are electrically isolated from each other.

[0020] For example, the CMOS data DT is data stored in a random-access memory (RAM) provided on the main board MB.

[0021] In the embodiment, when receiving the operation signal SO, the connection port 110 conducts the input pin 111 to the output pin 112. The input pin 111 is electrically connected to the pin PIN1 of the pin header HD via the output pin 112. When the pulse signal RTC on the input pin 111 transitions from a high voltage value to a low voltage value, the low voltage value of the pulse signal RTC is equal to the voltage value of the reference low voltage. In other words, a voltage value of the output pin 112 is substantially equal to the voltage value of the pin PIN2. It can be seen that the connection port 110 simulates the operation state in which the pin PIN1 is connected to the pin PIN2. Therefore, the control chip CCP clears the CMOS data DT.

[0022] On the other hand, when the operation signal SO is not received, the input pin 111 and the output pin 112 are electrically isolated from each other. The pin PIN1 is not electrically connected to the input pin 111. It can be seen that the connection port 110 simulates the operation state in which the pin PIN1 is connected to the pin PIN3. Therefore, the control chip CCP does not clear the CMOS data DT.

[0023] It is worth mentioning here that the controller 120 generates the pulse signal RTC to the input pin 111. The control chip CCP automatically clears the CMOS data DT located in the main board MB based on the voltage variation of the pulse signal RTC. A user does not need to manually use a jumper to operate pin header HD. In this way, the labor cost and time cost required for clearing CMOS data can be saved.

[0024] In the embodiment, the pin header HD may be disposed on an edge EG of the main board MB. The output pin 112 can be connected to the header pin PIN1 at the edge EG. Therefore, when an abnormality occurs in the electronic device ED, the CMOS data clearing circuit 100 is easily connected to the pin header HD. Thus, convenience of use of the CMOS data clearing circuit 100 could be improved.

[0025] In the embodiment, the CMOS data clearing circuit 100 further includes an activation component 130. The activation component 130 is coupled to the connection port 110 and the controller 120.

[0026] For example, the activation component 130 may be a button, a key or a jumper. When the abnormality occurs in the electronic device ED, the user connects the output pin 112 to the pin PIN1 and operates the activation component 130. When the activation component 130 is operated, the controller 120 provides the operation signal SO. In other words, the controller 120 generates the operation signal SO and the pulse signal RTC in response to the user's operation on the activation element 130. Therefore, the input pin 111 and the output pin 112 are short-circuited and the pulse signal RTC is provided to the pin PIN1. The pulse signal RTC simulates the operation state of the pin PIN1 being connected to the pin PIN2. Thus, the control chip CCP clears the CMOS data DT.

[0027] Please refer to FIG. 2, FIG. 2 illustrates a schematic circuit diagram of a CMOS data clearing circuit according to an embodiment of the disclosure. In the embodiment, the CMOS data clearing circuit 200 includes a connection port 110 and a controller 220. The implementation details of the connection port 110 have been clearly explained in the embodiment of FIG. 1, so it will not be repeated here. The controller 220 generates a control signal VA. For example, the controller 220 generates the control signal VA in response to the user's operation on the activation element 130. The controller 220 delays the control signal VA to generate a delayed signal VB, and generates the pulse signal RTC according to the control signal VA and the delayed signal VB.

[0028] In the embodiment, the controller 220 includes switches SW1 and SW2, resistors R1 and R2, and a delay circuit DLC. The switch SW1 has a first terminal, a second terminal and a control terminal. The first terminal of the switch SW1 is coupled to the input pin 111 of the connection port 110. The second terminal of the switch SW1 is coupled to the reference low voltage. Resistor R1 has a first terminal and a second terminal. The first terminal of the resistor R1 receives the control signal VA. The second terminal of the resistor R1 is coupled to the control terminal of the switch SW1. The resistor R2 is coupled between the control terminal of the switch SW1 and the reference low voltage. The delay circuit DLC receives the control signal VA and delays the timing of the control signal VA to generate the delayed signal VB. The switch SW2 has a first terminal, a second terminal and a control terminal. The first terminal of the switch SW2 is coupled to the control terminal of the switch SW1. The second terminal of the switch SW2 is coupled to the reference low voltage. The control terminal of the switch SW2 is coupled to the delay circuit DLC. The control terminal of the switch SW2 receives the delayed signal VB.

[0029] In the embodiment, the switches SW1 and SW2 may be implemented by transistors or transmission gates. Taking the embodiment as an example, the switches SW1 and SW2 are respectively implemented by any form of N-type field-effect transistor (FET), but the disclosure is not limited thereto.

[0030] Please refer to FIG. 1, FIG. 2 and FIG. 3, FIG. 3 illustrates a timing diagram according to an embodiment of the disclosure. In the embodiment, the control signal VA may be a DC voltage signal (but the disclosure is not limited thereto). When the controller 220 generates the control signal VA, during a first period PT1, the switch SW1 is turned on in response to the control signal VA. Furthermore, the rising time of the rising edge of the delayed signal VB is delayed, and the voltage value of the delayed signal VB is lower than or equal to a threshold voltage value VT of the switch SW2. Therefore, the switch SW2 is turned off in response to the delay signal VB. The resistors R1 and R2 divide the control signal VA to generate the control signal VC. The rising time of the rising edge of the control signal VC is not delayed. Therefore, during the first period PT1, the switch SW1 is turned on in response to the high voltage value of the control signal VA. A voltage value of the pulse signal RTC is pulled down to a low voltage value.

[0031] In addition, during the first period PT1, the input pin 111 is electrically connected to the output pin 112. Therefore, the voltage value of the output pin 112 is substantially equal to the voltage value of the pin PIN2. It can be seen that the connection port 110 simulates the operation state in which the pin PIN1 is connected to the pin PIN2. Therefore, the control chip CCP clears the CMOS data DT.

[0032] During a second period PT2 later than the first period PT1, the voltage value of the delay signal VB is higher than the threshold voltage value VT of the switch SW2. Therefore, the switch SW2 is turned on in response to the delay signal VB, thereby turning off the switch SW1. Furthermore, during the second period PT2, the switch SW2 is turned on to pull down the voltage value of the control signal VC to a low voltage value. Therefore, the switch SW1 is turned off. So that the input pin 111 is floated during the second period PT2. It can be seen that the connection port 110 simulates the operation state in which the pin header pin PIN1 is connected to the pin header pin PIN3. Therefore, the control chip CCP stops or finishes clearing the CMOS data DT.

[0033] In the embodiment, the time length of the first period PT1 may be determined by the delay circuit DLC.

[0034] FIG. 4 illustrates a schematic circuit diagram of a CMOS data clearing circuit according to an embodiment of the disclosure. Please refer to FIG. 4, in the embodiment, the CMOS data clearing circuit 300 includes a connection port 110 and a controller 320. The controller 320 includes switches SW1, SW2, resistors R1, R2, and a delay circuit DLC. The implementation of the switches SW1 and SW2 and the resistors R1 and R2 is the same as the implementation of the switches SW1 and SW2 and the resistors R1 and R2 in FIG. 2, so it will not be repeated here. In the embodiment, the delay circuit DLC includes a delay resistor R3 and a delay capacitor C1. The first terminal of the delay resistor R3 receives the control signal VA. The second terminal of the delay resistor R3 is coupled to the control terminal of the switch SW2. The delay capacitor C1 is coupled between the control terminal of the switch SW2 and the reference low voltage. Therefore, the delay circuit DLC can determine the rise time of the rising edge of the delay signal VB based on a resistance value of the delay resistor R3 and a capacitance value of the delay capacitor C1. Therefore, the delay circuit DLC can determine the maintenance time length of the low voltage value of the pulse signal RTC based on the resistance value of the delay resistor R3 and the capacitance value of the delay capacitor C1.

[0035] In view of the foregoing, the CMOS data clearing circuit generates a pulse signal on the input pin. The control chip automatically clears the CMOS data of the main board based on the voltage change of the pulse signal. The user does not need to manually use a jumper to operate the pin header. In this way, the labor cost and time cost required for clearing CMOS data can be saved. In additional, the pin header can be placed on the edge of the main board. Therefore, when an abnormality occurs in the electronic device, the CMOS data clearing circuit is easily connected to the pin header. Thereby improving the ease of use of the CMOS data clearing circuit.

[0036] Although the disclosure has been described with reference to the above embodiments, they are not intended to limit the disclosure. It will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit and the scope of the disclosure. Accordingly, the scope of the disclosure will be defined by the attached claims and their equivalents and not by the above detailed descriptions.