Smart surveillance service in pre-boot for quick remediations

[0001] The present disclosure relates in general to information handling systems, and more particularly to providing diagnostics (also referred to as surveillance) of a pre-boot environment such as a Unified Extensible Firmware Interface (UEFI) Basic Input/Output System (BIOS).

[0002] As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.

[0003] Portions of this disclosure may be used in conjunction with techniques described in U.S. patent application Ser. No. 18/473,097, entitled “SECURE HANDSHAKE FOR HOST TO NON-HOST EXECUTION,” which is being filed concurrently herewith and is incorporated by reference herein in its entirety.

[0004] Current implementations of pre-boot surveillance in information handling systems are somewhat lacking. For example, it would be advantageous if the pre-boot firmware environment could utilize all processors present in a system to perform live monitoring of the system and continuously learn from its behavior. For example, such a surveillance system might be able to capture information about unexpected slowdowns in the firmware execution, errors, etc., and report them to a monitoring service.

[0005] The Multiprocessor (MP) Protocol is a part of the UEFI Specification. It provides a standard way for the operating system (OS) to discover and manage multiple processors or cores in a system. An information handling system may use the MP Protocol to determine the number and type of processors in the system and configure them for use in the PEI pre-boot phase. The protocol also provides services for controlling the execution of code on specific processors or cores, including starting and stopping them and setting their priority in the DXE pre-boot phase.

[0006] In current systems, however, various limitations are present regarding surveillance of the pre-boot environment.

• • [0007] 1. There is no surveillance system which will monitor the boot path and immediately provide remediation for failures occurring in the pre-boot environment.
  • [0008] 2. There is no connectivity available in the early pre-boot phases, because the Bluetooth/Wi-Fi/Network stack all are initialized in the late DXE phase, and thus there are limitations for any telemetry in the PEI and early DXE phases.
  • [0009] 3. In current systems, it may be necessary to wait for the OS to boot to send logged telemetry events, which limits complete auto healing capabilities during boot and implemented via the pre-boot environment.
  • [0010] 4. Currently, there is no mechanism to perform BIOS diagnostics in parallel during the boot process execution, and so diagnostics take a longer time than would be ideal.
  • [0011] 5. In modern systems, the boot process executes using one CPU, leaving any other CPUs or cores idle, instead of using them for learning the boot paths and remediation of platforms in case of any failure in booting of the system.

[0012] Embodiments thus improve on existing techniques in the context of pre-boot surveillance.

[0013] It is to be noted that various terms discussed herein are described in the UEFI Specification Version 2.10, released August 2022 (hereinafter, UEFI Specification), which is hereby incorporated by reference in its entirety. One of ordinary skill in the art with the benefit of this disclosure will understand its applicability to other specifications (e.g., prior or successor versions of the UEFI Specification). Further, some embodiments may be applicable to different technologies other than UEFI.

[0014] It should be noted that the discussion of a technique in the Background section of this disclosure does not constitute an admission of prior-art status. No such admissions are made herein, unless clearly and unambiguously identified as such.

[0015] In accordance with the teachings of the present disclosure, the disadvantages and problems associated with pre-boot surveillance in information handling systems may be reduced or eliminated.

[0016] In accordance with embodiments of the present disclosure, an information handling system may include a host central processing unit (CPU); and a non-CPU processing unit. The information handling system may be configured to, during execution of a pre-boot environment: perform boot tasks on the host CPU; and perform diagnostic tasks on the non-CPU processing unit.

[0017] In accordance with these and other embodiments of the present disclosure, a method may include an information handling system that includes a host central processing unit (CPU) and a non-CPU processing unit executing a pre-boot environment; during execution of the pre-boot environment, the information handling system performing boot tasks on the host CPU; and during execution of the pre-boot environment, the information handling system performing diagnostic tasks on the non-CPU processing unit.

[0018] In accordance with these and other embodiments of the present disclosure, an article of manufacture may include a non-transitory, computer-readable medium having computer-executable code thereon that is executable by at least one processor of an information handling system for: executing a pre-boot environment; during execution of the pre-boot environment, performing boot on tasks a host central processing unit (CPU) of the information handling system; and during execution of the pre-boot environment, performing diagnostic tasks on a non-CPU processing unit of the information handling system.

[0019] Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

[0020] It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.

[0026] Preferred embodiments and their advantages are best understood by reference to FIGS. 1 through 4, wherein like numbers are used to indicate like and corresponding parts.

[0027] For the purposes of this disclosure, the term “information handling system” may include any instrumentality instrumentalities operable to compute, or aggregate of classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system may be a personal computer, a personal digital assistant (PDA), a consumer electronic device, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include memory, one or more processing resources such as a central processing unit (“CPU”) or hardware or software control logic. Additional components of the information handling system may include one or more storage devices, one or more communications ports for communicating with external devices as well as various input/output (“I/O”) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communication between the various hardware components.

[0028] For purposes of this disclosure, when two or more elements are referred to as “coupled” to one another, such term indicates that such two more elements are in electronic communication or mechanical communication, as applicable, whether connected directly or indirectly, with or without intervening elements.

[0029] When two or more elements are referred to as “coupleable” to one another, such term indicates that they are capable of being coupled together.

[0030] For the purposes of this disclosure, the term “computer-readable medium” (e.g., transitory or non-transitory computer-readable medium) may include any instrumentality or aggregation of instrumentalities that may retain data and/or instructions for a period of time. Computer-readable media may include, without limitation, storage media such as a direct access storage device (e.g., a hard disk drive or floppy disk), a sequential access storage device (e.g., a tape disk drive), compact disk, CD-ROM, DVD, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and/or flash memory; communications media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and/or optical carriers; and/or any combination of the foregoing.

[0031] For the purposes of this disclosure, the term “information handling resource” may broadly refer to any component system, device, or apparatus of an information handling system, including without limitation processors, service processors, basic input/output systems, buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, and/or any other components and/or elements of an information handling system.

[0032] FIG. 1 illustrates a block diagram of an example information handling system 102, in accordance with embodiments of the present disclosure. In some embodiments, information handling system 102 may comprise a server chassis configured to house a plurality of servers or “blades.” In other embodiments, information handling system 102 may comprise a personal computer (e.g., a desktop computer, laptop computer, mobile computer, and/or notebook computer). In yet other embodiments, information handling system 102 may comprise a storage enclosure configured to house a plurality of physical disk drives and/or other computer-readable media for storing data (which may generally be referred to as “physical storage resources”). As shown in FIG. 1, information handling system 102 may comprise a processor 103, a memory 104 communicatively coupled to processor 103, a BIOS 105 (e.g., a UEFI BIOS) communicatively coupled to processor 103, a network interface 108 communicatively coupled to processor 103. In addition to the elements explicitly shown and described, information handling system 102 may include one or more other information handling resources.

[0033] Processor 103 may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation, a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, processor 103 may interpret and/or execute program instructions and/or process data stored in memory 104 and/or another component of information handling system 102.

[0034] Memory 104 may be communicatively coupled to processor 103 and may include any system, device, or apparatus configured to retain program instructions and/or data for a period of time (e.g., computer-readable media). Memory 104 may include RAM, EEPROM, a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to information handling system 102 is turned off.

[0035] As shown in FIG. 1, memory 104 may have stored thereon an operating system 106. Operating system 106 may comprise any program of executable instructions (or aggregation of programs of executable instructions) configured to manage and/or control the allocation and usage of hardware resources such as memory, processor time, disk space, and input and output devices, and provide an interface between such hardware resources and application programs hosted by operating system 106. In addition, operating system 106 may include all or a portion of a network stack for network communication via a network interface (e.g., network interface 108 for communication over a data network). Although operating system 106 is shown in FIG. 1 as stored in memory 104, in some embodiments operating system 106 may be stored in storage media accessible to processor 103, and active portions of operating system 106 may be transferred from such storage media to memory 104 for execution by processor 103.

[0036] Network interface 108 may comprise one or more suitable systems, apparatuses, or devices operable to serve as an interface between information handling system 102 and one or more other information handling systems via an in-band network. Network interface 108 may enable information handling system 102 to communicate using any suitable transmission protocol and/or standard. In these and other embodiments, network interface 108 may comprise a network interface card, or “NIC.” In these and other embodiments, network interface 108 may be enabled as a local area network (LAN)-on-motherboard (LOM) card.

[0037] In some embodiments, information handling system 102 may include more than one processor 103. For example, one such processor 103 may be a CPU, and other processors 103 may include various other processing cores such as application processing units (APUs) and graphics processing units (GPUS). Embodiments of this disclosure may provide a method to dynamically initialize such processors during the early phases of a pre-boot environment to enable their use in parallel execution to reduce boot time. Further, a smart surveillance method may be loaded in the early PEI phase and may start continuous monitoring services for remediation readiness without disturbing current boot performance. A method is presented to create a connected pre-boot environment utilizing the Bluetooth/Wi-Fi stack in the late PEI phase for live telemetry. A method is presented to dynamically provide a parallel processing platform for faster diagnostics and quick healing.

[0038] Thus embodiments allow faster boot with smart surveillance without disturbing the existing boot path performance. As part of the smart cloud ecosystem, the early PEI phase APU and GPU initialization method to bring up the Bluetooth (e.g., BLE) and/or Wi-Fi stack enables cloud connectivity for telemetry and learning. Surveillance as a service in the pre-boot environment may perform cloud connections for continuous synchronization and faster remediations of any problems encountered by information handling system 102. A symmetric multiprocessing platform creates concurrent diagnostics and quick healing.

[0039] According to one embodiment, the PEI firmware may detect the CPU and identifies its characteristics, such as the number of cores and their specific features, and configure the CPU's control registers, cache parameters, and memory management units (MMUs) to ensure efficient memory access.

[0040] After the APU initialization, the PEI firmware does GPU initialization with memory interface, allocating resources and setting up memory controllers.

[0041] FIG. 2 provides an illustration of one embodiment.

[0042] During this PEI boot stage, MP services may identify the number of processors or processor cores present in the system. It collects information about each processor and provides data about the number of cores, their types, and local APIC (Advanced Programmable Interrupt Controller) IDs and saves this information in a data structure. This processor-specific data may assign the APIC ID to the BIOS process which will be stored in a hand-off buffer (HOB) and passed to the MP services in the DXE phase.

[0043] In the DXE phase, the MP service protocol assigns a BIOS process to the respective APIC ID of the processors identified in the HOB. The MP services functions may be called, and the process will be scheduled for execution on the specified processors or cores. As shown, storage may be assigned to CPU1, networking may be assigned to CPU2, boot path may be assigned to APU1, graphics may be assigned to GPU1, and processing of the visual forms representation (VFR) may be assigned to CPU3.

[0044] Thus, embodiments may ensure that all the CPUs and/or APUs and/or GPUs are utilized efficiently, and multiple drivers are handled in parallel by all CPUs and APUs, achieving a true multi-processing system in the pre-boot environment.

[0045] FIG. 3 provides an example of different tasks that may be carried out by a particular CPU core and a particular APU core during the various phases of boot. In the SEC phase, CPU1 may carry out the Trusted Platform Module (TPM) verification.

[0046] After the initialization of APU2, a surveillance service may run on APU2 creating an event logging queue, which will be utilized by the different BIOS drivers to capture relevant events and enqueue them in the event queue. These events can include hardware initialization progress, firmware status, error conditions, security-related events, or specific debug information. This service may continue logging events up until the ExitBootServices( ) event.

[0047] Monitoring data collected by the service running on APU2 may be compared to identify differences in event patterns and provide quick remediations to recover from failures and automatically address any problems encountered by the system. This surveillance process may run concurrently on APU2 without disturbing the existing boot path, which may be handled by CPU1.

[0048] FIG. 4 provides an illustration of tasks that may be carried out by a particular CPU core and a particular APU core during the PEI boot phase, according to another embodiment.

[0049] In some embodiments, the CPU may be used for executing the normal boot path, and the available APUs can be assigned for the task to initialize the Bluetooth/Wi-Fi stack in the late PEI phase. In case of a boot failure (e.g., no POST) condition, the APU may start creating the failure logs, collecting a dump of the NVRAM variables, etc. The crash dump logs may be collected and uploaded to a remote provisioned and secure Bluetooth/Wi-Fi device. Based on the event logs, the system can receive input from the secure remote device for quickly healing to recover the system. For example, the remote device may provide a service OS (SOS) to be executed on the local system to allow for remediation of any problems discovered.

[0050] In a symmetric processor environment, where multiple processors (or CPU cores) are present, running diagnostics during the pre-boot phase involves leveraging the capabilities of each processor to perform tests and gather diagnostic information. Using the MP service, the APIC ID of the available processors may be obtained. The necessary diagnostic code or routines that will be executed on each processor may then be loaded and initialized.

[0051] Tests may be distributed among the available processors to ensure that the workload is evenly distributed to maximize parallel execution. Using the function interface provided by the MP service, all available processors may start and complete their assigned work items in a synchronized manner.

[0052] Further, the results from each processor may be consolidated into a unified diagnostic report or summary. This report can be used for further analysis to take immediate action and provide faster root-cause analysis information. Thus, by leveraging the symmetric processor environment to distribute the diagnostic workload across multiple processors, parallel execution of f tests is enabled, and overall diagnostic efficiency and troubleshooting capabilities are enhanced.

[0053] Although various possible advantages with respect to embodiments of this disclosure have been described, one of ordinary skill in the art with the benefit of this disclosure will understand that in any particular embodiment, not all of such advantages may be applicable. In any particular embodiment, some, all, or even none of the listed advantages may apply.

[0054] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.

[0055] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale. However, in some embodiments, articles depicted in the drawings may be to scale.

[0056] Further, reciting in the appended claims that a structure is “configured to” or “operable to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, none of the claims in this application as filed are intended to be interpreted as having means-plus-function elements. Should Applicant wish to invoke § 112(f) during prosecution, Applicant will recite claim elements using the “means for [performing a function]” construct.

[0057] All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.