Image sensor, image processing system including the same, and operating method of the same

[0001] Korean Patent Application No. 10-2020-0024777, filed on Feb. 28, 2020, in the Korean Intellectual Property Office, and entitled: “Image Sensor, Image Processing System Including the Same, and Method of Operating the Same,” is incorporated by reference herein in its entirety.

[0002] Embodiments relate to an image sensor, an image processing system including the image sensor, and a method of operating the image sensor.

[0003] A complementary Metal Oxide Semiconductor (CMOS) image sensor is an image pickup device manufactured using a CMOS process, and has advantages of low manufacturing cost, low power consumption, and high integration compared to, e.g., a charge-coupled device (CCD) image sensor. Main performance indicators for the CMOS image sensor include dynamic range, noise, frame rate, sensitivity, color gamut, power consumption, and sensor size. Depending on specific application fields, specific indicators may be emphasized. In a field requiring high reliability and stability, a CMOS image sensor may provide high dynamic range and low noise performance.

[0004] Embodiments are directed to an image sensor, including a dual conversion gain (DCG) pixel configured to output a high conversion gain signal according to a high conversion gain and output a low conversion gain signal according to a low conversion gain, by adjusting a conversion gain; a scaler configured to scale a voltage level of the high conversion gain signal; a ramp generator configured to generate a first ramp signal and a second ramp signal, a slope of the second ramp signal being different from a slope of the first ramp signal; a comparator configured to compare the scaled high conversion gain signal and the first ramp signal to output a first comparison result, and compare the low conversion gain signal and the second ramp signal to output a second comparison result; and a counter configured to output a first counting result value based on the first comparison result and output a second counting result value based on the second comparison result.

[0005] Embodiments are also directed to an image processing system, including a dual conversion gain (DCG) pixel array including a plurality of DCG pixels, each DCG pixel configured to output a high conversion gain signal according to a high conversion gain and output a low conversion gain signal according to a low conversion gain, by adjusting a conversion gain; a ramp generator configured to generate a first ramp signal and a second ramp signal; a correlated double sampler configured to scale a voltage level of the high conversion gain signal, compare the scaled high conversion gain signal and the first ramp signal to output a first comparison result, and compare the low conversion gain signal and the second ramp signal to output a second comparison result; and a counter configured to output a first counting result value based on the first comparison result and output a second counting result value based on the second comparison result.

[0006] Embodiments are also directed to a method of operating an image sensor, the method including outputting a high conversion gain signal according to a high conversion gain and outputting a low conversion gain signal according to a low conversion gain, by adjusting a conversion gain; scaling a voltage level of the high conversion gain signal; outputting a first comparison result by comparing the scaled high conversion gain signal and a first ramp signal to output a first counting result value based on the first comparison result; and outputting a second comparison result by comparing the low conversion gain signal and a second ramp signal to output a second counting result value based on the second comparison result.

[0022] FIG. 1 is a block diagram illustrating an image sensor according to an example embodiment.

[0023] Referring to FIG. 1, an image sensor 10 according to the present example embodiment includes a dual conversion gain (DCG) pixel array 100, a correlated double sampling (CDS) block 200, a counter block 300, a ramp generator 400, a row driver 500, a control unit 600, and an image processing unit 700.

[0024] The DCG pixel array 100 may include a plurality of DCG pixels. The plurality of DCG pixels may be arranged in a matrix form. Each of the plurality of DCG pixels may be connected to one of a plurality of rows and one of a plurality of columns. The DCG pixel array 100 may detect an incident light according to a shutter operation, perform a photoelectric conversion, and generate and output a plurality of analog pixel signals based on photo-charges generated by the photoelectric conversion. A conversion gain may be adjusted in a process of generating the plurality of analog pixel signals. In an example embodiment, in the process of generating the plurality of analog pixel signals, the DCG pixel array 100 may generate a high conversion gain signal according to a high conversion gain and generate a low conversion gain signal according to a low conversion gain. The conversion gain may be adjusted by driving a dual gain transistor included in the DCG pixel array 100, as described in further detail below.

[0025] The CDS block 200 may include a plurality of CDS circuits. The plurality of CDS circuits may be connected to the plurality of columns of the DCG pixel array 100 and perform a CDS operation on the plurality of analog pixel signals output from the DCG pixel array 100. One of the plurality of CDS circuits may be connected to one column of the DCG pixel array 100 to perform the CDS operation on an analog pixel signal output from the one column of the plurality of columns.

[0026] The counter block 300 may include a plurality of counters. The plurality of counters may be connected to the plurality of columns of the DCG pixel array 100 through the plurality of CDS circuits. The plurality of counters may count the plurality of analog pixel signals, i.e., analog pixel signals which CDS operation is performed on, output from the DCG pixel array 100 in parallel, i.e., simultaneously, to generate counting results, and convert them into a plurality of digital signals CDAT. In an example embodiment, one of the plurality of counters may be connected to one of the plurality of columns through one of the plurality of CDS circuits, may count one of the analog pixel signals to generate a counting result, and may convert the counting result into one of the plurality of digital signal CDAT. Operations of the CDS block 200 and the counter block 300 described above may be performed in units of rows of the DCG pixel array 100.

[0027] The ramp generator 400 may include current sources, resistors, and capacitors. The current sources may generate currents, and the resistors and the capacitors may generate a ramp signal VRAMP falling or rising at a predetermined slope using the respective currents.

[0028] The row driver 500 may be connected to a plurality of rows of the DCG pixel array 100 and may drive the plurality of DCG pixels connected to the rows in units of rows.

[0029] The control unit 600 may generate control signals CTR1, CTR2, CTR3, and CTR4. The control unit 600 may control overall operations of components 100, 200, 300, 400, 500, and 700 included in the image sensor 10 using the control signals CTR1, CTR2, CTR3, and CTR4. The control unit 600 may control an operation timing of the components 100, 200, 300, 400, 500, and 700 using the control signals CTR1, CTR2, CTR3, and CTR4. In an example embodiment, the control unit 600 may control the ramp generator 400 to adjust the ramp signal VRAMP, and may control the CDS block 200 or the counter block 300 to adjust a voltage level of the analog pixel signals output from the DCG pixel array 100.

[0030] The image processing unit 700 may receive the plurality of digital signals output from the counter block 300, and may generate image data IDAT by applying various digital imaging algorithms to the plurality of digitals and performing image synthesis, and transmit the image data IDAT to an interface. Although not illustrated in FIG. 1, the image sensor 10 may further include buffers to transmit a plurality of digital signals output from the counter block 300 to the image processing unit 700, and may further include column drivers to drive columns included in the DCG pixel array 100.

[0031] FIG. 2 is a circuit diagram illustrating a structure of Dual Conversion Gain (DCG) pixel included in a DCG pixel array illustrated in FIG. 1. FIG. 3 is a block diagram illustrating a scaler, a comparator, and a counter in a Correlated Double Sampling (CDS) block or a counter block illustrated in FIG. 1. FIGS. 4 and 5 are timing diagrams illustrating operations of the image sensor of FIG. 1 operating at an ADC timing of Reset-Sig-Sig-Reset (RSSR).

[0032] In FIG. 2, one of a plurality of DCG pixels 110 included in a DCG pixel array 100 is illustrated in FIG. 1. As described above, since the plurality of DCG pixels 110 are arranged in a matrix form and each DCG pixel may be driven in units of rows, descriptions of a structure and an operation of one DCG pixel 110 may be applied to the other pixels connected to the same row.

[0033] Referring to FIG. 1, the DCG pixel 110 according to the present example embodiment includes a photoelectric converter 105, a transfer transistor 107, a reset transistor 115, a dual gain transistor 120, a drive transistor 125, and a selection transistor 130.

[0034] The photoelectric converter 105 may be connected between a ground node and the transfer transistor 107. The transfer transistor 107 may be connected between the photoelectric converter 105 and a floating diffusion node FD1. The reset transistor 115 may be connected between a power supply voltage VDD and a second floating diffusion node FD2. The dual gain transistor 120 may be connected between the first floating diffusion node FD1 and the second floating diffusion node FD2. The drive transistor 125 may be connected between the power supply voltage VDD and the selection transistor 130. The selection transistor 130 may be connected between the drive transistor 125 and an output terminal of the DCG pixel 110.

[0035] With the above-described configuration, the DCG pixel 110 may detect an incident light according to a shutter operation, perform a photoelectric conversion, output an analog pixel signal based on photo-charges generated by the photoelectric conversion, and adjust a conversion gain in a process of generating the analog pixel signal.

[0036] In an example embodiment, the photoelectric conversion is performed by the photoelectric converter 105, and the output of the analog pixel signal may be performed by a plurality of transistors 107, 115, 120, 125, and 130. In an example embodiment, the plurality of transistors 107, 115, 120, 125, and 130 may be driven by the control unit 600. The control unit 600 may generate a control signal CTRL1 and transmit the control signal CTRL1 to the plurality of transistors 107, 115, 120, 125, and 130.

[0037] In an example embodiment, the transfer transistor 107 may be driven by receiving a transfer signal TX as a gate signal. The reset transistor 115 may be driven by receiving a reset signal RX as a gate signal. The dual gain transistor 120 may be driven by receiving a dual gain signal DRX as a gate signal. The drive transistor 125 may be driven by receiving a voltage of the first floating diffusion node FD1 as a gate signal. The selection transistor 130 may be driven by receiving a selection signal SEL as a gate signal. The control signal CTRL1 may include the transfer signal TX, the reset signal RX, the dual gain signal DRX, and the selection signal SEL.

[0038] Hereinafter, the process of outputting the analog pixel signal by the DCG pixel 110 will be described in detail, referring first to FIG. 4 and then to FIG. 3.

[0039] In FIGS. 4 and 5, a first time period, i.e., 1H time period, is illustrated. The first time period may be a time for driving a plurality of DCG pixels 110 included in the DCG pixel array 100 illustrated in FIG. 1 in a row unit.

[0040] Referring to FIGS. 4 and 5, the first time period may include a plurality of second time periods AZ, HRST, HSIG, LSIG, and LRST. After an auto zero period AZ, the following periods may proceed in sequence: a high conversion gain reset signal period HRST, a high conversion gain image signal period HSIG, an auto zero period AZ, a low conversion gain image signal period LSIG, and a low conversion gain reset signal period LRST. In the plurality of second time periods HRST, HSIG, LSIG, and LRST (i.e., except the auto zero period AZ), a high conversion gain reset signal VHRES, a high conversion gain image signal VHSIG, a low conversion gain image signal VLSIG, and a low conversion gain reset signal VLRES may be output, respectively. The analog signals VHRES, VHSIG, VLSIG, and VLRES may be converted into digital signals in the order in which the analog signals VHRES, VHSIG, VLSIG, and VLRES are output, as described below.

[0041] The high conversion gain is a conversion gain greater than the low conversion gain. The conversion gain is a ratio of the analog pixel signal output from the DCG pixel 110 to the unit photo-charge generated by the photoelectric conversion. The unit of the conversion gain may be [V/e]. The conversion gain may be adjusted by driving the dual gain transistor 120 included in the DCG pixel 110. In an example embodiment, the conversion gain may be adjusted to a low conversion gain by turning on the dual gain transistor 120 by applying the dual gain signal DRX of a logic high level to the gate of the dual gain transistor 120, and the conversion gain may be adjusted to a high conversion gain by turning off the dual gain transistor 120 by applying the dual gain signal DRX of a logic low level to the gate of the dual gain transistor 120. As described above, the dual gain transistor 120 may be connected between the first floating diffusion node FD1 and the second floating diffusion node FD2. The conversion gain may be adjusted by changing a combined capacitance C1+C2 (which corresponds to the floating diffusion nodes FD1 and FD2) depending on whether the dual gain transistor 120 is driven.

[0042] Referring to FIG. 4 again, in the auto zero period AZ, an adjustment between a voltage level of a ramp signal VRAMP and a voltage level of an analog pixel signal VPIX may be performed. In the high conversion gain reset signal period HRST, a high conversion gain reset signal VHRES may be output by applying a reset signal RX of a logic high level to a gate of the reset transistor 115 and applying a dual gain signal DRX of a logic low level to a gate of the dual gain transistor 120. A high conversion gain image signal VHSIG may be output in the high conversion gain image signal period HSIG by applying a transfer signal TX of a logic high level to a gate of the transfer transistor 107 before the high conversion gain image signal period HSIG.

[0043] A low conversion gain image signal VLSIG may be output in the low conversion gain image signal period LSIG by applying a reset signal RX of a logic low level to a gate of the reset transistor 115 before the low conversion gain image signal period LSIG, applying a dual gain signal DRX of a logic high level to a gate of the dual gain transistor 120 and applying a transfer signal TX of a logic high level to a gate of the transfer transistor 107. A low conversion gain reset signal VLRES may be output in the low conversion reset signal period LRST by applying a reset signal RX of a logic high level to a gate of the reset transistor 115 before the low conversion reset signal period LRST.

[0044] As described above, the DCG pixel 110 may output the analog pixel signal VPIX. The analog pixel signal VPIX may include a high conversion gain signal and a low conversion gain signal. The high conversion gain signal may include the high conversion gain reset signal VHRES and the high conversion gain image signal VHSIG. The low conversion gain signal may include the low conversion gain reset signal VLRES and the low conversion gain image signal VLSIG.

[0045] Meanwhile, the analog pixel signal VPIX output from the DCG pixel 110 is typically compared with a ramp signal VRAMP and converted into a comparison result, and the comparison result is counted by a counter and converted into a counting result value CDAT. The counting result value CDAT is finally converted into a digital signal IDAT, and the analog pixel signal VPIX is converted into the digital signal IDAT through a series of processes.

[0046] However, it should be noted that the image sensor of FIG. 1 may be driven in the following manner to exhibit a high dynamic range and a low noise performance to provide high reliability and stability.

[0047] Referring now to FIG. 3, a scaler 210 may receive an analog pixel signal VPIX from the DCG pixel 110 and receive analog gain information AG_INFO from the control unit 600. The analog gain information AG_INFO may include information about a scale factor or predetermined multiple (a number), i.e., K times, where K is an integer equal to or greater than 2. In an example embodiment, the analog gain information AG_INFO may be one of 4 times and 16 times, for example.

[0048] The scaler 210 may scale only a voltage level of the high conversion gain signal included in the analog pixel signal VPIX based on the analog gain information AG_INFO. The scaler 210 may transmit a signal SPIX, by scaling only the voltage level of the high conversion gain signal and maintaining the voltage level of the low conversion gain signal, to a comparator 250. The analog pixel signal VPIX may include the high conversion gain signal and the low conversion gain signal, and the signal SPIX output from the scaler 210 may include the scaled high conversion gain signal and the unscaled low conversion gain signal.

[0049] The comparator 250 may receive the scaled high conversion gain signal and the unscaled low conversion gain signal SPIX from the scaler 210, and receive an adjusted ramp signal ADJ_VRAMP including the first ramp signal and the second ramp signal from the ramp generator 400.

[0050] The comparator 250 may generate a first comparison result by comparing the scaled high conversion gain signal and the first ramp signal, and generate a second comparison result by comparing the unscaled low conversion gain signal and the second ramp signal. The comparator 250 may output the first comparison result and the second comparison result as a comparison result TDAT.

[0051] In an example embodiment, the slope of the first ramp signal may be adjusted to output the first comparison result corresponding to the scaled high conversion gain signal. In an example embodiment, the absolute value of the slope of the first ramp signal may be adjusted to be smaller than the absolute value of the slope of the second ramp signal. A specific structure and operation of a ramp generator for generating the first ramp signal and the second ramp signal will be described below with reference to FIGS. 6A and 6B. A relationship between the scaled high conversion gain signal and the first ramp signal will be described below with reference to FIG. 7.

[0052] A counter 350 may receive the first comparison result and the second comparison result from the comparator 250, and receive a counter enable signal CNTEN and a counter clock CNTCLK from the control unit 600. The counter 350 may output a first counting result value (based on the first comparison result) and a second counting result value (based on the second comparison result), as a counting result value CDAT.

[0053] FIG. 6A is a circuit diagram illustrating an example embodiment of a ramp generator included in an image sensor of FIG. 1. FIG. 6B is a circuit diagram illustrating a structure of the ramp generator of FIG. 6A.

[0054] Referring to FIGS. 1 and 6A, the ramp generator 400 may include a variable ramp current source IRAMP and a ramp resistor RRAMP. The ramp generator 400 may further include a resistor R and a capacitor C.

[0055] The variable ramp current source IRAMP and the ramp resistor RRAMP may be connected in series between a power supply voltage VDD and a ground voltage VSS. The resistor R may be connected between a node between the variable ramp current source IRAMP and the ramp resistor RRAMP and an output terminal for outputting the ramp signal VRAMP. The capacitor C may be connected between the output terminal and the ground voltage VSS.

[0056] A variable offset current source IOFS may be connected in parallel with the variable ramp current source IRAMP between the power supply voltage VDD and the ramp resistance RRAMP. As described above with reference to FIG. 3, the ramp generator 400 may be implemented by including a variable ramp current source IRAMP to generate the first ramp signal and the second ramp signal. The ramp generator 400 may be implemented by including the variable offset current source IOFS to decrease or increase the offset of the first ramp signal and the second ramp signal by a constant magnitude.

[0057] Referring to FIGS. 1, 6A and 6B, a ramp generator 400 may include a plurality of ramp current sources IR0, IR1, IR2, . . . , IRN connected in parallel and the ramp resistance RRAMP.

[0058] The plurality of ramp current sources IR0˜IRN connected in parallel may correspond to the variable ramp current source IRAMP in FIG. 6A. In other words, the variable ramp current source IRAMP may include the plurality of ramp current sources IR0˜IRN connected in parallel.

[0059] The ramp current source IR0 may include transistors PR01, PR02, PR03, and PR04 and a capacitor C01, and may operate in response to control signals BPA, CASP, SLb<0>, and SL<0>. The transistors PR01 and PR02 and the capacitor C01 may be connected in series between the power supply voltage VDD and the ground voltage VSS. The transistor PR03 may be connected between a node between the transistor PR02 and the capacitor C01 and the ground voltage VSS. The transistor PR04 and the ramp resistance RRAMP may be connected in series between the node between the transistor PR02 and the capacitor C01 and the ground voltage VSS. The control signals BPA, CASP, SLb<0>, and SL<0> may be applied to gate electrodes of the transistors PR01, PR02, PR03, and PR04, respectively.

[0060] The remaining ramp current sources IR1˜IRN may have substantially the same configuration as the ramp current source IR0. For example, the ramp current source IR1 may include transistors PR11, PR12, PR13, and PR14 and a capacitor C11, and may operate in response to control signals BPA, CASP, SLb<1>, and SL<1>. The ramp current source IR2 may include transistors PR21, PR22, PR23, and PR24 and a capacitor C21, and may operate in response to control signals BPA, CASP, SLb<2>, and SL<2>. The ramp current source IRN may include transistors PRN1, PRN2, PRN3, and PRN4 and a capacitor CN1, and may operate in response to control signals BPA, CASP, SLb<N>, and SL<N>.

[0061] The plurality of ramp current sources IR0˜IRN may be sequentially turned off when the level of the ramp signal VRAMP is to fall with the constant slope, and may be sequentially turned on when the level of the ramp signal VRAMP is to rise with the constant slope.

[0062] For example, all of the plurality of ramp current sources IR0˜IRN may be substantially simultaneously or concurrently turned on at an initial operation time. When the level of the ramp signal VRAMP is to fall with the constant slope, the ramp current source IR0 may be turned off in response to the control signals SL<0> and SLb<0>, the ramp current source IR1 may be additionally turned off in response to the control signals SL<1> and SLb<1>, the ramp current source IR2 may be additionally turned off in response to the control signals SL<2> and SLb<2>, and the ramp current source IRN may be additionally turned off in response to the control signals SL<N> and SLb<N>. The ramp signal VRAMP may have the lowest voltage level when all the ramp current sources IR0˜IRN are turned off.

[0063] After that, when the level of the ramp signal VRAMP is to rise with the constant slope, the ramp current source IR0 may be turned on in response to the control signals SL<0> and SLb<0>, the ramp current source IR1 may be additionally turned on in response to the control signals SL<1> and SLb<1>, the ramp current source IR2 may be additionally turned on in response to the control signals SL<2> and SLb<2>, and the ramp current source IRN may be additionally turned on in response to the control signals SL<N> and SLb<N>. The ramp current sources IR0 to IRN may be turned on or off at the same time to generate a ramp signal of a different slope.

[0064] FIG. 7 is a diagram for describing a relationship between a scaled high conversion gain signal and a first ramp signal.

[0065] Referring to FIG. 7, the unscaled high conversion gain signal included in the analog pixel signal VPIX may be compared with an unadjusted ramp signal VRAMP to generate a comparison result. However, the high conversion gain signal scaled based on the analog gain information AG_INFO may not be compared with the unadjusted ramp signal VRAMP and thus the comparison result may not be generated. Therefore, a slope and an offset of the unadjusted ramp signal VRAMP is adjusted such that the adjusted ramp signal ADJ_VRAMP may be compared with the scaled high conversion gain signal. In an example embodiment, when the high conversion gain signal included in the analog pixel signal VPIX is scaled, in the high conversion gain reset signal period HRST, the ramp signal VRAMP with minimum and maximum values HRST_MIN1 and MRST_MAX1 may be adjusted to the adjusted ramp signal ADJ_VRAMP with minimum and maximum values HRST_MIN2 and HRST_MAX2. In the high conversion gain image signal period HSIG, the ramp signal VRAMP with minimum and maximum values HSIG_MIN1 and HSIG_MAX1 may be adjusted to the adjusted ramp signal ADJ_VRAMP with minimum and maximum values HSIG_MIN2 and HSIG_MAX2. In the auto zero period AZ, the ramp signal VRAMP with an offset OFS1 may be adjusted to the adjusted ramp signal ADJ_VRAMP with an offset OFS2. By the above-described adjustment, the adjusted ramp signal ADJ_VRAMP may be generated from the unadjusted ramp signal VRAMP.

[0066] FIG. 8 is a graph illustrating a change in a signal-to-noise ratio of an analog pixel signal when an analog gain is increased. FIG. 9 is a graph illustrating a change in a dynamic range of an analog pixel signal when an analog gain is increased. FIG. 10 is a graph illustrating a change in a dynamic range of image data generated based on an analog pixel signal when an analog gain is increased.

[0067] In FIGS. 8, 9, and 10, an X-axis represents a magnitude of an incident light incident on the DCG pixel array in Lux units, and a Y-axis represents a signal-to-noise ratio in dB units.

[0068] Referring to FIGS. 1, 2, 3, and 8, when increasing an analog gain, for example, 1→4→16 times, a high conversion gain signal HCG_AG1X→HCG_AG4X→HCG_AG16X and a low conversion gain signal LCG which are included in an analog pixel signal VPIX output from a DCG pixel array 100 may be changed as illustrated.

[0069] Referring to FIG. 9, when increasing the analog gain, for example, 1→4→16 times, a dynamic range of the high conversion gain signal HCG_AG1X→HCG_AG4X→HCG_AG16X and a low conversion gain signal LCG may be changed as illustrated. The dynamic range may be measured from the point where the signal-to-noise ratio is 0 [dB] to the point where the signal-to-noise ratio is saturated in cases, i.e., when the analog gain is 1, 4, and 16 times.

[0070] Referring to FIG. 10, when increasing the analog gain, for example, 1→4→16 times, a dynamic range of the image data generated based on the analog pixel signal VPIX output from the DCG pixel array 100 may be changed as illustrated. The dynamic range may be measured from the point where the signal-to-noise ratio is 0 [dB] to the point where the signal-to-noise ratio is saturated in cases, i.e., when the analog gain is 1, 4, and 16 times.

[0071] When increasing the analog gain, the dynamic range of the low conversion gain signal does not change, but the dynamic range of the high conversion gain signal gradually increases. Therefore, the dynamic range of the image data generated based on the analog conversion signal VPIX including the high conversion gain signal and the low conversion gain signal is also gradually increased.

[0072] FIG. 11 is a diagram for describing a noise generated by an image sensor of FIG. 1.

[0073] Referring to FIGS. 1, 2, and 11, a noise generated by an image sensor 10 of FIG. 1 may be modeled including adders 810-1, 810-3, 810-5, and 810-7 and buffers 830-1 and 830-3.

[0074] A signal S_PD generated by a photoelectric converter 105 is affected by a shot noise N_S, a conversion gain CG, a pixel noise N_PIX, CDS noise N_CDS, an analog gain AG, and a quantization noise N_Q, until the signal S_PD is finally converted to a digital signal IDAT. Meanwhile, an analog-to-digital conversion (ADC) noise generated by the CDS block 200 and the counter block 300 illustrated in FIG. 1 may be determined by Equation 1 below.
N_ADC=√{square root over (N²_CDS+(N_Q|AG)²)}  [Equation 1]

[0075] In Equation 1, N_ADC is the ADC noise, N_CDS is the CDS noise, N_Q is the quantization noise, and AG is the analog gain.

[0076] Therefore, when increasing the analog gain AG, it is possible to reduce the ADC noise N_ADC by reducing the magnitude of the quantization noise N_Q.

[0077] FIG. 12 is a diagram for describing a change in a dynamic range and a magnitude of random noise when an analog gain is increased.

[0078] Referring to FIGS. 1 and 12, when increasing the analog gain AG, for example, 1→4→16 times (AG1X, AG4X, and AG16X, respectively), a dynamic range is increased to a magnitude of 78.7 dB→79.6 dB→81.1 dB. When increasing the analog gain AG, for example, 1→4→16 times, a random noise is decreased to a magnitude of 4.5 e−→1.3 e−→1.0 e−.

[0079] When increasing the analog gain AG, since an absolute value of a SNR dip increases, a digital signal DAT may be generated by applying a digital imaging algorithm by the image processing unit 700.

[0080] FIGS. 13 and 14 are timing diagrams illustrating operations of the image sensor of FIG. 1 operating at an ADC timing of Reset-Reset-Sig-Sig (RRSS).

[0081] The timing diagrams of FIGS. 13 and 14 are only different in an ADC timing in a process of processing an analog pixel signal compared to the timing diagrams of FIGS. 4 and 5, and thus duplicate description will be omitted below.

[0082] Referring to FIGS. 13 and 14, the first time period, i.e., 1H time period, may include a plurality of second time periods AZ, HRST, LRST, LSIG, and HSIG. After an auto zero period AZ, the 1H time period may sequentially include a high conversion gain reset signal period HRST, a low conversion gain reset signal period LRST, a low conversion gain image signal period LSIG, and a high conversion gain image signal period HSIG.

[0083] A high conversion gain reset signal VHRES may be output in the high conversion gain reset signal period HRST by applying a reset signal of a logic high level to a gate of the reset transistor 115 and applying a dual gain signal DRX of a logic low level to a gate of the dual gain transistor 120 before the high conversion gain reset signal period HRST. A low conversion gain reset signal VLRES may be output in the low conversion reset signal period LRST by applying a dual gain signal DRX of a logic high level to a gate of the dual gain transistor 120 before the low conversion reset signal period LRST.

[0084] A low conversion gain image signal VLSIG may be output in the low conversion gain image signal period LSIG by applying a reset signal RX of a logic low level to a gate of the reset transistor 115, applying a dual gain signal DRX of a logic high level to a gate of the dual gain transistor 120, and applying a transfer signal TX of a logic high level to a gate of the transfer transistor 107 before the low conversion gain image signal period LSIG. A high conversion gain image signal VHSIG may be output in the high conversion gain image signal period HSIG by applying a dual gain signal DRX of a logic low level to the dual gain transistor 120 and applying a transfer signal TX of a logic high level to a gate of the transfer transistor 107 before the high conversion gain image signal period HSIG.

[0085] As described above, the DCG pixel 110 may output the analog pixel signal VPIX, and the analog pixel signal VPIX may include a high conversion gain signal and a low conversion gain signal. The high conversion gain signal may include the high conversion gain reset signal VHRES and the high conversion gain image signal VHSIG, and the low conversion gain signal may include the low conversion gain reset signal VLRES and the low conversion gain image signal VLSIG. The descriptions provided above with reference to FIGS. 3, 6A, 6B, and 7 may be similarly applied in a process of processing an analog pixel signal when the image sensor operates at an ADC timing of Reset-Reset-Sig-Sig (RRSS).

[0086] FIG. 15 is a flowchart illustrating a method of operating the image sensor of FIG. 1 according to an example embodiment.

[0087] Referring to FIGS. 1 and 15, in a method of operating the image sensor according to an example embodiment, the image sensor 10 may adjust a conversion gain to output a low conversion gain signal according to a low conversion gain, and output a high conversion gain signal according to a high conversion gain (S1000). The image sensor 10 may scale a voltage level of the high conversion gain signal (S3000). The image sensor 10 may compare the scaled high conversion gain signal and a first ramp signal to output a first comparison result, and output a first counting result based on the first comparison result (S5000). The image sensor 10 may compare the low conversion gain signal and a second ramp signal to output a second comparison result, and output a second counting result based on the second comparison result (S7000).

[0088] FIG. 16 is a block diagram illustrating an electronic system including an image sensor of FIG. 1 according to an example embodiment.

[0089] Referring to FIG. 16, an electronic system 1000 according to an example embodiment may be implemented as a data processing device that uses or supports a mobile industry processor interface (MIPI) interface. The electronic system 1000 may include an application processor 1110, an image sensor 1140, a display device 1150, a radio frequency (RF) chip 1160, a global positioning system (GPS) 1120, a storage 1170, a microphone (MIC) 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190. In addition, the electronic system 1000 may perform communications using an ultra wideband (UWB) 1210, a wireless local area network (WLAN) 1220, a worldwide interoperability for microwave access (WIMAX) 1230, etc.

[0090] The application processor 1110 may be a controller or a processor that controls an operation of the image sensor 1140. The image sensor 1140 may be an image sensor as described above in connection with FIG. 1 according to an example embodiment, and may perform or execute the method of operating the image sensor according to an example embodiment.

[0091] The application processor 1110 may include a display serial interface (DSI) host 1111 that performs a serial communication with a DSI device 1151 of the display device 1150, a camera serial interface (CSI) host 1112 that performs a serial communication with a CSI device 1141 of the image sensor 1140, a physical layer (PHY) 1113 that performs data communications with a physical layer (PHY) 1161 of the RF chip 1160 based on a MIPI DigRF, and a DigRF MASTER 1114 that controls the data communications of the physical layer 1161. A DigRF SLAVE 1162 of the RF chip 1160 may be controlled through the DigRF MASTER 1114.

[0092] In an example embodiment, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). In an example embodiment, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER).

[0093] As described above, an image sensor, an image processing system including the image sensor, and a method of operating the image sensor according to an example embodiment may scale only a voltage level of a high conversion gain signal included in an analog pixel signal output from a DCG image sensor, and may not scale a voltage level of a low conversion gain signal. Through the scaling, a dynamic range of an image photographed in low light may be increased to increase a dynamic range of a finally generated digital signal and reduce a random noise.

[0094] Example embodiments may be applied to various electronic devices and systems including the image sensors. For example, example embodiments may be applied to systems such as a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, etc.

[0095] Example embodiments may provide an image sensor, an image processing system including the image sensor, and a method of operating the image sensor, which may provide high dynamic range and reduce noise.

[0096] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.