DC coupled amplifier having pre-driver and bias control

[0001] The field of the invention relates to amplifiers and in particular to an improved distributed amplifier and improved DC-coupled amplifier.

[0002] Distributed amplifiers, also known as traveling wave amplifiers, are a common amplifier configuration for wide bandwidth applications. FIG. 1 illustrates an example circuit of an exemplary prior art distributed amplifier. The distributed amplifier of FIG. 1 is a single ended configuration. As shown, an input node 104 is configured to receive a data signal to be amplified. The input node 104 connects to an inductor 108A. The opposite terminal of the inductor 108A connects to an inductor 108B and a first amplifier section 112A. The inductors 108 are in a circuit section defined herein as the input line.

[0003] The amplifier section 112A comprises two transistors connected source to drain as shown. The gate terminal of FET 154 connects to the inductors 108A and 108B. A capacitor 162 connects the gate terminal of FET 150 to ground. The drain terminal of the FET 150 connects to inductors 120A, 120B as shown. The opposite terminal of inductor 120A connects to an output termination resistor RD 130, which in turn connects to capacitor 134. Resistor RD 130 may also be referred to a drain resistor that is used for impedance matching and to set the output impedance. The opposite terminal of the capacitor 134 connects to ground. The output termination resistor RD 130 and capacitor 134 establish the output impedance seen from an output node 124. The inductors 120A, 120B are in a circuit section defined as the output line 122.

[0004] The FETs 150, 154 of the amplifiers sections 112 have parasitic capacitance and the inductors 108A, 108B, 120A, 120B arranged in the circuit are selected to cancel or counter the parasitic capacitance associated with the amplifier sections.

[0005] The arrangement of amplifier sections 112A and inductors 108A, 108B, 120A, 120B repeats with one or more additional amplifying sections 112B and inductors 108C, 108N and 120C and 120N where N is any whole number. An output node 124 connects to the inductor 120N. An inductor 170 also connects to the output node 124 and to a supply voltage VD 166. The supply voltage 166 provides a DC supply voltage to the circuit, for biasing.

[0006] Also, part of this distributed amplifier is an input termination resistor 140 and a capacitor 144 which connect in series to ground to provide input impedance matching. A supply voltage VG 150 is supplied at a node between the input termination resistor 140 and capacitor 144.

[0007] Although shown with two amplifier sections 112A, 112B, it is contemplated that any number of sections may be implemented to increase gain or establish other circuit characteristics.

[0008] In operation, the input signal is presented to the input node 104 and in turn to the first amplifier section 112A where it is amplified, and the amplified signal is presented on the output line 122. The process repeats through one or more additional amplifier sections 112 such that an amplified output signal is presented on the output node 124. The input impedance is set, at least in part, by the input termination resistor RG 140 and capacitor 144. The resistor RG 140 may also be referred to a gate resistor used to set input impedance. The output impedance is set, at least in part, by the output termination resistor 130 and capacitor 134. The inductors 108A, 108B, 120A, 120B cancel the parasitic capacitance of the amplifier sections.

[0009] FIG. 2 illustrates an example circuit arrangement for an exemplary prior art distributed amplifier in a differential mode configuration. As compared to FIG. 1, similar elements are labeled with similar reference numbers. However, due to the differential configuration the arrangement is a mirrored collection of components. As is understood in the art, the differential configuration includes two inputs 104-P and 104-N. The inputs 104-P, 104-N receive differential signals that are 180 degrees out of phase with respect to the other. The signal of interest is the difference between the differential signal presented on inputs 104-P, 104-N. The −P and −N designations reflect the two separate but similar arrangements of elements, which are generally mirrored to form the differential configuration. Likewise, the inductors 108 are separated by −P and −N designation with the reference numbers. Due to the generally similar, but duplicate nature of the differential configuration, in the discussion of FIG. 2 only the aspects of FIG. 2 which differs from FIG. 1 are discussed.

[0010] FIG. 2 includes differential amplifier sections 208A, 208B which connect as shown to the input lines 110-P, 110-N and the output lines 122-P, 122-N. Each differential amplifier section 208 includes several components. As in FIG. 1, connected between inductors 108A-P and inductors 108B-P is a gate terminal of FET 224A. The drain terminal of FET 224A connects to the source terminal of a FET 228A. This configuration is mirrored with FETs 224B and 228B as shown such that the gate terminals of FETs 228A, 228B are connected and the source terminals of FETs 224A, 224B are connected. This is referred to as a common source configuration for the FETs 224 and a common gate arrangement for the FETs 228. The drain terminals of FETs 228A and 228B connect to the output lines 122-P and 122-N. A capacitor 232 connects between ground and the gate terminals of FETs 228A, 228B. A current source 220 connects between ground and the source terminals of FETs 224A, 224B. The node between the current source 220 and the source terminals of the FETs 224 becomes a virtual ground when presented with a differential signal. One or more additional differential amplifying sections 208B are similarly configured.

[0011] In operation, a differential signal is presented on the inputs 104-P and 104-N and thus presented to the differential amplifier sections 208A, . . . 208B while the amplified version of the input signals is presented on the outputs 124-P and 124-N. Similar to FIG. 1, the supply voltage VD 166-P provides the bias for the positive side of the amplifier through an inductor 170-P. The voltage VD 166-N and inductor 170-N provide the bias for the negative side of the amplifier. In the differential amplifier configuration, the voltage VD 166-P and 166-N either have equal values or can be connected to the same DC voltage supply. Also, in this embodiment, the inductor 170-P and inductor 170-N are identical but may be different in value in other embodiments. The voltage supply VG 150 is supplied at the node between resistor 140-P and resistor 140-N to provide the gate bias for both sides of the differential amplifier.

[0012] While prior art designs, such as those shown in FIGS. 1 and 2 are suitable for certain applications, improvements would benefit the state of the art. Disclosed herein are improvements to amplifiers and pre-amplifiers as are discussed below.

[0013] To overcome the drawbacks of the prior art and provide additional benefits, disclosed is a DC-coupled amplifier comprising a pre-driver, amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode arranged transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. In other embodiment, a cascode design is not used, thus allowing for any amplifier configuration other than a cascode configuration. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.

[0014] Disclosed herein is an amplifier system comprising a pre-driver configured to receive the one or more input signals, and amplify the one or more input signals to create one or more pre-amplified signals. Also part of this embodiment is an amplifier configured to receive and amplify the one or more pre-amplifier input signals to create one or more amplified signals. The amplifier may include an output driver termination element. A bias control circuit is connected between the pre-driver and the amplifier. The bias control circuit receives at least one bias control circuit input current from the output driver termination element of the amplifier. In this embodiment, the pre-driver, bias control circuit, and the amplifier are formed on a same die.

[0015] In one embodiment, the amplifier system includes a bias control circuit that includes one or more transistors configured as level shifters that control a voltage provided to the pre-driver. The amplifier system die may be a gallium arsenide die. The bias control circuit includes one or more transistors configured to ensure that the pre-driver bias current is insensitive to process variation and bias voltage variation. In one configuration, the pre-driver includes one or more amplifier sections, each of which receive a bias signal from the bias control circuit. Each amplifier section may be formed from two transistors in a common source configuration. In one embodiment, the amplifier is a DC-coupled amplifier having cascode connected transistors. The amplifier system may further comprise a gain control circuit configured with the pre-driver, such that the gain control circuit controls gain of the pre-driver based on a gain control signal.

[0016] Also disclosed herein is a method for amplifying a signal with an amplifier. This method includes providing a pre-driver, an amplifier and a bias control circuit on the same die and providing one or more input signals to the pre-driver. Then, amplify the one or more input signals with the pre-driver to create one or more pre-amplified signals and providing one or more pre-amplified signals to the amplifier, subsequently amplifying the one or more amplifier input signals to create one or more amplified signals and one or more bias control circuit input currents. This method then provides the bias control circuit with the one or more bias control circuit input currents and generates the one or more bias control signals with the bias control circuit.

[0017] The bias control circuit may include one or more transistors configured as level shifters that control a voltage provided to the pre-driver. In one embodiment, the die is a gallium arsenide die. The method may further comprise providing a gain control circuit and receiving a gain control signal at the gain control circuit to thereby control the gain of the pre-driver. In one embodiment, the pre-driver includes one or more amplifier sections, each of which receives a bias signal from the bias control circuit. In one configuration, each amplifier section is formed from two transistors in a common source configuration. The amplifier may comprise an output driver termination element and the bias control circuit receives the one or more bias control circuit input currents from the output driver termination element of the amplifier.

[0018] Also disclosed herein is an amplifier system comprising a pre-driver configured to receive one or more input signals and pre-amplify the one or more input signals to create one or more pre-amplified signals. A gain control system is part of the amplifier system and is configured as part of the pre-driver. The gain control system controls the pre-driver gain in response to a gain control signal provided to the gain control system. An amplifier is configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals. A bias control circuit is connected between the pre-driver and the amplifier. The bias control circuit receiving at least one bias control circuit input current from the amplifier, such that the pre-driver, the gain control circuit, the bias control circuit, and the amplifier are formed on the same die.

[0019] In one configuration, the bias control circuit includes one or more transistors configured as level shifters that control a voltage provided to the pre-driver. The bias control circuit includes one or more transistors configured to ensure that the pre-driver bias current is insensitive to process variation and bias voltage variation. In one embodiment, the pre-driver includes three amplification sections, each of which receives a bias signal from the bias control circuit. Each amplifier section may be formed from two transistors in a common source configuration.

[0031] Distributed amplifiers such as those identified in FIG. 1 and FIG. 2 are commonly fabricated of either Gallium Arsenide, Silicon Germanium, a combination of both, or any other material or process. Silicon Germanium has many performance advantages such as higher gain and bandwidth but Gallium Arsenide inherently provides higher output voltage and lower power dissipation. For applications requiring relatively high output voltage and gain, typical prior art applications have used a Silicon Germanium pre-driver stage and a Gallium Arsenide output driver stage in one package.

[0032] Improvements are possible over the prior art applications. One area for improvement over the prior art is significantly reduced amplifier (driver and pre-driver) size and cost. This system improves the prior art by reducing the size and cost of a distributed amplifier (driver and pre-driver) while maintaining the same or higher gain level, while also maintaining or increasing bandwidth. As compared to the prior art, this is achieved by incorporating a pre-driver and the output driver on a single Gallium Arsenide die with high gain. This provides significantly reduced amplifier size and cost and the integrated driver and pre-driver stages are easier to use.

[0033] FIG. 3A illustrates a block diagram of an improved DC-coupled amplifier 300, such as would be used instead of the distributed amplifier of FIG. 2. The DC-coupled amplifier 300 includes an output driver 302, a bias control section 304 and a pre-driver section 306. The pre-driver section 306 and the output driver section 302 are both differential amplifiers, and thus include differential inputs as shown. The pre-driver section 306 amplifies its differential inputs IN_pre and IN_Pre to output amplified differential inputs IN and IN, under bias control by bias control section 304. The bias control section 304 receives bias currents from the output driver section 302, as will be explained in conjunction with FIG. 4. In one embodiment, the bias control 304, the pre-driver 306, and the output driver 302 are all on the same die. By placing all these elements on the same die, the otherwise required off die AC coupling capacitor between separate dies can be avoided, thus saving space and cost per unit, while maintaining ideal voltage levels and reducing capacitance and inductance. The capacitor required in the prior art may be a 10000 picofarad capacitor. It is preferred to have the voltage on the output of the pre-driver be the same as the voltage on the input to the driver circuit. In the prior art, the output pre-driver voltage may be 3 volts and the input to the driver amplifier may be 1 volt. To connect these two elements, the off-die capacitor was utilized to pass the RF signal while blocking the DC signal.

[0034] FIG. 3B illustrates a block diagram of an alternative embodiment of a DC coupled amplifier 300. As compared to FIG. 3A, similar elements are labeled with identical reference numbers. In this embodiment, the pre-driver 306 includes a gain control module 308 that receives a gain control signal on control input 312. The gain control signal and the gain control module allow the gain of the pre-driver to be adjusted manually or automatically. The gain control module 308 is discussed below in greater detail in connection with FIGS. 6A and 6B. In one embodiment, the pre-driver 306, the bias control circuit 304, and the amplifier (driver 302) are formed on the same die 390.

Pre-Driver Section

[0035] The pre-driver section 306 is shown in FIG. 4. The pre-driver section 306 amplifies differential inputs IN_pre and IN_pre, with IN_pre connected to inductor 278 and the gate of FET Q1 266, and with IN_Pre connected to inductor 280 and the gate of FET Q2 268. FET Q1 266 and FET Q2 268 form the first stage of the amplifier. Any number of stages may be used. In one embodiment, three stages are utilized. The source terminals of FETs 266 and 268 are connected in a common source configuration. A current source 270 connects between ground and the source terminals of FETs 266, 268. The current source 270 could be either a fixed current source or a variable current source. In one embodiment the current source 270 is a resistor. The node VGND associated with the current source 270 is a virtual ground so there is no signal present. Nodes labeled VG_PD are also a virtual ground and thus there is no signal present at these nodes. This designation is found through the embodiments of FIG. 4. The drain of Q1 266 is connected to inductor 262 and to resistor 242, while the drain of transistor Q2 268 is connected to inductor 264 and to resistor 244.

[0036] A second stage of amplification of the pre-driver 306 is provided by transistors Q3 272, Q4 274 and current source 276, which are connected in the same configuration as the first stage of amplification provided by transistors Q1 266, Q2 268 and current source 270. While two stages of amplification are shown, any number of stages of amplification can be included within pre-driver 306 to provide additional gain.

[0037] The voltage supply VG_PD is provided at a voltage supply VG_PD node 290B between resistors RG_PD 282 and 284 to provide the gate bias for transistors Q1-Q4 266, 268, 272, 274. The pre-driver section 306 produces amplified outputs OUT_PD and OUT_PD which are provided to the input terminals 104-P and 104-N of the output driver 302.

Bias Control Section

[0038] The bias control section 304 is shown in detail in FIG. 4. The bias control section 304 receives currents IDP_PD and IDN_PD, which the bias control section 304 uses to generate bias currents for the pre-driver 306.

[0039] IDP_PD is directed to the drain of transistor Q5 230 and to a first terminal of resistor R1 234. The second terminal of resistor R1 234 is connected to the gate of transistor Q5 230, and to a first terminal of resistor R3 240. The second terminal of resistor R3 240 is connected to ground. The source of transistor Q5 is connected to a first terminal of resistor RDP_PD 242, with the second terminal of resistor RDP_PD connected to the drain of transistor Q1 266 and Q3 272 to provide bias control.

[0040] IDN_PD is directed to the drain of transistor Q6 232 and to a first terminal of resistor R2 236. The second terminal of resistor R2 236 is connected to the gate of transistor Q6 232, and to a first terminal of resistor R4 238. The second terminal of resistor R4 238 is connected to ground. The source of transistor Q6 232 is connected to a first terminal of resistor RDN_PD 244, with the second terminal of resistor RDN_PD 244 connected to the drain of transistor Q2 268 and Q4 274 to provide bias control.

[0041] The gate voltages of transistors Q5 230 and Q6 232 are clamped by voltage divider resistors R1-R4 and are used to reduce the DC voltage on the drains of transistors Q1-Q4 in the pre-driver section 306. Additionally, the transistors Q5-Q7 in the bias control section ensure that the pre-driver bias current is insensitive to process variation and bias voltage variation. FETS Q5 230 and Q6 232 may be referred to as a level shifter that is part of the bias circuit 304. Q8 248 is the current mirror. A bias voltage is set up on transistor Q8 248 and by connecting its gate voltage VG_PD to other transistors, it mirrors the same bias condition to other transistors Q1-Q4 with same VG voltage.

[0042] The bias control section also includes transistor Q7 246 having a drain terminal connected to the line receiving bias current IDP_PD and to a first terminal of transistor R5 250. The gate of transistor Q7 246 is connected to a second terminal of resistor R5 250 and to a first terminal of resistor R6 252. A second terminal of resistor R6 252 is connected to ground. A source of transistor Q7 246 is connected to a first terminal of resistor R7 254. A second terminal of resistor R7 254 is connected to a drain of transistor Q8 and to a first terminal of resistor R9 256. The second terminal of resistor R9 256 is connected to the gate of transistor Q8 248 and to a first terminal of resistor R10 258. The second terminal of resistor R10 is an input terminal 290A that sets the voltage VG_PD, which is the same voltage VG_PD applied in the pre-driver section 306 at the node 290B between resistors 282 and 284. The source of transistor Q8 248 is connected to a first terminal of resistor R8 260, with the second terminal of resistor R8 260 connected to ground.

[0043] The transistor Q7 246 and associated resistors R5-R7 function as a level shifter that acts in a manner similar to transistors Q5 and Q6, to reduce the voltage applied to the drains of the transistors in the pre-driver section 306. The transistor Q8 and associated resistors R8-R10 acts as a current mirror to set the gate voltage on the transistors Q1-Q4 in the pre-driver section 306.

[0044] The value of resistors RDP_PD 242 and RDN_PD 244 may be adjusted to control the bias current applied to the pre-driver 306. In a preferred embodiment, the currents IDP_PD and IDN_PD may be set to 15 mA, although other pre-driver currents could be used in other embodiments.

Output Driver Section

[0045] The output driver section 302 is shown in detail in the right side of FIG. 4. The output driver section 302 shares most components with the amplifier of FIG. 2, and the like components that share reference numerals with the amplifier of FIG. 2 will not be further described. In addition to those elements, the output driver section includes resistors RDP 178 and RDN 180 connected to inductors 120A-P and 120A-N, respectively, and capacitors 182, 184 connected between resistors 178, 180 and ground. The resistors RDP 178 and RDN 180 are used to set the current to the pre-driver section 306, where the transistors Q5 230 and Q6 232 receive currents based on the voltage drop across the resistors RDP 178 and RDN 180.

[0046] By adding the pre-driver section 306 and bias control section 304 to the output driver section 302 and producing them on a same gallium arsenide die, the size of the DC-coupled amplifier 300 is reduced, while still producing the needed gain with simplified circuitry, thus avoiding the bandwidth reduction associated with larger FET size. Furthermore, two or more pre-driver sections can be added to achieve significant higher gain while maintaining the same bandwidth and very little increase in chip size. These are improvements over the prior art.

[0047] In operation, the differential input signals are provided to the pre-driver section 306 and amplified. The bias currents applied to the pre-driver section 306 are obtained using output driver termination resistors, and then the bias control uses single common source FETs to allow operation of the pre-driver section 306 at a low drain bias voltage (about 1V in a preferred embodiment). The pre-driver section 306 outputs amplified signals to the output driver section 302, which provides further amplification.

[0048] Many environments of use utilize distributed amplifiers. Distributed amplifiers are commonly found in optical transmitters to transmit data at high data rates between two locations. Numerous other environments of use rely on distributed amplifier and gain control elements. Foundational to optical communication systems is a driver amplifier which amplifies a modulating signal onto an optical modulator or directly onto a laser diode. FIG. 5A illustrates a block diagram of an example environment of use, namely, an optic signal transmitter. This is but one possible environment of use and it is contemplated that other environments of use are possible.

[0049] As shown in FIG. 5A, a data source 504 provides data for eventual transmission over an optic fiber 108. To achieve biasing of a driver, a supply voltage source 512 is provided to deliver power to the system. The supply voltage source 512 may be any source including a hard wire utility supplied power, power supply, battery, or any other source. The supply voltage source 512 provides a supply voltage to the pre-driver and driver amplifier 520. The pre-driver and driver amplifier 520 also receives the data to be transmitted in optic format from the data source 504. The pre-driver and driver amplifier 520 includes one or more amplifiers configured to amplify and modulate the data to a level suitable for driving an optical modulator 524 or laser diode 526. Responsive to the signal from the driver 520, the optical modulator 524 or laser diode 526 generates the optic signal 528, which is presented to the fiber optic cable 108, for transmission to a remote location such as for example another device in a data center or to a remote location in long haul applications. In the example configuration of FIG. 5A, elements inside the dashed line 530 are on one or more integrated circuits.

[0050] FIG. 5B illustrates a block diagram of an example environment of use of an alternative embodiment, namely, an optic signal transmitter. As compared to FIG. 5A, similar elements are labeled with identical reference numbers. In this example embodiment, the pre-driver and driver amplifier 520 includes a gain control input 536 that carries a gain control signal to the pre-driver and driver amplifier. This configuration is shown in greater detail in FIGS. 6A and 6B.

[0051] FIG. 6A illustrates an alternative embodiment of a pre-driver for use in the configuration of FIG. 4. This is but one possible configuration for a pre-driver with gain control. In FIG. 6A, a pre-driver with gain control is shown. The gain control system includes a gain control node 604 configured to receive a gain control signal Vgain. The gain control node 604 connects to a resistor 608. The opposing terminal of the resistor 608 connects to the gate 612 of FET Q9 616 and the gate 620 of FET Q10 624. Also shown are current sources CS1-CS4 which are connected as shown such that each FET Q1, Q2, Q3, and Q4 has its own current source. A fixed or variable resistor may be used as the current source. In one embodiment, CS1 and CS3 may be replaced by a single current source while CS2 and CS4 may be replaced by a single current source.

[0052] The gain control signal presents a voltage to the gates 612, 620 of the FETs 616, 624 to thereby control the resistance across the FETs 616, 624. As such, the FETs 616, 624 perform as variable resistors having a resistance set by the value of the gain control signal. This arrangement maybe referred to as degeneration (or source degeneration) because it reduces the gain of the amplifier. For example, FET Q9 616 appears as a resistor and the resistance is controlled by the value of the voltage applied to the gate 612. When, turned on, with a high voltage at the gate, a low resistance is established which provides the maximum gain. When the FET Q9 is shut off due a low gain control voltage presented at the gate, this increases resistance and provides minimum gain. In addition, the transistors Q9, Q10 provide frequency equalization due to the parasitic capacitance between the drain and source terminals of FETs 612, 620. This equalized gain response is effective to counter the high frequency attenuation nature of the external transmission lines or other aspects of the circuit.

[0053] Also shown in FIG. 6A is an interconnect 630 between node 640A and node 640B. Likewise, an interconnect 634 is between node 644A and 644B. These interconnects bridge the sources of the FETs as shown. These connections are optional and may be beneficial in implementing the gain control circuitry.

[0054] In one embodiment, a single transistor is used in place of the transistors Q9 616 and Q10 624. Although shown with two pre-driver stages, the three dots indicate that additional pre-driver stages may be enabled. In one embodiment, the pre-driver has three stages. It should be noted that the transistors Q9 and Q10 function as a variable resistor but may be modeled as a variable resistor in parallel with a capacitor. Thus, with changes in the gain control signal, the resistance of transistors Q9 and Q10 changes, but the capacitance of these elements either do not change or the changes are insignificant. This provides the benefit of not reducing gain for high frequency components of the input signal at low and high gain levels. This in turn counters the inherent nature of transmission lines and circuits to attenuate high frequency signal components more than low frequency signal components. Thus, the gain changes more for low frequency than for high frequency, thus providing an additional benefit.

[0055] FIG. 6B is a block diagram illustrating an alternative embodiment of the pre-driver with gain control. In the embodiment of FIG. 6B, the interconnects 634 of FIG. 6A between node 644A and 644B is absent. Likewise, interconnect 630 between node 640A and node 640B is absent. These connections are optional and may be beneficial in implementing the gain control circuitry.

[0056] FIG. 7 illustrates a plot of gain versus frequency for the amplifier system with variable gain. This is but one possible plot of gain versus frequency for an amplifier as disclosed herein. The horizontal axis 704 represents frequency, while the vertical axis 708 represents gain. The plots 712 are shown for different gain levels. Plot 734 represents the signal at low gain levels while plot 730 represents the signal at high gain levels. As can be seen, the gain changes more at low frequency than high frequency and this is an added feature of this gain control circuit. This is desirable because at low gain levels, it is preferred to not reduce the gain of the high frequency components 720 because to do so would undesirably attenuate the high frequency components. This provides the benefit of frequency dependent equalization with less attenuation at high frequencies when gain is reduced.

[0057] Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

[0058] While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. In addition, the various features, elements, and embodiments described herein may be claimed or combined in any combination or arrangement.