FeFET transistor

[0001] This application claims the priority benefit of French Application for Patent No. 1870707, filed on Jun. 15, 2018, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

[0002] The present disclosure concerns a transistor and a method for manufacturing the transistor, and more particularly a FeFET-type transistor and a method for manufacturing the FeFET-type transistor.

[0003] A FeFET-type (“Ferroelectric Field Effect Transistor”) transistor is a transistor similar to a MOSFET-type (“Metal Oxide Semiconductor Field Effect Transistor”) transistor where the gate insulator layer is replaced with a layer made of an insulating and ferroelectric material.

[0004] It would be desirable to improve certain aspects of known FeFET-type transistors.

[0005] In an embodiment, a method is presented for manufacturing a first transistor on a semiconductor substrate, wherein a gate insulator layer is deposited on the substrate before deposition of a first ferroelectric layer.

[0006] According to an embodiment, a second MOS-type transistor is formed from the same substrate as the first transistor.

[0007] According to an embodiment, the gate insulator layer is a hafnium oxide layer.

[0008] According to an embodiment, the method also includes a step of depositing a first layer favoring the nucleation of an orthorhombic crystal structure between the gate insulator layer and the first ferroelectric layer.

[0009] According to an embodiment, the first layer favoring the nucleation of an orthorhombic crystal structure is made of a material made of one or of a combination of the following compounds: lanthanum, lanthanum oxides, germanium, germanium oxides, gadolinium, gadolinium oxides, strontium, strontium oxides, yttrium, yttrium oxides, aluminum, aluminum oxides, silicon, and silicon oxides.

[0010] According to an embodiment, the method includes steps of depositing a stack alternately including at least one second layer favoring the nucleation of an orthorhombic crystal structure and at least one second ferroelectric layer.

[0011] According to an embodiment, the stack is formed on the first ferroelectric layer.

[0012] Another embodiment provides a transistor including, between a substrate and a first ferroelectric layer, a gate insulator layer.

[0013] According to an embodiment, the gate insulator layer is a hafnium oxide layer.

[0014] According to an embodiment, the first ferroelectric layer is made of a hafnium oxide or of a zirconium oxide.

[0015] According to an embodiment, the transistor also includes an interface layer between the gate insulator layer and the substrate.

[0016] According to an embodiment, the interface layer is made of silicon oxynitride.

[0017] According to an embodiment, the first ferroelectric layer rests on a first layer favoring the nucleation of an orthorhombic crystal structure.

[0018] According to an embodiment, the transistor also includes a stack alternately having at least one second layer favoring the nucleation of an orthorhombic crystal structure and at least one second ferroelectric layer, the stack being arranged on the first ferroelectric layer.

[0019] Another embodiment provides an assembly of transistors including, inside and on top of a same substrate, a MOS type transistor and a transistor of a type described hereinabove or hereinbelow.

[0020] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

[0026] The same elements have been designated with the same reference numerals in the different drawings. In particular, the structural and/or functional elements common to the different embodiments may be designated with the same reference numerals and may have identical structural, dimensional, and material properties.

[0027] For clarity, those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the operation of a FeFET-type transistor will not be detailed, be it an N-type or P-type MOS transistor, as such operation is known to those of skill in the art.

[0028] In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., it is referred to the orientation of the drawings.

[0029] The terms “approximately”, “substantially”, and “on the order of” are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.

[0030] FIG. 1 is a cross-section view of an embodiment of a FeFET-type transistor 100. More particularly, transistor 100 is N-type, but a P-type transistor may be formed by inverting the biasing of the structure disclosed hereafter.

[0031] Transistor 100 is formed inside and on top of a semiconductor substrate 101, for example, a lightly P-type doped. Substrate 101 is, for example, made of silicon. Source and drain regions 102 and 103 are formed from the surface of substrate 101. Regions 102 and 103 extend from the upper surface of substrate 101, and are, for example, N-type doped. Regions 102 and 103 are separated from each other by a P-type doped channel region 105. The upper surface of channel region 105 has a stack successively comprising the following elements resting thereon: an interface layer 106 resting on top of and in contact with channel region 105; a gate insulator layer 107 resting on top of and in contact with interface layer 106; an insulating ferroelectric layer 108 resting on top of and in contact with gate insulator layer 107; and a gate layer 109 resting on top of and in contact with ferroelectric layer 108.

[0032] Interface layer 106 is, for example, made of silicon oxynitride (SiON). Interface layer 106 has a thickness preferably in the range from 0.5 nm to 2 nm, for example, on the order of 1.5 nm.

[0033] Gate insulator layer 107 is, for example, made of a hafnium oxide. Gate insulator layer 107 has a thickness preferably in the range from 1 nm to 3 nm, for example, on the order of 2 nm.

[0034] Ferroelectric layer 108 is, for example, made of a hafnium oxide and/or of a zirconium oxide. The material of layer 108 has an orthorhombic crystal structure favoring the ferroelectric character of the material. Ferroelectric layer 108 has a thickness preferably in the range from 2 to 12 nm, for example, on the order of 5 nm.

[0035] Gate layer 109 is made of a gate metal, for example, of titanium nitride (TiN). Gate layer 109 has a thickness preferably in the range from 2 nm to 10 nm, for example, on the order of 5 nm.

[0036] The placing of a gate insulator layer under a ferroelectric layer enables avoiding the presence of many asperities between the ferroelectric layer and the channel region which would trap charges during a turning-on of the transistor. Such asperities are generally present in a usual FeFET transistor despite the presence of a silicon oxide interface layer.

[0037] Advantage is thus taken from the fact, for MOS-type transistors, interfaces between a gate insulator and a channel region may be formed which are “clean”, that is, are interfaces comprising a density of asperities or a density of interface defects smaller than 10¹¹/cm².

[0038] FIGS. 2 and 3 show two phases of a method of manufacturing a gate of FeFET transistor 100 of FIG. 1 in parallel with a gate of a MOS transistor 200. More particularly, each of FIGS. 2A-2C and 3A-3C comprises a cross section view, each illustrating a step of the method. Further, each cross-section view shows, in a left-hand portion M, the forming of the gate of a MOS transistor 200 and, in a right hand portion F, the forming of the gate of a FeFET transistor 100.

[0039] FIG. 2A illustrates an initial structure resulting from a plurality of successive layer deposition steps. During these steps, interface and gate insulator layers 106 and 107 have been deposited on substrate 101. Layer 106 and 107 are deposited on portion M as well as on portion F.

[0040] In FIG. 2B, a protection layer 120 is deposited on the surface of the structure of FIG. 2A (portions M and F). Protection layer 120 is made of a material selectively etchable over the material of layer 107. As an example, to be selectively etchable over hafnium oxide, protection layer 120 is made of silicon, of silicon oxide, of polysilicon, or of silicon nitride.

[0041] In FIG. 2C, a portion of protection layer 120 covering portion F of gate insulation layer 107 is removed by masking. The remaining portions of protection layer 120 then form a mask protecting portion M.

[0042] In FIG. 3A, a layer of ferroelectric material 121 is deposited on the structure illustrated in relation with FIG. 2C. More particularly, layer 121 is, for example, formed by chemical vapor deposition (CVD) or for example by atomic layer deposition (ALD). Layer 121 is made of a material identical to layer 108 described in relation with FIG. 1.

[0043] In FIG. 3B, the portion of layer 120 covering portion M and the portion of layer 121 covering it are removed by a chemical etch step, for example, a gas phase chemical etching with the use of a plasma, or in liquid phase. Thus, the remaining portion of layer 121 forms, on portion F, the ferroelectric layer 108 described in relation with FIG. 1.

[0044] In FIG. 3C, gate layer 109 described in relation with FIG. 1 is deposited on the structure described in relation with FIG. 3B. The next step is a masking step, not shown, enabling completion of formation of the gates of transistors 100 and 200. The masking step is followed by an anneal operation, for example, at a temperature on the order of 650° C. The anneal phase enables the material of layer 108 to have an orthorhombic crystal structure and to thus have a ferroelectric behavior.

[0045] Once the gates of transistors 100 and 200 have been formed, source and drain regions are formed by doping portions of substrate 101. To achieve this, the layers stacked on the concerned portions of substrate 101 are etched, after which the portions are doped by different usual methods.

[0046] An advantage of this embodiment is that the method of manufacturing the gate of FeFET transistor 100 may be implemented in parallel with a MOS-type transistor manufacturing method, which enables forming a FeFET transistor accompanied by a logic circuit formed of one or a plurality of MOS transistors.

[0047] FIG. 4 is a cross-section view of another embodiment of a FeFET-type transistor 300 similar to transistor 100 described in relation with FIG. 1. Transistor 300 comprises the same elements as transistor 100, these elements being designated with the same reference numerals in FIG. 3 as in FIG. 1.

[0048] Transistor 300 further comprises a layer 301 favoring the nucleation of an orthorhombic crystal structure. Layer 301 is arranged between gate insulator layer 107 and ferroelectric layer 108. Layer 301 is made of a material made of one or of a combination of the following compounds: lanthanum, lanthanum oxides, germanium, germanium oxides, gadolinium, gadolinium oxides, strontium, strontium oxides, yttrium, yttrium oxides, aluminum, aluminum oxides, silicon, and silicon oxides. Layer 301 has a thickness preferably in the range from 0.05 to 1 nm, for example, on the order of 0.3 nm.

[0049] The method of manufacturing a FeFET-type transistor of the type of that in FIG. 4 comprises a step of depositing a layer made of a material favoring the nucleation of an orthorhombic crystal structure on layer 107 (of the step described in relation with the step of FIG. 2B). Thus, the growth of ferroelectric layer 121 (described in relation with the step of FIG. 3A) is directly performed on the layer favoring the nucleation of an orthorhombic crystal structure and thus layer 121 has an orthorhombic crystal structure.

[0050] FIG. 5 is a cross-section view of still another embodiment of a FeFET-type transistor 400 similar to transistor 300 described in relation with FIG. 4. Transistor 400 comprises the same elements as transistor 300, these elements being designated with the same reference numerals in FIG. 5 as in FIG. 4.

[0051] In this embodiment, ferroelectric layer 108 has a thickness in the range from 2 to 5 nm, for example, on the order of 3 nm.

[0052] Transistor 400 further comprises, between gate layer 109 and ferroelectric layer 108, a stack alternately comprising layer 401 favoring the nucleation of an orthorhombic crystal structure, and ferroelectric layers 403. In FIG. 5, the stack comprises a single layer 401 and a single layer 403. Layer 401 favoring the nucleation of an orthorhombic crystal structure has the same characteristics as layer 301. Ferroelectric layer 403 has the same characteristics as layer 108.

[0053] An advantage of this embodiment is that interposing layers favoring the nucleation of an orthorhombic crystal structure between ferroelectric layers enables better control of the crystal structure of the ferroelectric layers.

[0054] The definitions of the following terms used are:

• • [0055] lightly-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10¹⁴ to 5×10¹⁵ atoms/cm³;
  • [0056] heavily-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10¹⁷ to 10¹⁸ atoms/cm³; and
  • [0057] very heavily-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10¹⁸ to 10²⁰ atoms/cm³.

[0058] Specific embodiments have been described. Various alterations and modifications will occur to those skilled in the art. In particular, any insulating ferroelectric material may be used to form the electric layer.

[0059] It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step.

[0060] Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.