US 10,643,129 B2Grant
Apparatus and methods for training in convolutional neural networks
Issue Date:2020-05-05
•27 Claims
•8 Drawing Sheets
Abstract
Aspects for backpropagation of a convolutional neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient, wherein the master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.
Metadata
Assignee
- CAMBRICON TECHNOLOGIES CORPORATION LIMITED
Inventors
- Yunji Chen
- Tian Zhi
- Shaoli Liu
- Qi Guo
- Tianshi Chen
Application Information
Application Number:US 16/174,165
Filing Date:2018-10-29
Priority Date:2016-04-29
Art Unit:2122
Classifications
IPC:
G06N3/08G06F7/544
Field of Search:
G06F 13/362G06F 17/16G06F 9/30G06F 9/3001G06N 3/0454G06N 3/063
Patent Drawings (8 sheets)
Description
Cross-Reference to Related Applications
[0001] The present invention is a continuation-in-part of PCT Application No. PCT/CN2016/081088, filed on May 5, 2016, which claims priority to commonly owned CN application number 201610283838.5, filed on Apr. 29, 2016. The entire contents of each of the aforementioned applications are incorporated herein by reference.
Technical Field
[0002] The present disclosure generally relates to the technical field of artificial neural network, and specifically, relates to an apparatus and method for backpropagation of a convolutional artificial neural network.
Background
[0003] Convolutional artificial neural networks have been widely applied in pattern recognition and image processing for its high efficiency. One known type of devices for convolutional artificial neural networks is to implement a general-purpose processor, which includes a general-purpose register file and a general-purpose functional unit to execute general purpose instructions to support algorithms for convolutional artificial neural networks. However, one of the defects of the method is lower operational performance of a single general-purpose processor which cannot meet performance requirements for usual multilayer neural network operations. When multiple general-purpose processors execute concurrently, the intercommunication among them also becomes a performance bottleneck.
[0004] Another known type of devices may involve a graphics processing unit (GPU), which includes a general-purpose register file and a general-purpose stream processing unit to execute general purpose single-instruction-multiple-data (SIMD) instructions to support the algorithms. However, since GPU only contains rather small on-chip caching, then model data (weight values) of a multilayer artificial neural network may be repeatedly moved from the off-chip, and off-chip bandwidth becomes a main performance bottleneck, causing huge power consumption.
Summary
[0005] The following presents a simplified summary of one or more aspects to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
[0006] One example aspect of the present disclosure provides an example apparatus for backpropagation in a convolutional artificial neural network. The example apparatus may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the example apparatus may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient. The master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.
[0007] Another example aspect of the present disclosure provides an example method for backpropagation of a convolutional artificial neural network. The example method may include receiving, by a direct memory access unit, input data from a storage device and selecting, by a master computation module, one or more portions of the input based on a predetermined convolution window. The example method may further include convoluting, by one or more slave computation modules, one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient. Further still, the example method may include updating, by the master computation module, a prestored convolution kernel based on the kernel gradient.
[0008] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features herein after fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.
Brief Description of the Drawings
[0009] The disclosed aspects will hereinafter be described in conjunction with the appended drawings, provided to illustrate and not to limit the disclosed aspects, wherein like designations denote like elements, and in which:
[0010] FIG. 1 is a block diagram illustrating an example forward propagation process and an example backpropagation process in a convolutional neural network;
[0011] FIG. 2 is a block diagram illustrating an example backpropagation computing process in a convolutional neural network;
[0012] FIG. 3 is a block diagram illustrating an overall structure of a neural network acceleration processor by which backpropagation may be implemented in a convolutional neural network;
[0013] FIG. 4 is a block diagram illustrating an overall structure of an interconnection unit by which backpropagation may be implemented in a convolutional neural network;
[0014] FIG. 5 is a block diagram illustrating the overall structure of a slave computation module by which backpropagation may be implemented in a convolutional neural network;
[0015] FIG. 6 is a block diagram illustrating the overall structure of a master computation module by which forward propagation may be implemented in a convolutional neural network; and
[0016] FIG. 7 is a flow chart of an example method for backpropagation in a convolutional neural network according to embodiments of the present disclosure.
Detailed Description
[0017] Various aspects are now described with reference to the drawings. In the following description, for purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspect(s) may be practiced without these specific details.
[0018] In the present disclosure, the term “comprising” and “including” as well as their derivatives mean to contain rather than limit; the term “or”, which is also inclusive, means and/or.
[0019] In this specification, the following various embodiments used to illustrate principles of the present disclosure are only for illustrative purpose, and thus should not be understood as limiting the scope of the present disclosure by any means. The following description taken in conjunction with the accompanying drawings is to facilitate a thorough understanding to the illustrative embodiments of the present disclosure defined by the claims and its equivalent. There are specific details in the following description to facilitate understanding. However, these details are only for illustrative purpose. Therefore, persons skilled in the art should understand that various alternation and modification may be made to the embodiments illustrated in this description without going beyond the scope and spirit of the present disclosure. In addition, for clear and concise purpose, some known functionality and structure are not described. Besides, identical reference numbers refer to identical function and operation throughout the accompanying drawings.
[0020] FIG. 1 is a block diagram illustrating an example forward propagation process and an example backpropagation process (collectively, computing process 100) in a convolutional neural network. The computing process 100 is a merely example showing neural network operations that involve input data and weight values and is not limited to such operations. For example, other unshown neural network operations may include pooling operations, etc. Since convolution operation may be a major operation in the computing process 100, the illustrated multilayer neural network may be also referred to as a convolutional neural network.
[0021] As depicted, the example computing process 100 may be performed from the ith layer to the (i+1)th layer. The term “layer” here may refer to a group of operations, rather than a logic or a physical layer. A triangular-shaped operator (Δ as shown in FIG. 1 ) may indicate one or more neural network operations. Examples of the neural network operations may include an activation function, a bias operation, a matrix multiplication, a convolution operation, or any combination thereof. It is notable that the illustrated layers of operations may not be the first layer and the last layer of the entire computing process. Rather, the layers of operations may refer to any two consecutive layers in a neural network. As described below in greater detail, the computing process from the ith layer to the (i+1)th layer may be referred to as a forward propagation process; the computing process from (i+1)th layer to the ith layer may be referred to as a backward propagation (also may be interchangeably referred to as backpropagation) process.
[0022] The forward propagation process may start from input neuron data received at the ith layer (e.g., input neuron data 102A). Hereinafter, input neuron data may refer to the input data at each layer of operations, rather than the input data of the entire neural network. Similarly, output neuron data may refer to the output data at each layer of operations, rather than the output data of the entire neural network.
[0023] The received input neuron data 102A may be multiplied or convolved by one or more weight values 102C. The weight values 102C, stored as weight vectors, may also be referred to as a convolution kernel. The results of the multiplication or convolution may be transmitted as output neuron data 104A. In some examples, an activation function may be applied to the output neuron data 104A. The output neuron data 104A may be transmitted to the next layer (e.g., the (i+1)th layer) as input neuron data 106A. The forward propagation process may be shown as the solid lines in FIG. 1 .
[0024] The backward propagation process may start from the last layer of the forward propagation process. For example, the backward propagation process may include the process from the (i+1)th layer to the ith layer. During the process, the input data gradients 106B may be transmitted to the ith layer as output gradients 104B. The output gradients 104B may then be multiplied or convolved by the input neuron data 102A to generate weight gradients 102D. Additionally, the output gradients 104B may be multiplied by the weight values 102C to generate input data gradients 102B.
[0025] In some examples where the (i+1)th layer is the last layer of the forward propagation process, the input data gradients 106B may be determined based on a difference between the input neuron data 106A and expected neuron data. The backward propagation process may be shown as the dotted lines in FIG. 1 .
[0026] FIG. 2 is a block diagram illustrating an example backpropagation computing process in a convolutional neural network.
[0027] As depicted, input data 202 (e.g., input neuron data 102A) may be stored or presented in a two-dimensional format, e.g., W number of values horizontally and H number of values vertically, or stored as a two-dimensional vector. In some non-limiting examples, the input data 202 may refer to an image in a pattern recognition process executed in a convolutional neural network. As the size of the input data 202 may be large and may reduce overall system efficiency, the input data 202 may be segmented or divided into multiple subsets of data for further processing.
[0028] For example, a convolution window 204 may be predetermined for the segmentation or division. The convolution window 204 may be predetermined to be a fixed two-dimensional data range. That is, the data range in one dimension may be set to Kx number of values and the data range in the other dimension may be set to Ky number of values. In the example of a two-dimensional image, the convolution window 104 may refer to an area that includes Kx number of horizontal pixels and Ky number of vertical pixels.
[0029] The input data 202 within the convolution window 204 may be selected and transmitted, e.g., by a master computation module 312, to other components (e.g., slave computation modules 314) for further processing. The master computation module 312 and the slave computation modules 314 are described in greater detail in accordance with FIG. 3 . Once the processing is completed, the convolution window 204 may be configured to slide or move by a predetermined distance, e.g., Sx number of values in the one dimension or Sy number of values in the other dimension, to identify another subset of the input data 202. The newly identified subset of the input data may be transmitted and similarly processed. In some examples, the convolution window 204 may be configured to slide in one dimension, e.g., sliding by Sx number of values horizontally as shown in FIG. 1 , until the input data 202 in this dimension has been processed. The convolution window 204 may then be configured to move in another dimension, e.g., moving by Sy vertically as shown in FIG. 1 .
[0030] In at least one example, Sx may be set to a value that is greater than, equal to, or less than Kx. That is, when Sx is greater than Kx, some portions of the input data 202 may not be selected and further transmitted. When Sx is equal to Kx, all the input data 202 may be processed sequentially. When Sx is less than Kx, some of the input data 202 may be processed more than once.
[0031] In the forward propagation process, a portion of the input data 202 identified by the convolution window 204 (hereinafter referred to as “Xi”) may be transmitted to one or more slave computation modules 314 (e.g., 314A, 314B, 314C, . . . 314N). Each of the slave computation modules 314 may be configured to multiply the received Xi with a prestored convolution kernel (e.g., convolution kernel 206A). Convolution kernels 206A, 206B, 206C, . . . 206N may be collectively referred to as convolution kernels 206. The convolution kernel stored in each of the slave computation modules 314 may refer to a portion of the weight values 102C. In other words, the weight values 102C may be divided into portions and respectively transmitted to the slave computation modules 314 and stored as the convolution kernel 206. Thus, in some examples, each slave computation module may store a convolution kernel that may be different from other convolution kernels stored in other slave computation modules. As the convolution kernel 206N may be a portion of the weight values 102C, the convolution kernel 206N may be stored or formatted as a group of two-dimensional data, e.g., a two-dimensional vector. The multiplication results of the received Xi and the prestored convolution kernel may be output to a combiner 209 of an interconnection unit 308. The combiner 209 may be configured to add the multiplication results. An activation function may be further applied to the sum of the multiplication results, e.g., by a master computation module 312.
[0032] As described according to FIG. 1 , the backpropagation process may include two sub-processes, i.e., calculating the weight gradients 102D and calculating the input data gradients 102B. In the sub-process of calculating the weight gradients 102D, each of the slave computation modules 314 may receive the portion of the input data 202 identified by the convolution window and output gradients 216. The output gradients 216 may refer to one or more data gradients calculated at and output from a lower layer of the backpropagation process. For example, the output gradients 216 may refer to the output gradients 104B from the (i+1)th layer in FIG. 1 .
[0033] Each of the slave computation modules 314 may be configured to multiply the output gradients 216 with the selected portion of the input data 202 (e.g., Xi) to generate a kernel gradient. The multiplication may be represented as Xidsi, in which Xi represents the selected portion of the input data 202 and dsi represents the output gradients 216. Further, with respect to different portions of the input data 202 selected based on adjusted convolution window 204, each of the slave computation modules 314 may calculate a respective kernel gradient. The master computation module 312 or the interconnection unit 308 may be configured to sum the respective kernel gradients to generate a summed kernel gradient. The summed kernel gradient may be represented as dw=ΣXidsi and may be further processed by the master computation module 312.
[0034] The master computation module 312 may be configured to calculate a quadratic mean of the summed kernel gradient. The quadratic mean may be represented as
[0035]
in which n may refer to a count of the slave computation modules 314. Further, the master computation module 312 may be configured to compare the quadratic mean to a predetermined threshold. If the quadratic mean is greater than the threshold, the master computation module 312 may be configured to calculate a scaled kernel gradient based on the threshold and the quadratic mean. For example, the scaled kernel gradient may be calculated in accordance with the following equation: dw′=dw/c*t, in which dw represents the summed kernel gradient, c represents the quadratic mean, t represents the predetermined threshold, and dw′ represents the scaled kernel gradient. The weight values 102C and the convolution kernels 206 may be updated based on the scaled kernel gradients. That is, the master computation module 312 may be configured to add the scaled kernel gradients to the weight values 102C or the convolution kernels 206 to generate a new set of weight values. If the quadratic mean is less than the threshold, the master computation module 312 may be configured to add the summed kernel gradient to the weight values 102C and/or the convolution kernels 206 to generate a new set of weight values.
in which n may refer to a count of the slave computation modules 314. Further, the master computation module 312 may be configured to compare the quadratic mean to a predetermined threshold. If the quadratic mean is greater than the threshold, the master computation module 312 may be configured to calculate a scaled kernel gradient based on the threshold and the quadratic mean. For example, the scaled kernel gradient may be calculated in accordance with the following equation: dw′=dw/c*t, in which dw represents the summed kernel gradient, c represents the quadratic mean, t represents the predetermined threshold, and dw′ represents the scaled kernel gradient. The weight values 102C and the convolution kernels 206 may be updated based on the scaled kernel gradients. That is, the master computation module 312 may be configured to add the scaled kernel gradients to the weight values 102C or the convolution kernels 206 to generate a new set of weight values. If the quadratic mean is less than the threshold, the master computation module 312 may be configured to add the summed kernel gradient to the weight values 102C and/or the convolution kernels 206 to generate a new set of weight values.
[0036] In the sub-process of calculating the input data gradients 102B, the slave computation modules 314 may be configured to multiply the output gradients 216 with each of the convolution kernels 206 respectively. The interconnection unit 308 may be configured to sum the respective multiplication results. The master computation module 312 may be configured to multiply the summed results with a derivative of an activation function. The activation function may be a sigmoid function, a tanh function, a relu function, and a softmax function.
[0037] For example, the input data gradients 102B may be calculated in accordance with the following equation: dx=h(x)Σwidsi, in which h(x) represents the derivative of the activation function, wi represents one of the convolution kernels 206, dsi represents the output gradients 216, and dx represents the input data gradients 102B.
[0038] FIG. 3 is a block diagram illustrating an overall structure of a neural network acceleration processor 300 by which a backpropagation process may be implemented in a convolutional neural network.
[0039] As shown in FIG. 3 , the neural network acceleration processor 300 includes an instruction caching unit 304, a controller unit 306, a direct memory access unit 302, an interconnection unit 308, a plurality of computation modules 310 that may include the master computation module 312, and the one or more slave computation modules 314 (e.g., 314A, 314B . . . 314N). Any of the above-mentioned components or devices may be implemented by a hardware circuit (e.g., application specific integrated circuit (ASIC)).
[0040] In some examples, the instruction caching unit 304 may be configured to receive or read instructions from the direct memory access unit 302 and cache the received instructions. The controller unit 306 may be configured to read instructions from the instruction caching unit 304 and decode one of the instructions into micro-instructions for controlling operations of other modules including the direct memory access unit 302, the master computation module 312, the slave computation modules 314, etc. In other words, the modules including the direct memory access unit 302, the master computation module 312, and the slave computation modules 314 may be configured to respectively perform the micro-instructions.
[0041] The direct memory access unit 302 may be configured to access an external address range (e.g., in an external storage device such as a memory 301) and directly read or write data into respective caching units in the computation modules 310.
[0042] In some example, an IO instruction may be pre-stored into a head address of the instruction caching unit 304. The IO instruction may instruct the direct memory access unit 302 to read the input data 202 from an external address space, e.g., the memory 301. The IO instruction may further instruct the direct memory access unit 302 to store the output data 214 back into the external space after completion of computation.
[0043] The controller unit 306 may be configured to read the IO instruction from the head address of the instruction caching unit 304. According to the decoded micro-instruction, the direct memory access unit 302 may be configured to read data relevant to the forward propagation (e.g., the input data 202, an interpolation table for the activation function, a bias value, parameters to configure the computation modules 310) and to store the above data to the master computation module 312.
[0044] The controller unit 306 may be further configured to read a next IO instruction from the instruction caching unit 304. According to the decoded micro-instructions of this IO instruction, the direct memory access unit 302 may be configured to read the one or more convolution kernels 206 from the memory 301. The convolution kernels 206 may be respectively transmitted to the slave computation modules 314.
[0045] Further still, the controller unit 306 may be configured to read a CONFIG instruction from the instruction caching unit 304 to configure the parameters for processing at the computation modules 310.
[0046] Once the computation modules 310 are configured accordingly, the controller unit 306 may be configured to read a COMPUTE instruction. The master computation module 312 may be configured, according the decoded micro-instruction of the COMPUTE instruction, to select a portion of the input data 202 based on the convolution window 204. Further, the master computation module 312 may transmit the selected portion of the input data 202 (e.g., Xi) to the slave computation modules 314 via the interconnection unit 308. Further, the master computation module 312 may be configured to transmit the output gradients 216 to the slave computation modules 314.
[0047] In some examples, the COMPUTE instruction may be one of a convolution network sigmoid derivative instruction, a convolution network tanh derivative instruction, a convolution network relu derivative instruction, or a convolution softmax derivative instruction.
[0048] The convolution network sigmoid derivative instruction may include an address of the output gradients 216, a size of the output gradients 216, an address of the portion of the convolution kernel 206, a size of the portion of the convolution kernel 206, and an indication of a derivative of a sigmoid function.
[0049] The convolution network tanh derivative instruction may include an address of the output gradients 216, a size of the output gradients 216, an address of the portion of the convolution kernel 206, a size of the portion of the convolution kernel 206, and an indication of a derivative of a tanh function.
[0050] The convolution network relu derivative instruction may include an address of the output gradients 216, a size of the output gradients 216, an address of the portion of the convolution kernel 206, a size of the portion of the convolution kernel 206, and an indication of a derivative of a relu function.
[0051] The convolution network softmax derivative instruction may include an address of the output gradients 216, a size of the output gradients 216, an address of the portion of the convolution kernel 206, a size of the portion of the convolution kernel 206, and an indication of a derivative of a softmax function.
[0052] In accordance with the decoded micro-instructions, each of the slave computation modules 314 may be configured to multiply the output gradients 216 with the selected portion of the input data 202 (e.g., Xi) to generate a kernel gradient. The multiplication may be represented as Xidsi, in which Xi represents the selected portion of the input data 202 and dsi represents the output gradients 216. Further, with respect to different portions of the input data 202 selected based on adjusted convolution window 204, each of the slave computation modules 314 may calculate a respective kernel gradient. The kernel gradients may be summed up by the interconnection unit 308 and transmitted to the master computation module 312. The summed kernel gradient may be represented as dw=Σxidsi. The master computation module 312 may be configured to calculate a quadratic mean of the summed kernel gradients and calculate another set of weight values to update the weight values 102C based on the summed kernel gradients.
[0053] Additionally, the master computation module 312 may be configured to multiply the output gradients 216 with each of the convolution kernel 206 respectively. The master computation module 312 may be configured to multiply the output gradients 216 with each of the convolution kernel 206 respectively to generate the input data gradients 102B.
[0054] Formats of the abovementioned instructions are provided here in Table 1.
[0055]
| TABLE 1 | |||||||
|---|---|---|---|---|---|---|---|
| Instruction | |||||||
| (Operation Code) | Register 0 | Register 1 | Register 2 | Register 3 | Register 4 | Register 5 | Register 6 |
| COMPUTE | Starting | Data | Starting | Data | Starting | Data | Address of |
| address | length of | address of | length of | address | length | interpolation | |
| of input | input data | convolution | convolution | of output | of output | table of activation | |
| data | kernel | kernel | gradients | gradients | function | ||
| IO | Address | Data | Address | ||||
| of external | length | of internal | |||||
| storage | storage | ||||||
| device | device | ||||||
| NOP | |||||||
| JUMP | Target | ||||||
| address | |||||||
| MOVE | Address | Data size | Address | ||||
| of input | of output | ||||||
| data | data | ||||||
[0056] FIG. 4 is a block diagram illustrating an overall structure of an interconnection unit by which backpropagation may be implemented in a convolutional neural network.
[0057] As depicted, the interconnection unit 308 may be structured as a binary tree that includes multiple levels (e.g., from top level to lower levels). Each level may include one or more nodes. Each node may be configured to send data to two nodes at a lower level. Further, each node may combine or add data received from two nodes at a lower level. The combined data may be transmitted to a node at a higher level. For example, the received data (e.g., a and b) from the two nodes at the lower level may be combined into a 2-dimensional vector (e.g., (a, b)) by the node at this level. The combined data, i.e., the 2-dimensional vector may be transmitted to a node at a higher level and further combined into a 4-dimensional vector. Alternatively, or additionally, each node may be configured to add data received from the two nodes at the lower level and the sum of the addition may be sent to the node at the high level.
[0058] As shown in FIG. 4 , the nodes of the binary tree at the lowest levels may be connected to the slave computation modules 314. The data output from the slave computation modules 314 may be combined or summed at the multiple levels to generate a value or a vector at the first level node 402. The generated value or vector may be transmitted to the master computation module 312.
[0059] FIG. 5 is a block diagram illustrating the overall structure of a slave computation module 314N by which backpropagation may be implemented in a convolutional neural network.
[0060] As shown in FIG. 5 , the slave computation module 314N comprises a slave computation unit 502, a slave data dependency relationship determination unit 504, a slave neuron caching unit 506, and a weight value caching unit 508. Hereinafter, a caching unit (e.g., a master neuron caching unit 606, a slave neuron caching unit 506, a weight value caching unit 508, etc.) may refer to an on-chip caching unit integrated in the neural network acceleration processor 300, rather than other storage devices in memory 301 or other external devices. In some examples, the on-chip caching unit may be implemented as an on-chip buffer, an on-chip Static Random Access Memory (SRAM), or other types of on-chip storage devices that may provide higher access speed than the external memory.
[0061] The slave data dependency relationship determination unit 504 may be configured to perform data access operations (e.g., reading or writing operations) on the caching units including the slave neuron caching unit 506 and the weight value caching unit 508 during the computation process. The slave data dependency relationship determination unit 504 may be configured to prevent conflicts in reading and writing of the data in the caching units including the slave neuron caching unit 506 and the weight value caching unit 508. For example, the slave data dependency relationship determination unit 504 may be configured to determine whether there is dependency relationship in terms of data between a micro-instruction which to be executed and a micro-instruction being executed. If no dependency relationship exists, the micro-instruction may be allowed to be executed; otherwise, the micro-instruction may not be allowed to be executed until all micro-instructions on which it depends have been executed completely. The dependency relationship may be determined when a target operation range of the micro-instruction to be executed overlaps a target operation range of a micro-instruction being executed. For example, all micro-instructions sent to the slave data dependency relationship determination unit 504 may be stored in an instruction queue within the slave data dependency relationship determination unit 504. The instruction queue may indicate the relative priorities of the stored micro-instructions. In the instruction queue, if the target operation range of reading data by a reading instruction conflicts with or overlaps the target operation range of writing data by a writing instruction of higher priority in the front of the instruction queue, then the reading instruction may not be executed until the writing instruction is executed.
[0062] The slave neuron caching unit 506 may be configured to store the selected portion of the input data 202 and the weight value caching unit 508 may be configured to store the convolution kernel 206N.
[0063] The slave computation unit 502 may be configured to receive micro-instructions decoded from a COMPUTE instruction from the controller unit 306 and perform arithmetical logic operations according to the micro-instructions. In some examples, the slave computation unit 502 may further include a vector multiplier 510 and the adder 208N.
[0064] In the sub-process of calculating the weight gradients 102D, the vector multiplier 510 may be configured to multiply elements in the output gradients 216 with elements the selected portion of the input data 202 (e.g., Xi). The results of the multiplication may be added by the adder 208N to generate a result of the vector multiplication as a kernel gradient. One or more kernel gradients generated by respective slave computation modules may be transmitted to the interconnection unit 308. The interconnection unit 308 or the master computation module 312 may be configured to sum the respective kernel gradients.
[0065] In the sub-process of calculating the input data gradients 102B, the vector multiplier 510 may be configured to multiply the output gradients 216 with each of the convolution kernel 206 respectively. For example, the input data gradients 102B may be calculated in accordance with the following equation: dx=h(x)Σwidsi, in which h(x) represents the derivative of the activation function, wi represents one of the convolution kernels 206, dsi represents the output gradients 216, and dx represents the input data gradients 102B. The vector multiplier 510 may be configured to calculate the multiplication between wi and dsi. The multiplication results may be transmitted to the interconnection unit 308 that may be further configured to calculate a sum of the multiplication results, e.g., Σwidsi.
[0066] FIG. 6 is a block diagram illustrating the overall structure of a master computation module by which forward propagation may be implemented in a convolutional neural network.
[0067] As shown in FIG. 6 , the master computation module 312 may include a master computation unit 602, a master data dependency relationship determination unit 604, and a master neuron caching unit 606. The master computation unit 602 may further include a window controller 608, an adder 210, and an activator 212.
[0068] Similar to the slave data dependency relationship determination unit 504, the master data dependency relationship determination unit 604 may be configured to perform data access operations (e.g., reading or writing operations) on the caching units including the master neuron caching unit 606 during the computation process. The master data dependency relationship determination unit 604 may be configured to prevent conflicts in reading and writing of the data in the caching units including the master neuron caching unit 606. For example, the master data dependency relationship determination unit 604 may be configured to determine whether there is dependency relationship in terms of data between a micro-instruction which to be executed and a micro-instruction being executed. If no dependency relationship exists, the micro-instruction may be allowed to be executed; otherwise, the micro-instruction may not be allowed to be executed until all micro-instructions on which it depends have been executed completely. The dependency relationship may be determined when a target operation range of the micro-instruction to be executed overlaps a target operation range of a micro-instruction being executed. For example, all micro-instructions sent to the master data dependency relationship determination unit 604 may be stored in an instruction queue within the master data dependency relationship determination unit 604. The instruction queue may indicate the relative priorities of the stored micro-instructions. In the instruction queue, if the target operation range of reading data by a reading instruction conflicts with or overlaps the target operation range of writing data by a writing instruction of higher priority in the front of the instruction queue, then the reading instruction may not be executed until the writing instruction is executed.
[0069] The master neuron caching unit 606 may be configured to store the data related to the convolution window 204 including the data range, e.g., Kx and Ky, the predetermined distance for sliding or moving the convolution window, e.g., Sx number of values in the one dimension or Sy number of values in the other dimension. Further, the master neuron caching unit 606 may be configured to store results calculated by the slave computation modules 314.
[0070] In the sub-process of calculating the weight gradients 102D, the one or more kernel gradients generated by the slave computation modules 314 may be transmitted to the master computation module 312. The adder 210 may be configured to add the respective kernel gradients to generate a summed kernel gradient. The summed kernel gradient may be represented as dw=Σxidsi.
[0071] Further, in calculating the weight gradients 102D, the window controller 608 may be configured to slide or move the convolution window 204 by the predetermined distance, e.g., Sx number of values in the one dimension or Sy number of values in the other dimension, to identify different subsets of the input data 202. In some examples, the convolution window 204 may be configured to slide in one dimension, e.g., sliding by Sx number of values horizontally as shown in FIG. 1 , until the input data 202 in this dimension has been processed. The convolution window 204 may then be configured to move in another dimension, e.g., moving by Sy vertically as shown in FIG. 1 .
[0072] In the sub-process of calculating the input data gradients 102B, the sum of the multiplication results, e.g., Σwidsi, may be received by the master computation module 312. The activator 212 may be configured to apply a derivative of the activation function to the sum of the multiplication results to generate the input data gradients 102B, e.g., dx=h(x)Σwidsi, in which h(x) represents the derivative of the activation function, wi represents one of the convolution kernels 206, dsi represents the output gradients 216, and dx represents the input data gradients 102B.
[0073] In some examples, the one or more kernel gradients, the summed kernel gradient, the sum of the multiplication results, and other intermediate process results may be also stored in the master neuron caching unit 606.
[0074] FIG. 7 is a flow chart of an example method 700 for backpropagation in a convolutional neural network according to embodiments of the present disclosure. The example method 700 may be performed by one or more components as described in FIGS. 2, 3, 5, and 6 . Optional operations may be indicated by dash-lined blocks.
[0075] At block 702, the example method 700 may include receiving, by a direct memory access unit, input data from a storage device. For example, the direct memory access unit 102 may be configured to receive the input data, e.g., input neuron data 102A, and the weight values 102C from the memory 301.
[0076] At block 704, the example method 700 may include selecting, by a master computation module, one or more portions of the input based on a predetermined convolution window. For example, the master computation module 312 may be configured, according the decoded micro-instruction of the COMPUTE instruction, to select a portion of the input data 202 based on the convolution window 204. Further, the master computation module 312 may transmit the selected portion of the input data 202 (e.g., Xi) to the slave computation modules 314 via the interconnection unit 308. Further, the master computation module 312 may be configured to transmit the output gradients 216 to the slave computation modules 314.
[0077] At block 706, the example method 700 may include convoluting, by one or more slave computation modules, one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient. For example, each of the slave computation modules 314 may be configured to multiply the output gradients 216 with the selected portion of the input data 202 (e.g., Xi) to generate a kernel gradient.
[0078] At block 708, the example method 700 may include updating, by the master computation module, a prestored convolution kernel based on the kernel gradient. For example, the master computation module 312 or the interconnection unit 308 may be configured to sum the respective kernel gradients to generate a summed kernel gradient. The master computation module 312 may be configured to calculate a quadratic mean of the summed kernel gradient. Further, the master computation module 312 may be configured to compare the quadratic mean to a predetermined threshold. If the quadratic mean is greater than the threshold, the master computation module 312 may be configured to calculate a scaled kernel gradient based on the threshold and the quadratic mean. For example, the scaled kernel gradient may be calculated in accordance with the following equation: dw′=dw/c*t, in which dw represents the summed kernel gradient, c represents the quadratic mean, t represents the predetermined threshold, and dw′ represents the scaled kernel gradient. The weight values 102C and the convolution kernels 206 may be updated based on the scaled kernel gradients. That is, the master computation module 312 may be configured to add the scaled kernel gradients to the weight values 102C or the convolution kernels 206 to generate a new set of weight values. If the quadratic mean is less than the threshold, the master computation module 312 may be configured to add the summed kernel gradient to the weight values 102C and/or the convolution kernels 206 to generate a new set of weight values.
[0079] At block 710, the example method 700 may include multiplying, by the one or more slave computation modules, at least a portion of the prestored convolution kernel with the one or more first data gradients. For example, the slave computation modules 314 may be configured to multiply the output gradients 216 with each of the convolution kernel 206 respectively. The interconnection unit 308 may be configured to sum the respective multiplication results.
[0080] At block 714, the example method 700 may include calculating, by the master computation module, one or more second data gradients based on a derivative of the activation function and a sum of one or more multiplication results between the first data gradients and the portion of the prestored convolution kernel. For example, the master computation module 312 may be configured to multiply the summed results with a derivative of an activation function. The activation function may be a sigmoid function, a tanh function, a relu function, and a softmax function.
[0081] The process or method described in the above accompanying figures can be performed by process logic including hardware (for example, circuit, specific logic etc.), firmware, software (for example, a software being externalized in non-transitory computer-readable medium), or the combination of the above two. Although the process or method is described above in a certain order, it should be understood that some operations described may also be performed in different orders. In addition, some operations may be executed concurrently rather than in order.
[0082] In the above description, each embodiment of the present disclosure is illustrated with reference to certain illustrative embodiments. Apparently, various modifications may be made to each embodiment without going beyond the wider spirit and scope of the present disclosure presented by the affiliated claims. Correspondingly, the description and accompanying figures should be understood as illustration only rather than limitation. It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
[0083] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described herein that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
[0084] Moreover, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, the phrase “X employs A or B” is satisfied by any of the following instances: X employs A; X employs B; or X employs both A and B. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.
Claims
We claim:
1. An apparatus for backpropagation of a convolutional neural network, comprising:
a master computation circuit configured to:
receive input data, and
select one or more portions of the input data based on a predetermined convolution window in response to an instruction; and
one or more slave computation circuits respectively configured to convolute one of the one or more portions of the input data with one of one or more calculated first data gradients to generate a kernel gradient,
wherein the master computation circuit is further configured to update a prestored convolution kernel based on the kernel gradient,
wherein the one or more slave computation circuits are respectively configured to multiply at least a portion of the prestored convolution kernel with the one or more first data gradients, and
wherein the master computation circuit is further configured to calculate one or more second data gradients based on a derivative of an activation function and a sum of one or more multiplication results between the first data gradients and the portion of the prestored convolution kernel.
2. The apparatus of claim 1, wherein the activation function is a function selected from the group consisting a sigmoid function, a tanh function, a relu function, and a softmax function.
3. The apparatus of claim 1, further comprising an interconnection circuit configured to sum the one or more kernel gradients respectively generated by the one or more slave computation circuits to generate a summed kernel gradient.
4. The apparatus of claim 3, wherein the master computation circuit is further configured to calculate a quadratic mean of the summed kernel gradient generated by the interconnection circuit.
5. The apparatus of claim 1, further comprising an interconnection circuit configured to channel data between the master computation circuit and the one or more slave computation circuits.
6. The apparatus of claim 5, wherein the interconnection circuit is configured to calculate a sum of one or more multiplication results between the first data gradients and the portion of the prestored convolution kernel.
7. The apparatus of claim 1, wherein each of the one or more slave computation circuits includes a slave neuron caching circuit configured to store one of the one or more portions of the input data.
8. The apparatus of claim 1, each of the one or more slave computation circuits includes a weight value caching circuit configured to store a portion of the prestored convolution kernel that correspond to the slave computation circuit.
9. The apparatus of claim 1, wherein the master computation circuit includes a window controller circuit configured to adjust the predetermined convolution window to select the one or more portions of the input data.
10. The apparatus of claim 1, wherein the instruction is selected from the group consisting of a convolution network sigmoid derivative instruction, a convolution network tanh derivative instruction, a convolution network relu derivative instruction, and a convolution network softmax derivative instruction.
11. The apparatus of claim 10, wherein the convolution network sigmoid derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a sigmoid function.
12. The apparatus of claim 10, wherein the convolution network tanh derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a tanh function.
13. The apparatus of claim 10, wherein the convolution network relu derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a relu function.
14. The apparatus of claim 10, wherein the convolution network softmax derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a softmax function.
15. A method for backpropagation of a convolutional neural network, comprising:
receiving, by a direct memory access circuit, input data from a storage device;
selecting, by a master computation circuit, one or more portions of the input data based on a predetermined convolution window in response to an instruction;
convoluting, by one or more slave computation circuits, one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient;
updating, by the master computation circuit, a prestored convolution kernel based on the kernel gradient,
multiplying, by the one or more slave computation circuits, at least a portion of the prestored convolution kernel with the one or more first data gradients;
calculating, by the master computation circuit, one or more second data gradients based on a derivative of an activation function and a sum of one or more multiplication results between the first data gradients and the portion of the prestored convolution kernel.
16. The method of claim 15, further comprising summing, by an interconnection circuit, the one or more kernel gradients respectively generated by the one or more slave computation circuits to generate a summed kernel gradient.
17. The method of claim 16, further comprising calculating, by the master computation circuit, a quadratic mean of the summed kernel gradient respectively generated by the interconnection circuit.
18. The method of claim 15, further comprising channeling data, by an interconnection circuit, between the master computation circuit and the one or more slave computation circuits.
19. The method of claim 18, further comprising calculating, by the interconnection circuit, a sum of one or more multiplication results between the first data gradients and the portion of the prestored convolution kernel.
20. The method of claim 15, further comprising storing, by a slave neuron caching circuit of each of the one or more slave computation circuits, one of the one or more portions of the input data.
21. The method of claim 15, further comprising storing, by a weight value caching circuit of each of the one or more slave computation circuits, a portion of the convolution kernel that correspond to the slave computation circuit.
22. The method of claim 15, further comprising adjusting, by a window controller circuit of the master computation circuit, the predetermined convolution window to select the one or more portions of the input data.
23. The method of claim 15, wherein the instruction is selected from the group consisting of a convolution network sigmoid derivative instruction, a convolution network tanh derivative instruction, a convolution network relu derivative instruction, and a convolution network softmax derivative instruction.
24. The method of claim 23, wherein the convolution network sigmoid derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a sigmoid function.
25. The method of claim 23, wherein the convolution network tanh derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a tanh function.
26. The method of claim 23, wherein the convolution network relu derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a relu function.
27. The method of claim 23, wherein the convolution network softmax derivative instruction includes an address of the first data gradients, a size of the first data gradients, an address of the portion of the convolution kernel, a size of the portion of the convolution kernel, and an indication of a derivative of a softmax function.
Patent Citations (10)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US5204938(A) | 1993-04-01 | Skapura | Examiner |
| US9153230(B2) | 2015-10-01 | Maaninen | Examiner |
| US2012/0300988(A1) | 2012-11-01 | Ivanov | Examiner |
| US2014/0313339(A1) | 2014-10-01 | Diessner | Examiner |
| US2015/0294219(A1) | 2015-10-01 | Krizhevsky | Applicant |
| US2016/0026912(A1) | 2016-01-01 | Falcon et al. | Applicant |
| CN103150596(A) | 2013-06-01 | Applicant | |
| CN104103033(A) | 2014-10-01 | Applicant | |
| CN104537393(A) | 2015-04-01 | Applicant | |
| WO2017/185391(A1) | 2017-11-01 | Applicant |
Non-Patent Literature (16)
- T. Chen, et al., “A Small-Footprint Accelerator for Large-Scale Neural Networks”, ACM Transactions on Computer Systems, vol. 33, No. 2, Article 6, May 2015, 27 pages.Applicant
- Z. Du, et al., “An Accelerator for High Efficient Vision Processing”, IEEE Transactions on Computer-aided Design of Integrated Circuits and System, vol. 36, No. 2, Feb. 2017, pp. 227-240.Applicant
- S. Liu, et al., “Cambricon: An Instruction Set Architecture for Neural Networks”, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture, Oct. 12, 2016, pp. 393-405.Applicant
- S. Zhang, et al., “Cambricon-X” An Accelerator for Sparse Neural Networks, The 49th Annual IEEE/ACM International Symposium on Microarchitecture Article No. 20, Oct. 15, 2016, 12 pages.Applicant
- Y. Chen, et al., “DaDianNao: A Machine-Learning Supercomputer”, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 13, 2014, pp. 609-622.Applicant
- T. Luo, et al., “DaDianNao: A Neural Network Supercomputer”, IEEE Transaction on Computers, vol. 66, No. 1, Jan. 2017, pp. 73-88.Applicant
- T. Chen, et al., “DianNao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning”, ASPLOS '14, Proceedings of the 19th international conference on Architectural support for programming languages and operating systems, Feb. 24, 2014, pp. 269-283.Applicant
- Y. Chen, et al., “DianNao Family: Energy-Efficient Hardware Accelerators for Machine Learning”, Communications of the ACM, vol. 59, No. 11, Nov. 2016, pp. 105-112.Applicant
- D. Liu, et al., “PuDianNao: A Polyvalent Machine Learning Accelerator”, ASPLOS '15 Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, Mar. 14, 2015, pp. 369-381.Applicant
- Z. Du, et al., “ShiDianNao: Shifting Vision Processing Closer to the Sensor”, ISCA '15 Proceedings of the 42nd Annual International Symposium on Computer Architecture, Jun. 13, 2015, pp. 92-104.Applicant
- Yang, Xin, “Traffic sign recognition research and application based on convolutional neural network,” Jul. 15, 2015, 1 page English Summary.Applicant
- EP 16899902.7, Official Action ESR dated Jan. 24, 2020, 7 Pages.Applicant
- Ramon J. Aliaga; System-on-Chip Implementation of Neural Network Training on FPGA_XP 55604241A; Institute for the Implementation of Advanced Information and Communication Technologies (ITACA); 2009; 12 Pages.Applicant
- Pedro O. Domingos; An Efficient and Scalable Architecture for Neural Networks With Backpropagation Learning, XP 55606447A; Dept. of Electrical and Computer Engineering, IST/INESC-ID, Portugal; 2005; 6 pages.Applicant
- ESR Received for Application No. EP 16899902.7, dated Nov. 25, 2019, 5 Pages.Applicant
- Invitation to file a copy of Search Results, Application No. EP16899907.7, dated Dec. 3, 2019, 1 Page.Applicant